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Dissertations / Theses on the topic 'Switching Fabric'
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1
Yu, Lianghong. "Performance of a ATM Lan switching fabric." Master's thesis, University of Cape Town, 1998. http://hdl.handle.net/11427/26109.
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This thesis provides a focus on the architecture of a high-speed packet switching fabric and its performance. The switching fabric is suited for existing transparent protocols, based on Asynchronous Transfer Mode (ATM) technology and standards in an environment of Local Area Network (LAN). A high-speed switching fabric architecture which adopts Time Division mode and bases on a shared medium approach is proposed. This is an architecture for nonblocking performance, no congestion and high reliability. Its principle for performance is a method of sequentially scheduling the inputs and the transferring of bits in parallel. To study the performance of the switching fabric architecture one uses OPNET communication simulation software. Some parameters including the throughputs, the transfer (the switching fabric) delay, the switching overflow and the packet size in the buffer (the input buffer and the output buffer) are implemented through the simulation. And finally, an analysis for the results of the simulation for local ATM IDS fabric architecture is discussed. The results display an architecture that provides a rational design with some expected characteristics.
2
Cao, Qi. "Buffer and scheduler design in high-speed switching fabric /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20CAO.
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Yan, Zhaohui. "Performance Analysis of A Banyan Based ATM Switching Fabric with Packet Priority." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/5199.
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Since the emergence of the Asynchronous Transfer Mode ( A TM ) concept, various switching architectures have been proposed. The multistage interconnection networks have been proposed for the switching architecture under the A TM environment. In this thesis, we propose a new model for the performance analysis of an A TM switching fabric based on single-buffered Banyan network. In this model, we use a three-state, i.e., "empty", "new" and "blocked" Markov chain model to describe the behavior of the buffer within a switching element. In addition to traditional statistical analysis including throughput and delay, we also examine the delay variation. Performance results show that the proposed model is more accurate in describing the switch behavior under uniform traffic environment in comparison with the "two-state" Markov chain model developed by Jenq, et. al.[4] [6] . Based on the "three-state" model, we study a packet priority scheme which gives the blocked packet higher priority to be routed forward during contention. It is found that the standard deviation of the network delay is reduced by about 30%.
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Bolla, Siddhartha. "Implementation of Virtual Circuits as a Switching fabric in Virtual Modularized Network." University of Toledo / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1272002016.
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Yeo, Yong-Kee. "Dynamically Reconfigurable Optical Buffer and Multicast-Enabled Switch Fabric for Optical Packet Switching." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14615.
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Optical packet switching (OPS) is one of the more promising solutions for meeting the diverse needs of broadband networking applications of the future. By virtue of its small data traffic granularity as well as its nanoseconds switching speed, OPS can be used to provide connection-oriented or connectionless services for different groups of users with very different networking requirements. The optical buffer and the switch fabric are two of the most important components in an OPS router. In this research, novel designs for the optical buffer and switch fabric are proposed and experimentally demonstrated. In particular, an optical buffer that is based on a folded-path delay-line tree architecture will be discussed. This buffer is the most compact non-recirculating optical delay line buffer to date, and it uses an array of high-speed ON-OFF optical reflectors to dynamically reconfigure its delay within several nanoseconds. A major part of this research is devoted to the design and performance optimization of these high-speed reflectors. Simulations and measurements are used to compare different reflector designs as well as to determine their optimal operating conditions. Another important component in the OPS router is the switch fabric, and it is used to perform space switching for the optical packets. Optical switch fabrics are used to overcome the limitations imposed by conventional electronic switch fabrics: high power consumption and dependency on the modulation format and bit-rate of the signals. Currently, only those fabrics that are based on the broadcast-and-select architecture can provide truly non-blocking multicast services to all input ports. However, a major drawback of these fabrics is that they are implemented using a large number of optical gates based on semiconductor optical amplifiers (SOA). This results in large component count and high energy consumption. In this research, a new multicast-capable switch fabric which does not require any SOA gates is proposed. This fabric relies on a passive all-optical gate that is based on the Four-wave mixing (FWM) wavelength conversion process in a highly-nonlinear fiber. By using this new switch architecture, a significant reduction in component count can be expected.
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Park, Jahng Sun. "The Folded Hypercube ATM Switches." Diss., Virginia Tech, 2001. http://hdl.handle.net/10919/29167.
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Over the past few years, many high performance asynchronous transfer mode (ATM) switches have been proposed. The majority of these switches have high performance but also high hardware complexity. Therefore, there is a need for switch designs with low complexity and high performance. This research proposes three new ATM switches based on the folded hypercube network (FHC). The performance of the three architectures are studied using a network model and simulation. The major performance parameters measured are the cell loss rate and cell delay time through the switch under uniform, normal, and bursty traffic patterns. To guarantee faster switching of time-sensitive cells, the routing algorithm of the three switches uses a priority scheme that gives higher precedence to the time-sensitive cells. Also, an output buffer controller is designed to manage the buffers in a fair manner. The three proposed switch architectures have lower complexity while providing equivalent or better switching performance compared to other more complex ATM switches described in the literature. This research shows a new approach to designing ATM switches by using the FHC as the switching fabric for the first time instead of using the crossbar, multi-path, or Banyan-based switching fabrics.Ph. D.
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Lamothe, Gilles. "Accelerated simulation of ATM switching fabrics." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/tape15/PQDD_0011/MQ38756.pdf.
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Gordon, D. L. "Scheduling in optically based ATM switching fabrics." Thesis, University of Cambridge, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.599531.
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The recent explosion in the application of networking technology in many environments and on many scales has been facilitated by advances in both electronic and optical technology. The use of optical fibre transmission has increased greatly the data capacity of networks and at the same time reduced their cost. The increase in speed and complexity and the reduction in cost associated with VLSI electronic technology has brought about cheaper and more intelligent network components. In particular, faster and denser electronic memory means that buffering within the network is now prevalent and the increased speed of electronic gates has enabled a finer granularity of switching. The multiplexing strategy, Asynchronous Transfer Mode (ATM), takes advantage of these developments to integrate a variety of high bandwidth streams onto a single network whilst minimising inter-stream interference. The growth in transmission bandwidth requirements can be met by the increased capacity of glass fibre, but optical technology is insufficiently advanced for the more complex tasks involved in switching. Unfortunately, the buffering and control of data are currently impractical in the optical domain. Interconnects, which form the basis of all communications switches, can benefit from optical technology, particularly where they are large. The reduced complexity of an optical solution has many advantages. However, when compared to their electronic counterparts, many of the components used to build such devices have a relatively long path reconfiguration period during which no data can be transferred and this can seriously reduce the usable bandwidth of the interconnect. This dissertation shows how and where optical components can best be used in the construction of a hybrid opto-electronic ATM switch. It shows how the large bandwidth associated with optical interconnects can be used to overcome the problems of matching inputs to outputs during the arbitration process. It describes three new scheduling schemes for such a switch that take into account the reconfiguration penalty. Simulations involving a single switch and two switches in series are performed to measure the effects the schemes have on throughput and delay, and a new switching strategy, based on these schemes, is proposed especially for switches constructed from optical components. Finally, a simulation of a passive optical network shows how the granularity of scheduling, and therefore the quantity of control information, in such systems can be reduced using a similar scheme.
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Hassen, Fadoua. "Multistage packet-switching fabrics for data center networks." Thesis, University of Leeds, 2017. http://etheses.whiterose.ac.uk/17620/.
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Recent applications have imposed stringent requirements within the Data Center Network (DCN) switches in terms of scalability, throughput and latency. In this thesis, the architectural design of the packet-switches is tackled in different ways to enable the expansion in both the number of connected endpoints and traffic volume. A cost-effective Clos-network switch with partially buffered units is proposed and two packet scheduling algorithms are described. The first algorithm adopts many simple and distributed arbiters, while the second approach relies on a central arbiter to guarantee an ordered packet delivery. For an improved scalability, the Clos switch is build using a Network-on-Chip (NoC) fabric instead of the common crossbar units. The Clos-UDN architecture made with Input-Queued (IQ) Uni-Directional NoC modules (UDNs) simplifies the input line cards and obviates the need for the costly Virtual Output Queues (VOQs). It also avoids the need for complex, and synchronized scheduling processes, and offers speedup, load balancing, and good path diversity. Under skewed traffic, a reliable micro load-balancing contributes to boosting the overall network performance. Taking advantage of the NoC paradigm, a wrapped-around multistage switch with fully interconnected Central Modules (CMs) is proposed. The architecture operates with a congestion-aware routing algorithm that proactively distributes the traffic load across the switching modules, and enhances the switch performance under critical packet arrivals. The implementation of small on-chip buffers has been made perfectly feasible using the current technology. This motivated the implementation of a large switching architecture with an Output-Queued (OQ) NoC fabric. The design merges assets of the output queuing, and NoCs to provide high throughput, and smooth latency variations. An approximate analytical model of the switch performance is also proposed. To further exploit the potential of the NoC fabrics and their modularity features, a high capacity Clos switch with Multi-Directional NoC (MDN) modules is presented. The Clos-MDN switching architecture exhibits a more compact layout than the Clos-UDN switch. It scales better and faster in port count and traffic load. Results achieved in this thesis demonstrate the high performance, expandability and programmability features of the proposed packet-switches which makes them promising candidates for the next-generation data center networking infrastructure.
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Wassal, A. G. "Traffic-driven low-power design and modeling of VLSI satellite switching fabrics." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0021/NQ53523.pdf.
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Chen, Wen-Shyen E. "Design and analysis of high-speed packet switching fabrics for integrated broadband networks /." The Ohio State University, 1991. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487687959967612.
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Ho, Kwongchoi Caisy. "Possibility of positive-pulse switching in systems of nonlinear Fabry-Perot cavities." Diss., Virginia Tech, 1991. http://hdl.handle.net/10919/39427.
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The conventional way of using a nonlinear Fabry-Perot cavity as an optical memory requires a negative pulse input to reset the state of the cavity. The possibility of using positive pulses to turn a system of nonlinear Fabry-Perot cavities on and off is studied and it was found that positive pulse switching is possible in a system of two coupled nonlinear cavities.
First, Korpel and Lohmann's proposal of using polarization switching in a single nonlinear birefringent cavity was studied. After a detailed investigation of their proposal it was found that positive pulse switching in a single nonlinear Fabry-Perot cavity is not possible. One of the reasons is that the eigen-polarization states of the output of a nonlinear Fabry-Perot cavity cannot be switched independently. Although it is not possible to switch a single nonlinear Fabry-Perot cavity with positive pulses we were able to use the coupling of the eigen-polarization states to implement other kinds of optical switches which were demonstrated experimentally. The cross-talk effect in a metallic Fabry-Perot cavity was also studied.
Next, a steady state model of a system of two coupled nonlinear Fabry-Perot cavities was developed and it was found that positive pulse switching is possible in such a system. The output can be turned on and off either by pulses sent into different cavities or by pulses of different magnitudes sent into one cavity.
Finally, the dynamic behavior of the coupled cavities system was modeled by extending Goldstone and Garmire's model of a single cavity with one input to a system of two coupled cavities with two inputs. We verified by numerical calculations that positive pulse switching is also possible in the dynamic regime.Ph. D.
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Neves, Fabio Schittler Verfasser], Marc [Akademischer Betreuer] Timme, Florentin [Akademischer Betreuer] Wörgötter, and Theo [Akademischer Betreuer] [Geisel. "Universal Computation and Memory by Neural Switching / Fabio Schittler Neves. Gutachter: Marc Timme ; Florentin Wörgötter ; Theo Geisel. Betreuer: Marc Timme." Göttingen : Niedersächsische Staats- und Universitätsbibliothek Göttingen, 2011. http://d-nb.info/1042304882/34.
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Weng, Chien-hung, and 翁健宏. "A Multiple I/O Delta Network Based Multicast Switching Fabric." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/60927941433582494320.
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碩士國立中興大學
資訊科學研究所
87
While rapidly developing in wide variety of multimedia applications on Internet, the requirements for the capabilities of high-bandwidth, high-throughput and high processing in the design of network facilities are needed. Switching systems, which support the transport function from traditional unicast traffic to currently heavy loading multicast / broadcast traffic, are playing a key role in the communication network. In this thesis, we study a high performance architecture of multiple I/O Delta network based multicast switching fabric in which packets are delivered on parallel-in-parallel-out path between the switching elements, and also propose a new routing method according to our switching system. Before being delivered into switching system, the packet is attached a tag (we named it - Multicast Tag) in front of it, which unicast or multicast addresses of this packet are translated into it. Each switching element refers its relative address in Delta network and the tag of packet been delivered to determine the routing path. Packets will be transferred to their destination port without needing additional processing unit to handle the copy function of multicast, and will only pass through the Delta network once during packet transferring. Finally, we propose an analytical model for our switching system and use a simulation program to evaluate its performance.
15
Lee, Young, and 李揚. "Design and Implementation of Switching Fabric for Multi- subsystem Interconnection." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/73461527935036989463.
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碩士國立交通大學
電信研究所
82
Communication nodes are typically composed of multiple subsystems,each performing designated functions such as LAN interface, routing,format conversion, and high-level applications , etc.. Multiple subsystems are tightly coupled together to achieve the aggregated system functions and objectives by exchanging data and controls. Conventional backplane buses are uneffective means for the interconnection of multiple subsystems in broadband communication nodes,such as local ATM switches and super-hubs in Local Area Networks(LANs), because of the bandwidth inadequacy and physical distance constraint. The Multi-subsystem Interconnect(MSI)is intended as a scalable platform to facilitate the physical coupling and information exchange among multiple subsystems. The MSI is based on the fast-packet switching. Implemented on backplanes, it provides virtual channels for switching of level-2 information in sybsystems' memories , which are sent in 53 bytes packets by the MSI in hardware. The core of the MSI consists of a switching fabric and its control. The structure of the switching fabric provides multiple paths into each destination. Multi-cast is the inherent property of the fabric. Routing controls of packets are skewed to the switching fabric control one packet-time ahead. This pipe-line approach time constraint in performing any conflict resolutions,resulting simple logic design of the switching fabric control. The MSI subsystems will be highly reusable, in addition to having overhead-free communication and flexible physical interconnection capabilities. The MSI applications include local ATM switches, LAN superhubs, high performance bridges/ routers, and broadband bandwidth managers.
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Matthews, William B. "Fabric-on-a-Chip: Toward Consolidating Packet Switching Functions on Silicon." 2007. http://trace.tennessee.edu/utk_graddiss/239.
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The switching capacity of an Internet router is often dictated by the memory bandwidth required to bu¤er arriving packets. With the demand for greater capacity and improved service provisioning, inherent memory bandwidth limitations are encountered rendering input queued (IQ) switches and combined input and output queued (CIOQ) architectures more practical. Output-queued (OQ) switches, on the other hand, offer several highly desirable performance characteristics, including minimal average packet delay, controllable Quality of Service (QoS) provisioning and work-conservation under any admissible traffic conditions. However, the memory bandwidth requirements of such systems is O(NR), where N denotes the number of ports and R the data rate of each port. Clearly, for high port densities and data rates, this constraint dramatically limits the scalability of the switch.
In an effort to retain the desirable attributes of output-queued switches, while significantly reducing the memory bandwidth requirements, distributed shared memory architectures, such as the parallel shared memory (PSM) switch/router, have recently received much attention. The principle advantage of the PSM architecture is derived from the use of slow-running memory units operating in parallel to distribute the memory bandwidth requirement. At the core of the PSM architecture is a memory management algorithm that determines, for each arriving packet, the memory unit in which it will be placed. However, to date, the computational complexity of this algorithm is O(N), thereby limiting the scalability of PSM switches.
In an effort to overcome the scalability limitations, it is the goal of this dissertation to extend existing shared-memory architecture results while introducing the notion of Fabric on a Chip (FoC). In taking advantage of recent advancements in integrated circuit technologies, FoC aims to facilitate the consolidation of as many packet switching functions as possible on a single chip. Accordingly, this dissertation introduces a novel pipelined memory management algorithm, which plays a key role in the context of on-chip output- queued switch emulation. We discuss in detail the fundamental properties of the proposed scheme, along with hardware-based implementation results that illustrate its scalability and performance attributes.
To complement the main effort and further support the notion of FoC, we provide performance analysis of output queued cell switches with heterogeneous traffic. The result is a flexible tool for obtaining bounds on the memory requirements in output queued switches under a wide range of tra¢ c scenarios. Additionally, we present a reconfigurable high-speed hardware architecture for real-time generation of packets for the various traffic scenarios. The work presented in this thesis aims at providing pragmatic foundations for designing next-generation, high-performance Internet switches and routers.
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Matthews, William Brad. "Fabric-on-a-Chip toward consolidating packet switching functions on silicon /." 2007. http://etd.utk.edu/2007/MatthewsBrad.pdf.
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Lin, Chien-Yung, and 林千詠. "Investigation on Switching Characteristics of CNT Fabric RRAM Deposited by Electrophoretic Deposition." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/585eb4.
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Chao, Kuang-Hsiang, and 趙廣祥. "Implementation and Simulation of 8 Ports Gigabit NTU-II Switch: Switching Fabric and Output Stage." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/46131423042021937295.
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碩士國立臺灣大學
電信工程學研究所
91
Abstract In this paper, a multi-plane cross-bar switch called NTU-II switch is proposed and implemented. This switch has the following features: 1) Asynchronous operation mode 2) Modular design to achieve high scalability 3) Handling Ethernet variable length packet directly without fragmentation and recombination. 4) Self Routing without central controller 5) Non-blocking Compared to the NTU-I switch proposed previously, there are two major improvements. One is the use of request-polling handshaking protocol to transfer packets between internal circuits. It reduces the transmission latency in the switch. The other is channel grouping to partition whole switch into smaller sub-switches. It makes the implementation easier when we want to increase the switch I/O ports while hardware resources such as I/O pins, memories are limited. The former builds a simple interface between circuits, and the latter makes modular design more feasible. Because there are four planes in a sub-switch, simulation based on mathematical model shows that the throughput can reach 100% in geometric arrival, uniform distribution traffic. This result shows that the proposed switch compares favorably with the output-queue switch. The NTU-II switch is composed of preprocessors, sequencers, switching elements, and the output memory management units. An 8x8 switch with line rate 1 Gb/s is implemented using FPGA ( xc2v3000-4 fg676, Xilinx Corp. ).
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"Implementation considerations of algebraic switching fabrics." 2002. http://library.cuhk.edu.hk/record=b6073472.
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by Zhu Jian."May 2002."
Thesis (Ph.D.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (p. 162-170).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Mode of access: World Wide Web.
Abstracts in English and Chinese.
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Tsaur, Ding-Jyh, and 曹定智. "Scheduling Algorithms and Performance Evaluation of High-Speed Switching Fabrics." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/53706711092318457256.
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博士國立中興大學
資訊科學系
94
This work studies scheduling algorithms and evaluates the performance of high-speed electronic and photonic switching systems. A novel architecture for three-dimensional Virtual Output Queue (3D-VOQ) switches is proposed for use in electronic switching systems, in connection with a scheduling algorithm to improve the competitive transfer of service. This 3D-VOQ switch, which exactly emulates an output-queued switch with a broad class of service scheduling algorithms, requires no speedup, independently of its incoming traffic pattern and switch size. First, an N×N 3D-VOQ switch is proposed. In this contention-free architecture, the head-of-line problems are eliminated using a few virtual output queues (VOQ) from input ports and the output sides were arranged using sufficient separate queues. Next, a Small Time-to-leave Cell First (STCF) algorithm is proposed to generate a stable many-to-many assignment. The proposed 3D-VOQ switch is demonstrated to be able to mimic an exact OQ switch. Finally, analysis and simulation confirm the performance of 3D-VOQ and its satisfying high/low QoS requirements. The photonic switching system applies a threshold-based matching algorithm for Clos (t-MAC) network switches. The studied Clos network uses a central photonic switch fabric for transporting high-speed optical signals and electronic controllers at the input and output ports. The proposed matching algorithm can be used to solve the scheduling problems associated with the Clos network. The matching algorithm incorporates cut-through transmission, variable-threshold adjustment and preemptive scheduling. The performance is evaluated using the bursty and unbalanced traffic model, and simulation results obtained by t-MAC are presented. The results indicate that the proposed algorithm significantly reduces switching latency by approximately 45 to 36 % below that of Chao’s c-MAC.
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WANG, RUI-TENG, and 王瑞騰. "Queueing behavior of several ATM switching fabrics under hot-spot nonuniform traffic." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/32210585616745425146.
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Lin, Yi-Ying, and 林易穎. "Design and Implementation of Switching Fabrics and Fault-tolerant I/O interfaces in AdvancedTCA based Load Balanced Birkhoff-von Neumann Switches." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/03459800571480633339.
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