Academic literature on the topic 'Synchrous dataflow graph'

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Journal articles on the topic "Synchrous dataflow graph"

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Damavandpeyma, Morteza, Sander Stuijk, Twan Basten, Marc Geilen, and Henk Corporaal. "Schedule-Extended Synchronous Dataflow Graphs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 10 (2013): 1495–508. http://dx.doi.org/10.1109/tcad.2013.2265852.

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Chukhman, Ilya, Shuoxin Lin, William Plishker, Chung-Ching Shen, and Shuvra S. Bhattacharyya. "Instrumentation-Driven Model Detection and Actor Partitioning for Dataflow Graphs." International Journal of Embedded and Real-Time Communication Systems 4, no. 1 (2013): 1–21. http://dx.doi.org/10.4018/jertcs.2013010101.

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Dataflow modeling offers a myriad of tools to improve optimization and analysis of signal processing applications, and is often used by designers to help design, implement, and maintain systems on chip for signal processing. However, maintaining and upgrading legacy systems that were not originally designed using dataflow methods can be challenging. Designers often convert legacy code to dataflow graphs by hand, a process that can be difficult and time consuming. In this paper, the authors developed a method to facilitate this conversion process by automatically detecting the dataflow models of the core functions from bodies of legacy code. They focus first on detecting static dataflow models, such as homogeneous and synchronous dataflow, and then present an extension that can also detect dynamic dataflow models. Building on the authors’ algorithms for dataflow model detection, they present an iterative actor partitioning process that can be used to partition complex actors into simpler sub-functions that are more prone to analysis techniques.
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Ma, Mingze, and Rizos Sakellariou. "Code-size-aware Scheduling of Synchronous Dataflow Graphs on Multicore Systems." ACM Transactions on Embedded Computing Systems 20, no. 3 (2021): 1–24. http://dx.doi.org/10.1145/3440034.

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Synchronous dataflow graphs are widely used to model digital signal processing and multimedia applications. Self-timed execution is an efficient methodology for the analysis and scheduling of synchronous dataflow graphs. In this article, we propose a communication-aware self-timed execution approach to solve the problem of scheduling synchronous dataflow graphs on multicore systems with communication delays. Based on this communication-aware self-timed execution approach, four communication-aware scheduling algorithms are proposed using different allocation rules. Furthermore, a code-size-aware mapping heuristic is proposed and jointly used with a proposed scheduling algorithm to reduce the code size of SDFGs on multicore systems. The proposed scheduling algorithms are experimentally evaluated and found to perform better than existing algorithms in terms of throughput and runtime for several applications. The experiments also show that the proposed code-size-aware mapping approach can achieve significant code size reduction with limited throughput degradation in most cases.
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Hsu, Chia-Jui, José Luis Pino, and Shuvra S. Bhattacharyya. "Multithreaded Simulation for Synchronous Dataflow Graphs." ACM Transactions on Design Automation of Electronic Systems 16, no. 3 (2011): 1–23. http://dx.doi.org/10.1145/1970353.1970358.

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Hsu, Chia-Jui, Ming-Yung Ko, Shuvra S. Bhattacharyya, Suren Ramasubbu, and José Luis Pino. "Efficient simulation of critical synchronous dataflow graphs." ACM Transactions on Design Automation of Electronic Systems 12, no. 3 (2007): 1–28. http://dx.doi.org/10.1145/1255456.1255458.

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Bhattacharyya, Shuvra S., and Edward A. Lee. "Scheduling synchronous dataflow graphs for efficient looping." Journal of VLSI signal processing systems for signal, image and video technology 6, no. 3 (1993): 271–88. http://dx.doi.org/10.1007/bf01608539.

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Kapre, Nachiket, and André Dehon. "An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads." International Journal of Reconfigurable Computing 2011 (2011): 1–14. http://dx.doi.org/10.1155/2011/745147.

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Parallel graph-oriented applications expressed in the Bulk-Synchronous Parallel (BSP) and Token Dataflow compute models generate highly-structured communication workloads from messages propagating along graph edges. We can statially expose this structure to traffic compilers and optimization tools to reshape and reduce traffic for higher performance (or lower area, lower energy, lower cost). Such offline traffic optimization eliminates the need for complex, runtime NoC hardware and enables lightweight, scalable NoCs. We perform load balancing, placement, fanout routing, and fine-grained synchronization to optimize our workloads for large networks up to 2025 parallel elements for BSP model and 25 parallel elements for Token Dataflow. This allows us to demonstrate speedups between 1.2× and 22× (3.5× mean), area reductions (number of Processing Elements) between 3× and 15× (9× mean) and dynamic energy savings between 2× and 3.5× (2.7× mean) over a range of real-world graph applications in the BSP compute model. We deliver speedups of 0.5–13× (geomean 3.6×) for Sparse Direct Matrix Solve (Token Dataflow compute model) applied to a range of sparse matrices when using a high-quality placement algorithm. We expect such traffic optimization tools and techniques to become an essential part of the NoC application-mapping flow.
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Groote, Robert De, Philip K. F. Hölzenspies, Jan Kuper, and Gerard J. M. Smit. "Incremental Analysis of Cyclo-Static Synchronous Dataflow Graphs." ACM Transactions on Embedded Computing Systems 14, no. 4 (2015): 1–26. http://dx.doi.org/10.1145/2792981.

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Bodin, Bruno, and Alix Munier Kordon. "Evaluation of the Exact Throughput of a Synchronous DataFlow Graph." Journal of Signal Processing Systems 93, no. 9 (2021): 1007–26. http://dx.doi.org/10.1007/s11265-021-01649-z.

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Bennour, Imed Eddine. "Formal verification of timed synchronous dataflow graphs using Lustre." Journal of Logical and Algebraic Methods in Programming 121 (June 2021): 100678. http://dx.doi.org/10.1016/j.jlamp.2021.100678.

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Dissertations / Theses on the topic "Synchrous dataflow graph"

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Klikpo, Enagnon Cédric. "Méthode de conception de systèmes temps réels embarqués multi-coeurs en milieu automobile." Thesis, Sorbonne université, 2018. http://www.theses.fr/2018SORUS033/document.

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La complexité croissante des applications embarquées dans les voitures modernes augmente le besoin de puissance de calcul. Pour répondre à ce besoin, le standard automobile AUTOSAR introduit l'utilisation de plates-formes multi-cœurs. Cependant, l'utilisation du multi-cœurs pour des applications temps-réel critique automobile soulève plusieurs problématiques. Notamment, il faut respecter la spécification fonctionnelle et garantir de manière déterministe les échanges de données entre cœurs. Dans cette thèse, nous considérons des systèmes multi-périodiques spécifiés et validés fonctionnellement avec des modèles Matlab/Simulink. Ainsi, nous avons développé un framework pour déployer des applications Matlab/Simulink sur AUTOSAR multi-cœurs afin de garantir le déterminisme fonctionnel et temporel tout en exploitant au mieux le parallélisme. Notre contribution a porté sur trois axes. Premièrement nous avons identifié les mécanismes d'échanges de données imposés dans le modèle fonctionnel Matlab/Simulink. Nous avons montré que ces mécanismes pouvaient s'exprimer en utilisant le formalisme des Synchronous Dataflow Graph (SDFG). Ce modèle est un excellent outil d'analyse pour exploiter le parallélisme car il est très populaire dans la littérature et largement étudié pour le déploiement d'applications flow de données sur plateforme multi/many-cœurs. Par la suite, nous avons développé des méthodes pour réaliser le flux de données exprimés par le SDFG dans un ordonnancement temps-réel préemptif. Ces méthodes utilisent des résultats théoriques sur les SDFGs pour garantir les contraintes de précédence de manière déterministe sans utiliser des mécanismes de synchronisation bloquants. De cette sorte, nous garantissons à la fois le déterminisme fonctionnel et temporel des applications. Finalement, nous caractérisons l'impact des contraintes de flux de données sur l'ordonnancement des tâches. Nous proposons une technique de partitionnement qui minimise cet impact. Nous montrons alors que cette technique favorise la construction d'un partitionnement et d'un ordonnancement lorsqu'elle est utilisée pour initialiser des algorithmes de recherche et d'optimisation heuristiques<br>The increasing complexity of embedded applications in modern cars has increased the need of computing power. To meet this need, the European automotive standard AUTOSAR has introduced the use of \multicore platforms. However, \multicore platform for critical automotive applications raises several issues. In particular, it is necessary to respect the functional specification and to guarantee deterministically the data exchanges between cores. In this thesis, we consider multi-periodic systems specified and validated with \mat. So, we developed a framework to deploy \mat applications on AUTOSAR \multicore. This framework guarantees the functional and temporal determinism and exploits the parallelism. Our contribution is threefold. First, we identify the communication mechanisms in \mat. Then, we prove that the dataflow in a multi-periodic \mat system is modeled by a SDFG. The SDFG formalism is an excellent analysis tool to exploit the parallelism. In fact, it is very popular in the literature and it is widely studied for the deployment of dataflow applications on multi/many-core. Then, we develop methods to realize the dataflow expressed by the SDFG in a preemptive \rt scheduling. These methods use theoretical results on SDFGs to guarantee deterministic precedence constraints without using blocking synchronization mechanisms. As such, both the functional and temporal determinism are guaranteed. Finally, we characterize the impact of dataflow requirements on tasks. We propose a partitioning technique that minimizes this impact. We show that this technique promotes the construction of a partitioning and a feasible scheduling when it is used to initiate multi-objective research and optimization algorithms. %As such, we reduce the number of design iterations and shorten the design time
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Klikpo, Enagnon Cédric. "Méthode de conception de systèmes temps réels embarqués multi-coeurs en milieu automobile." Electronic Thesis or Diss., Sorbonne université, 2018. http://www.theses.fr/2018SORUS033.

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La complexité croissante des applications embarquées dans les voitures modernes augmente le besoin de puissance de calcul. Pour répondre à ce besoin, le standard automobile AUTOSAR introduit l'utilisation de plates-formes multi-cœurs. Cependant, l'utilisation du multi-cœurs pour des applications temps-réel critique automobile soulève plusieurs problématiques. Notamment, il faut respecter la spécification fonctionnelle et garantir de manière déterministe les échanges de données entre cœurs. Dans cette thèse, nous considérons des systèmes multi-périodiques spécifiés et validés fonctionnellement avec des modèles Matlab/Simulink. Ainsi, nous avons développé un framework pour déployer des applications Matlab/Simulink sur AUTOSAR multi-cœurs afin de garantir le déterminisme fonctionnel et temporel tout en exploitant au mieux le parallélisme. Notre contribution a porté sur trois axes. Premièrement nous avons identifié les mécanismes d'échanges de données imposés dans le modèle fonctionnel Matlab/Simulink. Nous avons montré que ces mécanismes pouvaient s'exprimer en utilisant le formalisme des Synchronous Dataflow Graph (SDFG). Ce modèle est un excellent outil d'analyse pour exploiter le parallélisme car il est très populaire dans la littérature et largement étudié pour le déploiement d'applications flow de données sur plateforme multi/many-cœurs. Par la suite, nous avons développé des méthodes pour réaliser le flux de données exprimés par le SDFG dans un ordonnancement temps-réel préemptif. Ces méthodes utilisent des résultats théoriques sur les SDFGs pour garantir les contraintes de précédence de manière déterministe sans utiliser des mécanismes de synchronisation bloquants. De cette sorte, nous garantissons à la fois le déterminisme fonctionnel et temporel des applications. Finalement, nous caractérisons l'impact des contraintes de flux de données sur l'ordonnancement des tâches. Nous proposons une technique de partitionnement qui minimise cet impact. Nous montrons alors que cette technique favorise la construction d'un partitionnement et d'un ordonnancement lorsqu'elle est utilisée pour initialiser des algorithmes de recherche et d'optimisation heuristiques<br>The increasing complexity of embedded applications in modern cars has increased the need of computing power. To meet this need, the European automotive standard AUTOSAR has introduced the use of \multicore platforms. However, \multicore platform for critical automotive applications raises several issues. In particular, it is necessary to respect the functional specification and to guarantee deterministically the data exchanges between cores. In this thesis, we consider multi-periodic systems specified and validated with \mat. So, we developed a framework to deploy \mat applications on AUTOSAR \multicore. This framework guarantees the functional and temporal determinism and exploits the parallelism. Our contribution is threefold. First, we identify the communication mechanisms in \mat. Then, we prove that the dataflow in a multi-periodic \mat system is modeled by a SDFG. The SDFG formalism is an excellent analysis tool to exploit the parallelism. In fact, it is very popular in the literature and it is widely studied for the deployment of dataflow applications on multi/many-core. Then, we develop methods to realize the dataflow expressed by the SDFG in a preemptive \rt scheduling. These methods use theoretical results on SDFGs to guarantee deterministic precedence constraints without using blocking synchronization mechanisms. As such, both the functional and temporal determinism are guaranteed. Finally, we characterize the impact of dataflow requirements on tasks. We propose a partitioning technique that minimizes this impact. We show that this technique promotes the construction of a partitioning and a feasible scheduling when it is used to initiate multi-objective research and optimization algorithms. %As such, we reduce the number of design iterations and shorten the design time
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Lesparre, Youen. "Evaluation de l'affectation des tâches sur une architecture à mémoire distribuée pour des modèles flot de données." Thesis, Paris 6, 2017. http://www.theses.fr/2017PA066086/document.

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Avec l'augmentation de l'utilisation des smartphones, des objets connectés et des véhicules automatiques, le domaine des systèmes embarqués est devenu omniprésent dans notre environnement. Ces systèmes sont souvent contraints en terme de consommation et de taille. L'utilisation des processeurs many-cores dans des systèmes embarqués permet une conception rapide tout en respectant des contraintes temps-réels et en conservant une consommation énergétique basse.Exécuter une application sur un processeur many-core requiert un dispatching des tâches appelé problème de mapping et est connu comme étant NP-complet.Les contributions de cette thèse sont divisées en trois parties :Tout d'abord, nous étendons d'importantes propriétés dataflow au modèle Phased Computation Graph.Ensuite, nous présentons un générateur de graphe dataflow capable de générer des Synchonous Dataflow Graphs, Cyclo-Static Dataflow Graphs et Phased Computation Graphs vivant avec plus de 10000 tâches en moins de 30 secondes. Le générateur est comparé à SDF3 et PREESM.Enfin, la contribution majeure de cette thèse propose une nouvelle méthode d'évaluation d'un mapping en utilisant les modèles Synchonous Dataflow Graphe et Cyclo-Static Dataflow Graphe. La méthode évalue efficacement la mémoire consommée par les communications d'un dataflow mappé sur une architecture à mémoire distribuée. L'évaluation est déclinée en deux versions, la première garantit la vivacité alors que la seconde ajoute une contrainte de débit. La méthode d'évaluation est expérimentée avec des dataflow générés par Turbine et avec des applications réelles<br>With the increasing use of smart-phones, connected objects or automated vehicles, embedded systems have become ubiquitous in our living environment. These systems are often highly constrained in terms of power consumption and size. They are more and more implemented with many-core processor array that allow, rapid design to meet stringent real-time constraints while operating at relatively low frequency, with reduced power consumption.Running an application on a processor array requires dispatching its tasks on the processors in order to meet capacity and performance constraints. This mapping problem is known to be NP-complete.The contributions of this thesis are threefold:First we extend important notions from the Cyclo-Static Dataflow Graph to the Phased Computation Graph model and two equivalent sufficient conditions of liveness.Second, we present a random dataflow graph generator able to generate Synchonous Dataflow Graphs, Cyclo-Static Dataflow Graphs and Phased Computation Graphs. The Generator, is able to generate live dataflow of up to 10,000 tasks in less than 30 seconds. It is compared with SDF3 and PREESM.Third and most important, we propose a new method of evaluation of a mapping using the Synchonous Dataflow Graph and the Cyclo-Static Dataflow Graph models. The method evaluates efficiently the memory footprint of the communications of a dataflow graph mapped on a distributed architecture. The evaluation is declined in two versions, the first guarantees a live mapping while the second accounts for a constraint on throughput.The evaluation method is experimented on dataflow graphs from Turbine and on real-life applications
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Koecher, Matthew R. "Hardware Synthesis of Synchronous Data Flow Models." BYU ScholarsArchive, 2004. https://scholarsarchive.byu.edu/etd/20.

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Synchronous Dataflow (SDF) graphs are a convenient way to represent many signal processing and dataflow operations. Nodes within SDF graphs represent computation while arcs represent dependencies between nodes. Using a graph representation, SDF graphs formally specify a dataflow algorithm without any assumptions on the final implementation. This allows an SDF model to be synthesized into a variety of implementation techniques including both software and hardware. This thesis presents a technique for generating an abstract hardware representation from SDF models. The techniques presented here operate on SDF models defined structurally within the Ptolemy modeling environment. The behavior of the nodes within Ptolemy SDF models is specified in software and can be simple, such as a single arithmetic operation, or arbitrarily complex. This thesis presents a technique for extracting the behavior of a limited class of SDF nodes defined in software and generating a structural description of the SDF model based on primitive arithmetic and logical operations. This synthesized graph can be used for subsequent hardware synthesis transformations.
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Lesparre, Youen. "Evaluation de l'affectation des tâches sur une architecture à mémoire distribuée pour des modèles flot de données." Electronic Thesis or Diss., Paris 6, 2017. http://www.theses.fr/2017PA066086.

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Avec l'augmentation de l'utilisation des smartphones, des objets connectés et des véhicules automatiques, le domaine des systèmes embarqués est devenu omniprésent dans notre environnement. Ces systèmes sont souvent contraints en terme de consommation et de taille. L'utilisation des processeurs many-cores dans des systèmes embarqués permet une conception rapide tout en respectant des contraintes temps-réels et en conservant une consommation énergétique basse.Exécuter une application sur un processeur many-core requiert un dispatching des tâches appelé problème de mapping et est connu comme étant NP-complet.Les contributions de cette thèse sont divisées en trois parties :Tout d'abord, nous étendons d'importantes propriétés dataflow au modèle Phased Computation Graph.Ensuite, nous présentons un générateur de graphe dataflow capable de générer des Synchonous Dataflow Graphs, Cyclo-Static Dataflow Graphs et Phased Computation Graphs vivant avec plus de 10000 tâches en moins de 30 secondes. Le générateur est comparé à SDF3 et PREESM.Enfin, la contribution majeure de cette thèse propose une nouvelle méthode d'évaluation d'un mapping en utilisant les modèles Synchonous Dataflow Graphe et Cyclo-Static Dataflow Graphe. La méthode évalue efficacement la mémoire consommée par les communications d'un dataflow mappé sur une architecture à mémoire distribuée. L'évaluation est déclinée en deux versions, la première garantit la vivacité alors que la seconde ajoute une contrainte de débit. La méthode d'évaluation est expérimentée avec des dataflow générés par Turbine et avec des applications réelles<br>With the increasing use of smart-phones, connected objects or automated vehicles, embedded systems have become ubiquitous in our living environment. These systems are often highly constrained in terms of power consumption and size. They are more and more implemented with many-core processor array that allow, rapid design to meet stringent real-time constraints while operating at relatively low frequency, with reduced power consumption.Running an application on a processor array requires dispatching its tasks on the processors in order to meet capacity and performance constraints. This mapping problem is known to be NP-complete.The contributions of this thesis are threefold:First we extend important notions from the Cyclo-Static Dataflow Graph to the Phased Computation Graph model and two equivalent sufficient conditions of liveness.Second, we present a random dataflow graph generator able to generate Synchonous Dataflow Graphs, Cyclo-Static Dataflow Graphs and Phased Computation Graphs. The Generator, is able to generate live dataflow of up to 10,000 tasks in less than 30 seconds. It is compared with SDF3 and PREESM.Third and most important, we propose a new method of evaluation of a mapping using the Synchonous Dataflow Graph and the Cyclo-Static Dataflow Graph models. The method evaluates efficiently the memory footprint of the communications of a dataflow graph mapped on a distributed architecture. The evaluation is declined in two versions, the first guarantees a live mapping while the second accounts for a constraint on throughput.The evaluation method is experimented on dataflow graphs from Turbine and on real-life applications
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Sinha, Ashmita. "Mutli-objective trade-off exploration for Cyclo-Static and Synchronous Dataflow graphs." Thesis, 2012. http://hdl.handle.net/2152/ETD-UT-2012-08-5995.

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Many digital signal processing and real-time streaming systems are modeled using dataflow graphs, such as Synchronous Dataflow (SDF) and Cyclo-static Dataflow (CSDF) graphs that allow static analysis and optimization techniques. However, mapping of such descriptions into tightly constrained real-time implementations requires optimization of resource sharing, buffering and scheduling across a multi-dimensional latency-throughput-area objective space. This requires techniques that can find the Pareto-optimal set of implementations for the designer to choose from. In this work, we address the problem of multi-objective mapping and scheduling of SDF and CSDF graphs onto heterogeneous multi-processor platforms. Building on previous work, this thesis extends existing two-stage hybrid heuristics that combine an evolutionary algorithm with an integer linear programming (ILP) model to jointly optimize throughput, area and latency for SDF graphs. The primary contributions of this work include: (1) extension of the ILP model to support CSDFGs with additional buffer size optimizations; (2) a further optimization in the ILP-based scheduling model to achieve a runtime speedup of almost a factor of 10 compared to the existing SDFG formulation; (3) a list scheduling heuristic that replaces the ILP model in the hybrid heuristic to generate Pareto-optimal solutions at significantly decreased runtime while maintaining near-optimality of the solutions within an acceptable gap of 10% when compared to its ILP counterparts. The list scheduling heuristic presented in this work is based on existing modulo scheduling approaches for software pipelining in the compiler domain, but has been extended by introducing a new concept of mobility-based rescheduling before resorting to backtracking. It has been proved in this work that if mobility-based rescheduling is performed, the number of required backtrackings and hence overall complexity and runtime is less.<br>text
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Book chapters on the topic "Synchrous dataflow graph"

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Ha, Soonhoi, and Hyunok Oh. "Decidable Signal Processing Dataflow Graphs: Synchronous and Cyclo-Static Dataflow Graphs." In Handbook of Signal Processing Systems. Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6345-1_30.

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Glanon, Philippe, Selma Azaiez, and Chokri Mraidha. "Estimating Latency for Synchronous Dataflow Graphs Using Periodic Schedules." In Lecture Notes in Computer Science. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-35092-5_6.

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Edwards, Martyn, and Peter Green. "The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44614-1_78.

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Honorat, Alexandre, Karol Desnos, Maxime Pelcat, and Jean-François Nezan. "Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs." In Lecture Notes in Computer Science. Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-27562-4_19.

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Ma, Mingze, and Rizos Sakellariou. "Buffer Minimization for Rate-Optimal Scheduling of Synchronous Dataflow Graphs on Multicore Systems." In Algorithms and Architectures for Parallel Processing. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-49583-5_25.

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Conference papers on the topic "Synchrous dataflow graph"

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Geilen, Marc. "Reduction techniques for synchronous dataflow graphs." In the 46th Annual Design Automation Conference. ACM Press, 2009. http://dx.doi.org/10.1145/1629911.1630146.

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Hsu, Chia-Jui, José Luis Pino, and Shuvra S. Bhattacharyya. "Multithreaded simulation for synchronous dataflow graphs." In the 45th annual conference. ACM Press, 2008. http://dx.doi.org/10.1145/1391469.1391553.

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Kanur, Sudeep, Johan Lilius, and Johan Ersfolk. "Detecting data-parallel synchronous dataflow graphs." In 2017 Conference on Design and Architectures for Signal and Image Processing (DASIP). IEEE, 2017. http://dx.doi.org/10.1109/dasip.2017.8122118.

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Zhu, Xue-Yang. "Efficient Retiming of Unfolded Synchronous Dataflow Graphs." In 2019 24th International Conference on Engineering of Complex Computer Systems (ICECCS). IEEE, 2019. http://dx.doi.org/10.1109/iceccs.2019.00022.

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Chia-Jui Hsu, S. Ramasubbu, Minq-Yunq Ko, J. L. Pino, and S. S. Bhattacharvva. "Efficient simulation of critical synchronous dataflow graphs." In 2006 Design Automation Conference. IEEE, 2006. http://dx.doi.org/10.1109/dac.2006.229257.

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Hsu, Chia-Jui, Suren Ramasubbu, Ming-Yung Ko, José Luis Pino, and Shuvra S. Bhattacharyya. "Efficient simulation of critical synchronous dataflow graphs." In the 43rd annual conference. ACM Press, 2006. http://dx.doi.org/10.1145/1146909.1147137.

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Desnos, Karol, Maxime Pelcat, Jean-Francois Nezan, and Slaheddine Aridhi. "Distributed Memory Allocation Technique for Synchronous Dataflow Graphs." In 2016 IEEE International Workshop on Signal Processing Systems (SiPS). IEEE, 2016. http://dx.doi.org/10.1109/sips.2016.16.

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Damavandpeyma, M., S. Stuijk, T. Basten, M. Geilen, and H. Corporaal. "Modeling static-order schedules in synchronous dataflow graphs." In 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012). IEEE, 2012. http://dx.doi.org/10.1109/date.2012.6176588.

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Lesparre, Youen, Alix Munier-Kordon, and Jean-Marc Delosme. "Evaluation of Synchronous Dataflow Graph Mappings onto Distributed Memory Architectures." In 2016 Euromicro Conference on Digital System Design (DSD). IEEE, 2016. http://dx.doi.org/10.1109/dsd.2016.52.

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de Groote, Robert, Philip K. F. Hölzenspies, Jan Kuper, and Gerard J. M. Smit. "Single-rate approximations of cyclo-static synchronous dataflow graphs." In the 17th International Workshop. ACM Press, 2014. http://dx.doi.org/10.1145/2609248.2609249.

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