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Journal articles on the topic 'Synchrous dataflow graph'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 May 2024

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1

Damavandpeyma, Morteza, Sander Stuijk, Twan Basten, Marc Geilen, and Henk Corporaal. "Schedule-Extended Synchronous Dataflow Graphs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 10 (2013): 1495–508. http://dx.doi.org/10.1109/tcad.2013.2265852.

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2

Chukhman, Ilya, Shuoxin Lin, William Plishker, Chung-Ching Shen, and Shuvra S. Bhattacharyya. "Instrumentation-Driven Model Detection and Actor Partitioning for Dataflow Graphs." International Journal of Embedded and Real-Time Communication Systems 4, no. 1 (2013): 1–21. http://dx.doi.org/10.4018/jertcs.2013010101.

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Dataflow modeling offers a myriad of tools to improve optimization and analysis of signal processing applications, and is often used by designers to help design, implement, and maintain systems on chip for signal processing. However, maintaining and upgrading legacy systems that were not originally designed using dataflow methods can be challenging. Designers often convert legacy code to dataflow graphs by hand, a process that can be difficult and time consuming. In this paper, the authors developed a method to facilitate this conversion process by automatically detecting the dataflow models o
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3

Ma, Mingze, and Rizos Sakellariou. "Code-size-aware Scheduling of Synchronous Dataflow Graphs on Multicore Systems." ACM Transactions on Embedded Computing Systems 20, no. 3 (2021): 1–24. http://dx.doi.org/10.1145/3440034.

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Synchronous dataflow graphs are widely used to model digital signal processing and multimedia applications. Self-timed execution is an efficient methodology for the analysis and scheduling of synchronous dataflow graphs. In this article, we propose a communication-aware self-timed execution approach to solve the problem of scheduling synchronous dataflow graphs on multicore systems with communication delays. Based on this communication-aware self-timed execution approach, four communication-aware scheduling algorithms are proposed using different allocation rules. Furthermore, a code-size-awar
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4

Hsu, Chia-Jui, José Luis Pino, and Shuvra S. Bhattacharyya. "Multithreaded Simulation for Synchronous Dataflow Graphs." ACM Transactions on Design Automation of Electronic Systems 16, no. 3 (2011): 1–23. http://dx.doi.org/10.1145/1970353.1970358.

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5

Hsu, Chia-Jui, Ming-Yung Ko, Shuvra S. Bhattacharyya, Suren Ramasubbu, and José Luis Pino. "Efficient simulation of critical synchronous dataflow graphs." ACM Transactions on Design Automation of Electronic Systems 12, no. 3 (2007): 1–28. http://dx.doi.org/10.1145/1255456.1255458.

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6

Bhattacharyya, Shuvra S., and Edward A. Lee. "Scheduling synchronous dataflow graphs for efficient looping." Journal of VLSI signal processing systems for signal, image and video technology 6, no. 3 (1993): 271–88. http://dx.doi.org/10.1007/bf01608539.

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7

Kapre, Nachiket, and André Dehon. "An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads." International Journal of Reconfigurable Computing 2011 (2011): 1–14. http://dx.doi.org/10.1155/2011/745147.

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Parallel graph-oriented applications expressed in the Bulk-Synchronous Parallel (BSP) and Token Dataflow compute models generate highly-structured communication workloads from messages propagating along graph edges. We can statially expose this structure to traffic compilers and optimization tools to reshape and reduce traffic for higher performance (or lower area, lower energy, lower cost). Such offline traffic optimization eliminates the need for complex, runtime NoC hardware and enables lightweight, scalable NoCs. We perform load balancing, placement, fanout routing, and fine-grained synchr
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8

Groote, Robert De, Philip K. F. Hölzenspies, Jan Kuper, and Gerard J. M. Smit. "Incremental Analysis of Cyclo-Static Synchronous Dataflow Graphs." ACM Transactions on Embedded Computing Systems 14, no. 4 (2015): 1–26. http://dx.doi.org/10.1145/2792981.

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9

Bodin, Bruno, and Alix Munier Kordon. "Evaluation of the Exact Throughput of a Synchronous DataFlow Graph." Journal of Signal Processing Systems 93, no. 9 (2021): 1007–26. http://dx.doi.org/10.1007/s11265-021-01649-z.

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10

Bennour, Imed Eddine. "Formal verification of timed synchronous dataflow graphs using Lustre." Journal of Logical and Algebraic Methods in Programming 121 (June 2021): 100678. http://dx.doi.org/10.1016/j.jlamp.2021.100678.

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11

Hyunuk Jung, Kangnyoung Lee, and Soonhoi Ha. "Efficient hardware controller synthesis for synchronous dataflow graph in system level design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10, no. 4 (2002): 423–28. http://dx.doi.org/10.1109/tvlsi.2002.807765.

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12

Tang, Qi, Twan Basten, Marc Geilen, Sander Stuijk, and Ji-Bo Wei. "Mapping of synchronous dataflow graphs on MPSoCs based on parallelism enhancement." Journal of Parallel and Distributed Computing 101 (March 2017): 79–91. http://dx.doi.org/10.1016/j.jpdc.2016.11.012.

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13

Zhu, Xue-Yang, Marc Geilen, Twan Basten, and Sander Stuijk. "Multiconstraint Static Scheduling of Synchronous Dataflow Graphs Via Retiming and Unfolding." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 6 (2016): 905–18. http://dx.doi.org/10.1109/tcad.2015.2495167.

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14

Stuijk, Sander, Marc Geilen, and Twan Basten. "Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs." IEEE Transactions on Computers 57, no. 10 (2008): 1331–45. http://dx.doi.org/10.1109/tc.2008.58.

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15

Choi, Junchul, and Soonhoi Ha. "Worst-Case Response Time Analysis of a Synchronous Dataflow Graph in a Multiprocessor System with Real-Time Tasks." ACM Transactions on Design Automation of Electronic Systems 22, no. 2 (2017): 1–26. http://dx.doi.org/10.1145/2997644.

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16

Wang, Jin Lin. "Scheduling of Periodic Tasks with Data Dependency on Multiprocessors." Advanced Materials Research 756-759 (September 2013): 2131–36. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.2131.

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This article studies the scheduling problem of a set of tasks with time or data constraints on a number of identical processors with full connections. We present an algorithm, in which a set of static schedule lists can be obtained, each for a processor, such that each task starts executing after its release time and completes its computation before its deadline, and all the precedence relations between tasks resulting from data dependency are satisfied. The data dependency relations between tasks are represented by Synchronous Dataflow Graphs (SDF) as they can indicate tasks concurrency and e
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17

Yuan, Bo, Xiaofen Lu, Ke Tang, and Xin Yao. "Cooperative Coevolution-based Design Space Exploration for Multi-mode Dataflow Mapping." ACM Transactions on Embedded Computing Systems 20, no. 3 (2021): 1–25. http://dx.doi.org/10.1145/3440246.

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Some signal processing and multimedia applications can be specified by synchronous dataflow (SDF) models. The problem of SDF mapping to a given set of heterogeneous processors has been known to be NP-hard and widely studied in the design automation field. However, modern embedded applications are becoming increasingly complex with dynamic behaviors changes over time. As a significant extension to the SDF, the multi-mode dataflow (MMDF) model has been proposed to specify such an application with a finite number of behaviors (or modes) and each behavior (mode) is represented by an SDF graph. The
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18

DEY, SOUMYAJIT, PRAVEEN ROKKAM, and ANUPAM BASU. "MODELING AND ANALYSIS OF EMBEDDED MULTIMEDIA APPLICATIONS USING COLORED PETRI NETS." International Journal of Modeling, Simulation, and Scientific Computing 02, no. 02 (2011): 169–93. http://dx.doi.org/10.1142/s1793962311000438.

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Embedded multimedia systems often run multiple time-constrained applications simultaneously. To meet the throughput constraints given in the specification, each application must be provided with enough resources by the underlying architecture, which is generally a multiprocessor system-on-chip (MPSoC). For this purpose, a mechanism for task binding and scheduling is required to provide each application with a timing guarantee, keeping in mind the available resources like processor(s) and memory bandwidth. Commonly, synchronous dataflow graphs (SDFGs) are used to model time-constrained multimed
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19

Fradet, Pascal, Alain Girault, Ruby Krishnaswamy, Xavier Nicollin, and Arash Shafiei. "RDF: A Reconfigurable Dataflow Model of Computation." ACM Transactions on Embedded Computing Systems, June 27, 2022. http://dx.doi.org/10.1145/3544972.

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Dataflow Models of Computation (MoCs) are widely used in embedded systems, including multimedia processing, digital signal processing, telecommunications, and automatic control. In a dataflow MoC, an application is specified as a graph of actors connected by FIFO channels. One of the first and most popular dataflow MoCs, Synchronous Dataflow (SDF), provides static analyses to guarantee boundedness and liveness, which are key properties for embedded systems. However, SDF and most of its variants lacks the capability to express the dynamism needed by modern streaming applications. In particular,
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20

Ma, Mingze, Jian Hou, Dongming Xiang, Wang Lin, and Zuohua Ding. "Efficient Pipelining of Synchronous Dataflow Graphs via Graph Conversion." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024, 1. http://dx.doi.org/10.1109/tcad.2024.3355190.

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21

Elahi, H., M. Geilen, and T. Basten. "Efficient Computation of the Max-Plus Semantics of Synchronous Dataflow Graphs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, 1. http://dx.doi.org/10.1109/tcad.2023.3239538.

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22

Song, Shihao, Harry Chong, Adarsha Balaji, Anup Das, James Shackleford, and Nagarajan Kandasamy. "DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware." ACM Transactions on Embedded Computing Systems, January 26, 2022. http://dx.doi.org/10.1145/3479156.

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Spiking Neural Networks (SNN) are an emerging computation model, which uses event-driven activation and bio-inspired learning algorithms. SNN-based machine-learning programs are typically executed on tile-based neuromorphic hardware platforms, where each tile consists of a computation unit called crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware pe
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