Relevant bibliographies by topics / System-on-a-programmable-chip

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Academic literature on the topic 'System-on-a-programmable-chip'

Author: Grafiati
Published: 5 June 2025
Last updated: 1 August 2025

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Journal articles on the topic "System-on-a-programmable-chip"

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Raj Kansal, Abhay. "A Study on Programmable System on Chip." IOSR journal of VLSI and Signal Processing 4, no. 5 (2014): 31–37. http://dx.doi.org/10.9790/4200-04513137.

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Choi, Woo-Chang, and Jee-Youl Ryu. "A Programmable Compensation Circuit for System-on-Chip Application." JSTS:Journal of Semiconductor Technology and Science 11, no. 3 (2011): 198–206. http://dx.doi.org/10.5573/jsts.2011.11.3.198.

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Truong, Nhu Thanh, and Diem Thi Tran. "DESIGNING A SOPC FOR FACE RECOGNITION USING WMPCA ALGORITHM." Science and Technology Development Journal 14, no. 4 (2011): 24–33. http://dx.doi.org/10.32508/stdj.v14i4.2033.

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A flexible accelerator hardware for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real-time image compression and recognition applications. Nowadays, FPGA and its SoPC (System on Programmable Chip) tools are powerful enough to efficiently develop a flexible hardware accelerator for VQ application. In addition, one of statistical analysis methods, weighted modular principal component analysis, has showed efficiencies in recognition applications. In this paper, a parallel architecture for online face recognition using
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Yu, Bing, Tian Hong Zhang, and Dong Dong Liu. "Low Cost AFDX End System Based on System on a Programmable Chip." Applied Mechanics and Materials 29-32 (August 2010): 2308–11. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.2308.

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AFDX (Avionics Full DupleX Switched Ethernet, ARINC 664) utilized in Airbus A380 and Boeing 787 represents a major upgrade in both bandwidth and capability; however some legacy systems are difficult to connect into the AFDX bus smoothly. A low cost AFDX end system based on SOPC (System On a Programmable Chip) is presented. A Xilinx Spartan 3AN FPGA is employed to build the whole system; and then a dedicated reduced Ethernet MAC controller for AFDX end system is designed; a MC8051 open core microcontroller is employed as the system controller and protocol processing unit. The whole design costs
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Cui, Rui Xue, Li Shuo, Xiao Rui Zhang, and Tong Fei Li. "Design of Intelligent Greenhouse Control System Based on PSoC Platform." Advanced Materials Research 860-863 (December 2013): 2346–50. http://dx.doi.org/10.4028/www.scientific.net/amr.860-863.2346.

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This paper mainly introduces a new design about intelligent greenhouse control system based on system on a programmable chip, which is PSoC. This paper first introduces the current advanced characteristics of this system on a programmable chip PSoC with digital and analog mixed processing ability, and then focuses on the system structure, working principle, the realization of hardware module and software design method of the intelligent greenhouse control system based on PsoC platform.
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Hall, T. S., and J. O. Hamblen. "System-on-a-Programmable-Chip Development Platforms in the Classroom." IEEE Transactions on Education 47, no. 4 (2004): 502–7. http://dx.doi.org/10.1109/te.2004.825926.

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Guo, Xu, and Patrick Schaumont. "Optimized System-on-Chip Integration of a Programmable ECC Coprocessor." ACM Transactions on Reconfigurable Technology and Systems 4, no. 1 (2010): 1–21. http://dx.doi.org/10.1145/1857927.1857933.

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Lopin, Prattana, and Kyle V. Lopin. "PSoC-Stat: A single chip open source potentiostat based on a Programmable System on a Chip." PLOS ONE 13, no. 7 (2018): e0201353. http://dx.doi.org/10.1371/journal.pone.0201353.

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Chen, H., F. Xu, and Y. Xi. "Field programmable gate array/system on a programmable chip-based implementation of model predictive controller." IET Control Theory & Applications 6, no. 8 (2012): 1055–63. http://dx.doi.org/10.1049/iet-cta.2010.0443.

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Zhang, Wei Min, Pei Min Zhu, Xi Feng Wang, Ya Min Li, and Yong Gao. "Design of a High-Performance Programmable Filter Based on TLC7528." Advanced Materials Research 875-877 (February 2014): 2152–57. http://dx.doi.org/10.4028/www.scientific.net/amr.875-877.2152.

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High-performance filter is the key to improving the detection accuracy of geophysical instruments. In order to achieve high-precision measurement of small signals, this paper presents a design of high-performance programmable filter based on TLC7528. The system design mainly included programmable amplifier circuit design, programmable filter circuit design, amplitude-frequency test circuit design, display circuit and the keyboard circuit design. The system used a microcontroller as the control center for system parameters setting and control, adopted analog switches and selected low-noise op a
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Dissertations / Theses on the topic "System-on-a-programmable-chip"

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Patel, Vipul Hiralal. "A system on programmable chip approach for MIMO lattice decoder." ScholarWorks@UNO, 2004. http://louisdl.louislibraries.org/u?/NOD,167.

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Thesis (M.S.)--University of New Orleans, 2004.<br>Title from electronic submission form. "A thesis ... in partial fulfillment of the requirements for the degree of Master of Science in the Department of Electrical Engineering."--Thesis t.p. Vita. Includes bibliographical references.
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Han, Yi. "A high-performance CMOS programmable logic core for system-on-chip applications /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/5948.

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Rößler, Marko. "Parallel Hardware- and Software Threads in a Dynamically Reconfigurable System on a Programmable Chip." Universitätsbibliothek Chemnitz, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-129626.

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Today’s embedded systems depend on the availability of hybrid platforms, that contain heterogeneous computing resources such as programmable processors units (CPU’s or DSP’s) and highly specialized hardware cores. These platforms have been scaled down to integrated embedded system-on-chip. Modern platform FPGAs enhance such systems by the flexibility of runtime configurable silicon. One of the major advantages that arises is the ability to use hardware (HW) and software (SW) resources in a time-shared manner. Though the ability to dynamically assign computing resources based on decisions taken
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Mollberg, Alexander. "A Resource-Efficient and High-Performance Implementation of Object Tracking on a Programmable System-on-Chip." Thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-124044.

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The computer vision problem of object tracking is introduced and explained. An approach to interest point based feature detection and tracking using FAST and BRIEF is presented and the selection of algorithms suitable for implementation on a Xilinx Zynq7000 with an XC7Z020 field-programmable gate array (FPGA) is detailed. A modification to the smoothing strategy of BRIEF which significantly reduces memory utilization on the FPGA is presented and benchmarked against a reference strategy. Measures of performance and resource efficiency are presented and utilized in an iterative development proce
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Loitz, Sacha [Verfasser]. "A Property Checking Methodology for Weakly Programmable System-on-Chip IPs : Eine Methode zur Eigenschaftsprüfung von schwach programmierbaren System-on-Chip IPs / Sacha Loitz." Aachen : Shaker, 2014. http://d-nb.info/1049381300/34.

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Bretz, Daniel. "Digitales Diktiergerät als System-on-a-Chip mit FPGA-Evaluierungsboard." [S.l. : s.n.], 2001. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB9033538.

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Holland, Mark. "Automatic creation of product-term-based reconfigurable architectures for system-on-a-chip /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6124.

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Vyas, Dhaval N. "FPGA-based hardware accelerator design for performance improvement of a system-on-a-chip application." Diss., Online access via UMI:, 2005.

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Fabris, Eric Ericson. "A Modular and digitally programmable interface based on band-pass sigma-delta modulator for mixed-signal systems-on-chip." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/6226.

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O foco desta tese é a descrição e validação de uma arquitetura de interface para processamento de sinais analógicos para SOC de sinais mistos. A abordagem proposta apresenta a possibilidade de cobertura de uma larga faixa de freqüências com performance praticamente constante associada a uma estrutura digital de programação. A premissa é usar uma célula analógica fixa e promover a configuração da aplicação no domínio digital, levando a uma arquitetura de interface de sinais mistos. O emprego de um bloco analógico fixo busca eliminar a perda inerente de performance decorrente da própria estrutur
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Al-Araje, Abdul-Nasser. "Micronetwork based system-on-FPGA (SOFPGA) architecture." Connect to resource, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1122609799.

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Books on the topic "System-on-a-programmable-chip"

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Blokdyk, Gerardus. Programmable System on a Chip a Complete Guide - 2020 Edition. Emereo Pty Limited, 2020.

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Nurmi, Jari. Processor Design: System-On-Chip Computing for ASICs and FPGAs. Springer London, Limited, 2007.

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Nurmi, Jari. Processor Design: System-on-Chip Computing for ASICs and FPGAs. Springer Netherlands, 2010.

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Processor Design: System-On-Chip Computing for ASICs and FPGAs. Springer, 2007.

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Book chapters on the topic "System-on-a-programmable-chip"

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Shan, Dan, Weidong Xiang, Paul Richardson, and Hua Qian. "System on a Programmable Chip Design of a Wireless Transceiver Prototype for Smart Grid Applications." In Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-41773-3_10.

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Hahn, Tobias, Maximilian Langohr, Andreas Becher, et al. "ReProVide: Query Optimization and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis." In Scalable Data Management for Future Hardware. Springer Nature Switzerland, 2025. https://doi.org/10.1007/978-3-031-74097-8_7.

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Abstract The available parallelism and heterogeneity of emerging computer systems must be exploited for being able to process the huge amounts of data produced every day. As a consequence, we observe an increasing research interest in accelerating database query processing on multi-cores and attached co-processors like Graphics Processing Units (GPUs) and Field-Programmable Gate Arrays (FPGAs). This chapter presents ReProVide, an approach combining near-data processing and FPGA-based acceleration. The System-on-Chip (SoC) architecture of ReProVide including a flexibly reconfigurable FPGA can l
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Chalimbaud, Pierre, and François Berry. "Versatile Imaging Architecture Based on a System on Chip." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_156.

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Boluda, Jose Antonio, and Fernando Pardo. "Synthesizing on a Reconfigurable Chip an Autonomous Robot Image Processing System." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45234-8_45.

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Cheung, Ray C. C. "A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_173.

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Urriza, Isidoro, José I. Garcia-Nicolás, Alfredo Sanz, and Antonio Valdovinos. "A System on Chip for Power Line Communications According to European Home Systems Specifications." In Field-Programmable Logic and Applications. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44687-7_74.

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"Introducing System-on-a-Programmable-Chip." In Rapid Prototyping of Digital Systems. Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-72671-7_15.

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Capmany, José, and Daniel Pérez. "Programmable Integrated Photonics for Quantum Systems." In Programmable Integrated Photonics. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198844402.003.0007.

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Programmable photonics can find applications in myriad areas including the quantum information field, which encompasses communications, computing, sensing and tomography. Large-scale bulk optics setups previously prevented the development of more complex and scalable quantum optics configurations. Linear optic systems with the required fidelity require a strict control of interference through demanding phase stability mechanisms. Integrating a considerable number of photonic elements on a chip in order to implement multi-port interferometers has become the only viable technological path toward
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Zhang Lin, Slaets Peter, and Bruyninckx Herman. "An FPGA Based Architecture for Concurrent System Design Applied to Human-robot Interaction Applications." In Advances in Transdisciplinary Engineering. IOS Press, 2014. https://doi.org/10.3233/978-1-61499-440-4-555.

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This paper presents a hardware and software architecture for vision-based human-robot interaction designed for field programmable gate array (FPGA) based embedded system. The configurable logic and memory blocks connected through programmable interconnects on the FPGA permit programmers to create complex systems running multiple processing cores in parallel, which motivated the authors to implement vision algorithms and robot controllers on a single system-on-chip (SoC) board, aiming at low cost, low power consumption and high performance in human-robot interaction for industrial and education
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Mukhopadhyay, Sumitra, and Soumyadip Das. "A System on Chip Development of Customizable GA Architecture for Real Parameter Optimization Problem." In Handbook of Research on Natural Computing for Optimization Problems. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-5225-0058-2.ch004.

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This chapter presents the design and development of a hardware based architecture of Evolutionary Algorithm for solving both the unimodal and multimodal fixed point real parameter optimization problems. Here a modular architecture has been proposed to provide a tradeoff between real time performance and flexibility and to work as a resource efficient reconfigurable device. The evolutionary algorithm used here is Genetic Algorithm. Prototype implementation of the algorithm has been performed on a system-on-chip field programmable gate array. The notable feature of the architecture is the capabi
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Conference papers on the topic "System-on-a-programmable-chip"

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Li, Dongfeng, Nan Chen, Bo Li, Tingcun Wei, Yongqian Du, and Tong Wu. "Design of A Programmable Digital Controller System on Chip for Switching Converters." In 2024 9th International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2024. https://doi.org/10.1109/icicm63644.2024.10814593.

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Yang, Hangbo, Nicola Peserico, Shurui Li, et al. "Prototyped and Upgraded Programmable On-chip Photonic Joint Transform Correlator-Based CNN." In CLEO: Science and Innovations. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/cleo_si.2024.sm4m.4.

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Gaska, Thomas, Aaron Carpenter, and Yu Chen. "Future Avionic System Hybrid Processor Pooled Architectures." In Vertical Flight Society 71st Annual Forum & Technology Display. The Vertical Flight Society, 2015. http://dx.doi.org/10.4050/f-0071-2015-10129.

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Next generation avionics Size Weight and Power (SWaP) can benefit from transformational improvements and flexibility in processing brought on by Moore's Law with proper heterogeneous pooled processor solutions. It is no longer feasible to simply use a modest number of network-connected single-core processors in isolated subsystems; instead, multicore processing is the norm. By 2016-2018, there will be on-chip multicore processors with 16 or more cores on each die integrated with on-chip transformational multi-Teraflop General Purpose Graphics Processing Units (GPGPUs). Heterogeneous reprogramm
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Hamalainen, P., Ning Liu, M. Hannikainen, and T. D. Hamalainen. "Acceleration of Modular Exponentiation on System-on-a-Programmable-Chip." In 2005 International Symposium on System-on-Chip. IEEE, 2005. http://dx.doi.org/10.1109/issoc.2005.1595632.

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Gomes, L., and A. Costa. "Teaching formal methods within system-on-a-programmable-chip design." In Proceedings. 2005 IEEE International Conference on Microelectronic Systems Education (MSE '05). IEEE, 2005. http://dx.doi.org/10.1109/mse.2005.53.

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BG, Alakananda, and Venugopal N. "Development of a Programmable System on Chip(Psoc) based Quadcopter." In 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI). IEEE, 2020. http://dx.doi.org/10.1109/icoei48184.2020.9143059.

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Thalhammer, S. "Programmable lab-on-a-chip system for single cell analysis." In SPIE Europe Microtechnologies for the New Millennium, edited by Achim Wixforth. SPIE, 2009. http://dx.doi.org/10.1117/12.820942.

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Petko, Maciej, and Grzegorz Karpiel. "Implementation of Control Algorithms in a System-on-a-Programmable-Chip." In 2006 IEEE International Conference on Mechatronics. IEEE, 2006. http://dx.doi.org/10.1109/icmech.2006.252544.

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Xu Ningyi, Liu Hong, Chen Xi, and Zhou Zucheng. "Implementation of DVB demultiplexer system with system-on-a-programmable-chip FPGA." In 2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03. IEEE, 2003. http://dx.doi.org/10.1109/icasic.2003.1277369.

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Zafar, Y. "Self-controlling asynchronous processor (SCAP) - a system on programmable chip (SoPC)." In International Multi Topic Conference, 2002. Abstracts. INMIC 2002. IEEE, 2002. http://dx.doi.org/10.1109/inmic.2002.1310149.

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