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Dissertations / Theses on the topic 'System-on-a-programmable-chip'

Author: Grafiati

Published: 5 June 2025

Last updated: 1 August 2025

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1

Patel, Vipul Hiralal. "A system on programmable chip approach for MIMO lattice decoder." ScholarWorks@UNO, 2004. http://louisdl.louislibraries.org/u?/NOD,167.

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Thesis (M.S.)--University of New Orleans, 2004.<br>Title from electronic submission form. "A thesis ... in partial fulfillment of the requirements for the degree of Master of Science in the Department of Electrical Engineering."--Thesis t.p. Vita. Includes bibliographical references.

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2

Han, Yi. "A high-performance CMOS programmable logic core for system-on-chip applications /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/5948.

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3

Rößler, Marko. "Parallel Hardware- and Software Threads in a Dynamically Reconfigurable System on a Programmable Chip." Universitätsbibliothek Chemnitz, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-129626.

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Today’s embedded systems depend on the availability of hybrid platforms, that contain heterogeneous computing resources such as programmable processors units (CPU’s or DSP’s) and highly specialized hardware cores. These platforms have been scaled down to integrated embedded system-on-chip. Modern platform FPGAs enhance such systems by the flexibility of runtime configurable silicon. One of the major advantages that arises is the ability to use hardware (HW) and software (SW) resources in a time-shared manner. Though the ability to dynamically assign computing resources based on decisions taken

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4

Mollberg, Alexander. "A Resource-Efficient and High-Performance Implementation of Object Tracking on a Programmable System-on-Chip." Thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-124044.

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The computer vision problem of object tracking is introduced and explained. An approach to interest point based feature detection and tracking using FAST and BRIEF is presented and the selection of algorithms suitable for implementation on a Xilinx Zynq7000 with an XC7Z020 field-programmable gate array (FPGA) is detailed. A modification to the smoothing strategy of BRIEF which significantly reduces memory utilization on the FPGA is presented and benchmarked against a reference strategy. Measures of performance and resource efficiency are presented and utilized in an iterative development proce

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5

Loitz, Sacha [Verfasser]. "A Property Checking Methodology for Weakly Programmable System-on-Chip IPs : Eine Methode zur Eigenschaftsprüfung von schwach programmierbaren System-on-Chip IPs / Sacha Loitz." Aachen : Shaker, 2014. http://d-nb.info/1049381300/34.

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6

Bretz, Daniel. "Digitales Diktiergerät als System-on-a-Chip mit FPGA-Evaluierungsboard." [S.l. : s.n.], 2001. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB9033538.

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7

Holland, Mark. "Automatic creation of product-term-based reconfigurable architectures for system-on-a-chip /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6124.

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8

Vyas, Dhaval N. "FPGA-based hardware accelerator design for performance improvement of a system-on-a-chip application." Diss., Online access via UMI:, 2005.

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9

Fabris, Eric Ericson. "A Modular and digitally programmable interface based on band-pass sigma-delta modulator for mixed-signal systems-on-chip." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/6226.

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O foco desta tese é a descrição e validação de uma arquitetura de interface para processamento de sinais analógicos para SOC de sinais mistos. A abordagem proposta apresenta a possibilidade de cobertura de uma larga faixa de freqüências com performance praticamente constante associada a uma estrutura digital de programação. A premissa é usar uma célula analógica fixa e promover a configuração da aplicação no domínio digital, levando a uma arquitetura de interface de sinais mistos. O emprego de um bloco analógico fixo busca eliminar a perda inerente de performance decorrente da própria estrutur

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10

Al-Araje, Abdul-Nasser. "Micronetwork based system-on-FPGA (SOFPGA) architecture." Connect to resource, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1122609799.

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11

Hong, Chuan. "Towards the development of a reliable reconfigurable real-time operating system on FPGAs." Thesis, University of Edinburgh, 2013. http://hdl.handle.net/1842/8948.

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In the last two decades, Field Programmable Gate Arrays (FPGAs) have been rapidly developed from simple “glue-logic” to a powerful platform capable of implementing a System on Chip (SoC). Modern FPGAs achieve not only the high performance compared with General Purpose Processors (GPPs), thanks to hardware parallelism and dedication, but also better programming flexibility, in comparison to Application Specific Integrated Circuits (ASICs). Moreover, the hardware programming flexibility of FPGAs is further harnessed for both performance and manipulability, which makes Dynamic Partial Reconfigura

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12

Schlottmann, Craig Richard. "A coordinated approach to reconfigurable analog signal processing." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/49021.

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The purpose of this research is to create a solid framework for embedded system design with field-programmable analog arrays (FPAAs). To achieve this goal, we've created a unified approach to the three phases of FPAA system design: (1) the hardware architecture; (2) the circuit design and modeling; and (3) the high-level software tools. First, we describe innovations to the reconfigurable analog hardware that enable advanced signal processing and integration into embedded systems. We introduce the multiple-input translinear element (MITE) FPAA and the dynamically-reconfigurable RASP 2.9v FPAA,

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13

Soh, Jeremy. "A scalable, portable, FPGA-based implementation of the Unscented Kalman Filter." Thesis, The University of Sydney, 2017. http://hdl.handle.net/2123/17286.

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Sustained technological progress has come to a point where robotic/autonomous systems may well soon become ubiquitous. In order for these systems to actually be useful, an increase in autonomous capability is necessary for aerospace, as well as other, applications. Greater aerospace autonomous capability means there is a need for high performance state estimation. However, the desire to reduce costs through simplified development processes and compact form factors can limit performance. A hardware-based approach, such as using a Field Programmable Gate Array (FPGA), is common when high perfor

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14

Robino, Francesco. "A model-based design approach for heterogeneous NoC-based MPSoCs on FPGA." Licentiate thesis, KTH, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-145521.

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Network-on-chip (NoC) based multi-processor systems-on-chip (MPSoCs) are promising candidates for future multi-processor embedded platforms, which are expected to be composed of hundreds of heterogeneous processing elements (PEs) to potentially provide high performances. However, together with the performances, the systems complexity will increase, and new high level design techniques will be needed to efficiently model, simulate, debug and synthesize them. System-level design (SLD) is considered to be the next frontier in electronic design automation (EDA). It enables the description of embed

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15

Tambara, Lucas Antunes. "Caracterização de circuitos programáveis e sistemas em chip sob radiação." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/86477.

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Este trabalho consiste em um estudo acerca dos efeitos da radiação em circuitos programáveis e sistemas em chip, do inglês System-on-Chip (SoC), baseados em FPGAs (Field-Programmable Gate Array). Dentre os diversos efeitos que podem ensejar falhas nos circuitos integrados, destacam-se a ocorrência de Single Event Effects (SEEs), Efeitos Transitórios em tradução livre, e a Dose Total Ionizante, do inglês Total Ionizing Dose (TID). SEEs podem ocorrer em razão da incidência de nêutrons originários de interações de raios cósmicos com a atmosfera terrestre, íons pesados provenientes do espaço e pró

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16

Limnuson, Kanokwan. "A Bidirectional Neural Interface Microsystem with Spike Recording, Microstimulation, and Real-Time Stimulus Artifact Rejection Capability." Case Western Reserve University School of Graduate Studies / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=case1421939391.

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17

Chiluvuri, Nayana Teja. "A Trusted Autonomic Architecture to Safeguard Cyber-Physical Control Leaf Nodes and Protect Process Integrity." Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/56572.

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Cyber-physical systems are networked through IT infrastructure and susceptible to malware. Threats targeting process control are much more safety-critical than traditional computing systems since they jeopardize the integrity of physical infrastructure. Existing defence mechanisms address security at the network nodes but do not protect the physical infrastructure if network integrity is compromised. An interface guardian architecture is implemented on cyber-physical control leaf nodes to maintain process integrity by enforcing high-level safety and stability policies. Preemptive detection s

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18

Lin, Yu-Chi, and 林育祺. "Implementation of Speech Recognition Using a System-on-a-Programmable-Chip System." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/20762684290250079459.

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碩士<br>逢甲大學<br>資訊工程所<br>92<br>The speed and size of programmable logic cores in FPGA have increased greatly, so that many complicated application can be realized in FPGA now. Therefore, FPGA has become the main device of SoC (System-on-a-Chip) design for fast application prototyping. Evidently, a good FPGA design environment plays an indispensable role in rapid prototyping and the demand of time-to-market of products. Speech is one friendly human-machine interface and is more and more attractive in consuming electronic products. This paper describes the implementation of an isolated word recogn

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19

Lin, Guang-bao, and 林廣保. "Integration of an Ethernet MAC on System-on-a-Programmable- Chip." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/90222173002001239018.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>94<br>This research aims to discuss the integration of an 10/100 Ethernet MAC on a System-on-a-Programmble-Chip. SOPC is a chip combined with “ASIC”(Application Specific IC) and “PLD”(Programmable Logic Device). Due to the lower Complexity, SOPC is suitable for SOC study in academic. In this research, Altera ARM-based ExcaliburTM SOPC is used and an Opencore 10/100 Ethernet MAC is integrated onto it. The topic of SOPC architecture, SOPC development flow, bus interface design of the hardware, driver development and verification strategy of SOPC are discussed. This w

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20

Hsin, Su Chien, and 蘇建新. "Performance Improvement of the 3D Graphic System Implemented on a System on a Programmable Chip System." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/28326151047686156103.

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碩士<br>輔仁大學<br>資訊工程學系碩士班<br>105<br>With the wide application of computer graphics, many handheld devices in market have embedded graphics acceleration systems. Moreover, there is a quick development of applying 3D graphics on multimedia and game systems. The study of this thesis is motivated by the research of using FPGA’s for versatile applications like accelerating voice recognition and Image Processing in computer graphics. Due to the fact that large datasets and elapsed CPU time for 3D graphics computation, this thesis addresses on FPGA’s hardware acceleration and batch processing of datase

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21

Liao, Chien-Yi, and 廖千毅. "Performance Improvement of the Speech Recognition System Implemented on a System-On-a-Programmable-Chip System." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/98244372828789733650.

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碩士<br>逢甲大學<br>資訊工程所<br>93<br>FPGA (Field Programmable Gate Array) has played an indispensable role in the design of SOC (System-on-Chip) systems. Due to the reconfigurable characteristic of the FPGAs, designer can flexibly design their system, and easily verify their systems. This thesis takes the design of speech recognition system as an example to demonstrate the design process of a SOPC (System-on-a-Programmable-Chip) system. We implemented the speech recognition system into the Altera’s SOPC system, and analyzed and compared our implementation with a previous implementation. Our speech rec

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22

Chang, Chih-Hao, and 張志豪. "Design for an Intelligent Surveillance System based on System-on-a-Programmable-Chip Platform." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/46894477546725654322.

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碩士<br>國立中央大學<br>電機工程學系<br>103<br>The digital surveillance system becomes more and more popular in recent years. It attempts to raise amount of high resolution cameras, consequently those systems stupendously increase the computational load on central server. As in the intelligent object recognition processing flow, the technique on segmentation and tracking multiple targets, such as tracking group of people through occlusion is still challenging. In this paper, we present a hardware design for the intelligent surveillance system. We have a complete system-level solution on algorithm and VLSI i

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23

Yu-Chang, Chang. "An Application Specific Design Methodology for System-On-a-Programmable-Chip." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-0307200520411200.

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24

Chang, Yu-Chang, and 張郁昌. "An Application Specific Design Methodology for System-On-a-Programmable-Chip." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/74550560828567827871.

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碩士<br>國立臺灣大學<br>電機工程學研究所<br>93<br>Field Programmable Gate Array (FPGA) technologies enabled the implementation of customizable computing platforms using System-on-a-Programmable-Chip (SOPC), where we can configure hardware resources appropriately to match specific application needs. In this paper, a new system design concept and a system design flow are proposed for SOPC paradigm. We describe our design and implementation of an embedded system on an SOPC development board, comparing different design methodologies and implementations using FIR application. Using the proposed design flow, the de

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25

Chen, Wei-ting, and 陳威廷. "System on a Programmable Chip Design with Applications in a Multimedia Platform." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/55353783428363555379.

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碩士<br>義守大學<br>電機工程學系碩士班<br>97<br>A stand alone embedded multimedia system is realized using SOPC (System on a programmable chip) in this thesis. The SOPC is built up on an Altera DE2-70 platform on which Nios II core is used as CPU and µC/OS II is selected as operating system. Based on the specifications of Avalon Bus, a soft master IP (Intellectual Property) of LTM Controller is developed using verilog HDL (hardware description language) to apply Multiple Master DMA and Share Memory methods to release the 64 MB SDRAM with dual-channel access on DE2_70 platform so that both software and hardwa

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26

Sule, Ambarish Mukund. "Hardware-software codesign of a programmable wireless receiver system-on-a-chip." 2003. http://www.lib.ncsu.edu/theses/available/etd-08212003-133438/unrestricted/etd.pdf.

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27

Tseng, Chih-Hao, and 曾志豪. "Programmable System-on-a-Chip (SoC) Design for Biomedical Signal Sensing Applications." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/47122934909381366436.

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碩士<br>中原大學<br>電子工程研究所<br>101<br>Recent years, biomedical research had been gradually developed toward multi-parameter sensing applications. In our lab, we has been proposed various parameter sensing systems for the project electronic tongue of which includes temperature, Glucose, pH, ECG … etc. The most representative system is the compound sensing system. It replaces the front sensor which can approach multi-parameter sensing system. It is a trend to develop multi-parameter sensing system in biomedical engineering. However, we cannot reach the stage of integration because we lack research of

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28

Yu, Po-Hsien, and 喻柏憲. "Microfluidic Control and Biomedical Detection Based on Field-Programmable Lab-on-a-Chip system." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/31878387081265320508.

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碩士<br>國立交通大學<br>電子研究所<br>105<br>In this thesis, several models for Field-Programmable Lab-On-a-Chip (FPLOC) system are proposed. FPLOC system which contains location sensing map, microfluidic operation, and high resolution capacitance sensor is a potential detecting device for bioassays, and these models including velocity models, moving operation, mixing operation, cutting operation, and error recovery system can improve throughput and accuracy of biomedical experiments. The velocity model can predict transporting time of different size droplets precisely. Moving operation contains diagonal m

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Shiu, Ming-Feng, and 許銘峰. "System Integration of Field-Programmable Lab-on-a-Chip (FPLOC) for Biomedical Detection." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/3awbqv.

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碩士<br>國立交通大學<br>生醫工程研究所<br>104<br>In this thesis, a system integration of Field-Programmable Lab-on-a-Chip (FPLOC) which is applied for biomedical detection is proposed. This work integrates many functions, including droplet location sensing, droplet pattern planning, actuation and high resolution measurement window. This novel FPLOC resolves bottleneck of traditional development. Furthermore, microelectrode cell employs the sensing circuit, forms droplet location/ category sensing, built-in self-test (BIST) for chip-testing. We realize a friendly graphical user interface (GUI) to achieve real

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30

Chun-I, Yeh, and 葉俊邑. "A Wearable Physical Activity and Heart Rate Monitoring Device Based on the Programmable System on Chip." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/88729654407048960593.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>100<br>The root of maintaining health is exercise. However, how much exercise is enough? A rule of exercise gives you suggestion - "333 Rule". It means that you should do exercise 30 minutes per time and three times every week at least, and let your heart rate (HR) reach to 130 beats per minute(bpm). Moreover, another keep health rule is walking 10000 steps every day. Nevertheless, how to know that HR and step count (SC)? Then you need a HR monitor and a pedometer. In order to measure the HR and SC in real time. We developed a wearable HR and activity monitoring syst

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