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Journal articles on the topic 'System-on-a-programmable-chip'

Author: Grafiati

Published: 5 June 2025

Last updated: 15 July 2025

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1

Raj Kansal, Abhay. "A Study on Programmable System on Chip." IOSR journal of VLSI and Signal Processing 4, no. 5 (2014): 31–37. http://dx.doi.org/10.9790/4200-04513137.

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Choi, Woo-Chang, and Jee-Youl Ryu. "A Programmable Compensation Circuit for System-on-Chip Application." JSTS:Journal of Semiconductor Technology and Science 11, no. 3 (2011): 198–206. http://dx.doi.org/10.5573/jsts.2011.11.3.198.

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3

Truong, Nhu Thanh, and Diem Thi Tran. "DESIGNING A SOPC FOR FACE RECOGNITION USING WMPCA ALGORITHM." Science and Technology Development Journal 14, no. 4 (2011): 24–33. http://dx.doi.org/10.32508/stdj.v14i4.2033.

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A flexible accelerator hardware for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real-time image compression and recognition applications. Nowadays, FPGA and its SoPC (System on Programmable Chip) tools are powerful enough to efficiently develop a flexible hardware accelerator for VQ application. In addition, one of statistical analysis methods, weighted modular principal component analysis, has showed efficiencies in recognition applications. In this paper, a parallel architecture for online face recognition using

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Yu, Bing, Tian Hong Zhang, and Dong Dong Liu. "Low Cost AFDX End System Based on System on a Programmable Chip." Applied Mechanics and Materials 29-32 (August 2010): 2308–11. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.2308.

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AFDX (Avionics Full DupleX Switched Ethernet, ARINC 664) utilized in Airbus A380 and Boeing 787 represents a major upgrade in both bandwidth and capability; however some legacy systems are difficult to connect into the AFDX bus smoothly. A low cost AFDX end system based on SOPC (System On a Programmable Chip) is presented. A Xilinx Spartan 3AN FPGA is employed to build the whole system; and then a dedicated reduced Ethernet MAC controller for AFDX end system is designed; a MC8051 open core microcontroller is employed as the system controller and protocol processing unit. The whole design costs

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Cui, Rui Xue, Li Shuo, Xiao Rui Zhang, and Tong Fei Li. "Design of Intelligent Greenhouse Control System Based on PSoC Platform." Advanced Materials Research 860-863 (December 2013): 2346–50. http://dx.doi.org/10.4028/www.scientific.net/amr.860-863.2346.

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This paper mainly introduces a new design about intelligent greenhouse control system based on system on a programmable chip, which is PSoC. This paper first introduces the current advanced characteristics of this system on a programmable chip PSoC with digital and analog mixed processing ability, and then focuses on the system structure, working principle, the realization of hardware module and software design method of the intelligent greenhouse control system based on PsoC platform.

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6

Hall, T. S., and J. O. Hamblen. "System-on-a-Programmable-Chip Development Platforms in the Classroom." IEEE Transactions on Education 47, no. 4 (2004): 502–7. http://dx.doi.org/10.1109/te.2004.825926.

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7

Guo, Xu, and Patrick Schaumont. "Optimized System-on-Chip Integration of a Programmable ECC Coprocessor." ACM Transactions on Reconfigurable Technology and Systems 4, no. 1 (2010): 1–21. http://dx.doi.org/10.1145/1857927.1857933.

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Lopin, Prattana, and Kyle V. Lopin. "PSoC-Stat: A single chip open source potentiostat based on a Programmable System on a Chip." PLOS ONE 13, no. 7 (2018): e0201353. http://dx.doi.org/10.1371/journal.pone.0201353.

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Chen, H., F. Xu, and Y. Xi. "Field programmable gate array/system on a programmable chip-based implementation of model predictive controller." IET Control Theory & Applications 6, no. 8 (2012): 1055–63. http://dx.doi.org/10.1049/iet-cta.2010.0443.

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Zhang, Wei Min, Pei Min Zhu, Xi Feng Wang, Ya Min Li, and Yong Gao. "Design of a High-Performance Programmable Filter Based on TLC7528." Advanced Materials Research 875-877 (February 2014): 2152–57. http://dx.doi.org/10.4028/www.scientific.net/amr.875-877.2152.

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High-performance filter is the key to improving the detection accuracy of geophysical instruments. In order to achieve high-precision measurement of small signals, this paper presents a design of high-performance programmable filter based on TLC7528. The system design mainly included programmable amplifier circuit design, programmable filter circuit design, amplitude-frequency test circuit design, display circuit and the keyboard circuit design. The system used a microcontroller as the control center for system parameters setting and control, adopted analog switches and selected low-noise op a

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11

Ruan, Yue, Ying Tang, and Wen Ji Yao. "Design and Implementation of a Single Chip Multi-Waveform Signal Generator Based on SOPC Design Methodology." Advanced Materials Research 482-484 (February 2012): 550–54. http://dx.doi.org/10.4028/www.scientific.net/amr.482-484.550.

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This work presents a highly integrated multi-functional, multi-waveform signal generator which can generate various waveforms, with digital controller inside to adapt embedded and low power applications. The proposed system uses Nios II, a reconfigurable, programmable and optimizable soft-core embedded CPU together with modern EDA tools to accomplish system HW/SW co-design and implementation. Utilizing characteristics of Nios II, we put together core and peripheral logical units that system needs and implant them into a single FPGA chip, then uses the Avalon bus to connect peripheral modules (

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12

Wang, L., E. A. Johannessen, P. A. Hammond, et al. "A Programmable Microsystem Using System-on-Chip for Real-time Biotelemetry." IEEE Transactions on Biomedical Engineering 52, no. 7 (2005): 1251–60. http://dx.doi.org/10.1109/tbme.2005.847562.

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13

Wang, Xiaoyu, Haigang Yang, Fanyang Li, Tao Yin, Guocheng Huang, and Fei Liu. "A programmable analog hearing aid system-on-chip with frequency compensation." Analog Integrated Circuits and Signal Processing 79, no. 2 (2014): 227–36. http://dx.doi.org/10.1007/s10470-014-0264-6.

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14

Zhang, Xiang, and Zhangwei Chen. "SAD-Based Stereo Vision Machine on a System-on-Programmable-Chip (SoPC)." Sensors 13, no. 3 (2013): 3014–27. http://dx.doi.org/10.3390/s130303014.

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15

Fernández-Pérez, José, Francisco Sánchez-Fernández, and Ricardo Carmona-Galán. "Performance Evaluation and Limitations of a Vision System on a Reconfigurable/Programmable Chip." JUCS - Journal of Universal Computer Science 13, no. (3) (2007): 440–53. https://doi.org/10.3217/jucs-013-03-0440.

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This paper presents a survey of the characteristics of a vision system implemented in a reconfigurable/programmable chip (FPGA). System limitations and performance have been evaluated in order to derive specifications and constraints for further vision system synthesis. The system hereby reported has a conventional architecture. It consists in a central microprocessor (CPU) and the necessary peripheral elements for data acquisition, data storage and communications. It has been designed to stand alone, but a link to the programming and debugging tools running in a digital host (PC) is provided.

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16

Xu, Jiang Chun, Shi Bo Hao, and Xi Liu. "Design of Video Motion Detect System Based on SOPC." Applied Mechanics and Materials 241-244 (December 2012): 2263–67. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.2263.

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It is very necessary to apply motion detection to video surveillance in order to enhance the performance of system. A new design scheme of video motion detect system based on System On a Programmable Chip is proposed. Two cameras will capture the video data in real-time, and transmitted to DE2_70 development board. After the system which is on a programmable chip based on FPGA processing, the cameras survey whether an illegal personnel is in the range of cameras. The system achieves that two-way video to switch through the switch button. The experimental results show that the SOPC realization

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McRae, Michael P., Glennon W. Simmons, Jorge Wong, et al. "Programmable bio-nano-chip system: a flexible point-of-care platform for bioscience and clinical measurements." Lab on a Chip 15, no. 20 (2015): 4020–31. http://dx.doi.org/10.1039/c5lc00636h.

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The programmable bio-nano-chip (p-BNC) is an ultra-flexible system for multiplexed and multiclass assays on a universal modular lab-on-a-chip platform for clinical and bioscience applications at the point-of-care.

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Muñoz-Martínez, Adrián Iván, Omar Israel González Peña, Jordi Colomer-Farrarons, José Manuel Rodríguez-Delgado, Alfonso Ávila-Ortega, and Graciano Dieck-Assad. "Electrochemical Instrumentation of an Embedded Potentiostat System (EPS) for a Programmable-System-On-a-Chip." Sensors 18, no. 12 (2018): 4490. http://dx.doi.org/10.3390/s18124490.

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Under the main features required on portable devices in electrochemical instrumentation is to have a small size, low power consumption, economically affordable and precision in the measurements. This paper describes the development of a programmable Embedded Potentiostat System (EPS) capable of performing electrochemical sensing over system-on-a-chip platforms. Furthermore, the study explains a circuit design and develops some validation of the entire system. The hardware validation is performed by electrochemical experiments such as Double Step Chronoamperometry (DSC), Linear Sweep Voltammetr

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19

Liu, Xiang Wen, and Li Min Liu. "The IP Design for a Customized Mobile SoC." Advanced Materials Research 605-607 (December 2012): 2087–90. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.2087.

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IP, Intellectual Property, modules are essential and important for SoC applications. SoC, System on a Chip, is a system integrated on a single semiconductor chip. It is a research hot-point in embedded systems. In this paper, the IP design for a customized mobile SoC is discussed. The customized mobile SoC integrates a mobile computing control or monitor system into one chip FPGA, Field Programmable Gate Arrays. The SoC is required smaller in size and more efficient in operation.

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Yang, Shufan, KongFatt Wong-Lin, James Andrew, Terrence Mak, and T. Martin McGinnity. "A neuro-inspired visual tracking method based on programmable system-on-chip platform." Neural Computing and Applications 30, no. 9 (2017): 2697–708. http://dx.doi.org/10.1007/s00521-017-2847-5.

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21

Adi, P. D. P., A. Kitagawa, V. Sihombing, et al. "A Study of Programmable System on Chip (PSoC) Technology for Engineering Education." Journal of Physics: Conference Series 1899, no. 1 (2021): 012163. http://dx.doi.org/10.1088/1742-6596/1899/1/012163.

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22

Wang, Xu, Yongxin Zhu, Yajun Ha, et al. "An energy-efficient system on a programmable chip platform for cloud applications." Journal of Systems Architecture 76 (May 2017): 117–32. http://dx.doi.org/10.1016/j.sysarc.2016.11.009.

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23

Ahmad, Sagheer, Vamsi Boppana, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, and Ralph Wittig. "A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform." IEEE Micro 36, no. 2 (2016): 48–62. http://dx.doi.org/10.1109/mm.2016.18.

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24

Yu, Ying-Hao, N. M. Kwok, and Q. P. Ha. "Color tracking for multiple robot control using a system-on-programmable-chip." Automation in Construction 20, no. 6 (2011): 669–76. http://dx.doi.org/10.1016/j.autcon.2011.04.013.

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25

Bahtin, Vadim, Ivan A. Podlesnykh, and Sergey F. Tyurin. "Investigation of a Neural Network Decomposition by Proteus Design Suite." Вестник Пермского университета. Математика. Механика. Информатика, no. 2(57) (2022): 73–80. http://dx.doi.org/10.17072/1993-0550-2022-2-73-80.

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The division of a monolithic neural network into blocks with their implementation on programmable logic within the framework of the Fog computing concept is considered. It is assumed that considering possible reconfiguration the implementation of blocks is performed on programmable logic: field-programmable gate array, FPGA (complex programmable logic device, CPLD), System-on-a-Chip, SoC or System-in-Package, SiP. The article explores such an implementation in the Proteus Design Suite based on ATMega32 microcontrollers. Modeling confirms the efficiency of the developed decomposition method. Th

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26

Baans, Omar Salem, and Asral Bahari Jambek. "Implementation of an ARM-based system using a Xilinx ZYNQ SoC." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (2019): 485. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp485-491.

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<span>ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the Cortex-A9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.</span>

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Baans, Omar Salem, and Asral Bahari Jambek. "Implementation of an ARM-Based system using a Xilinx ZYNQ SoC." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (2019): 485–91. https://doi.org/10.11591/ijeecs.v13.i2.pp485-491.

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ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the CortexA9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.

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28

Fu, Shi Min, Cheng Jun Qiu, Dan Bu, Quan Yi Liu, and Chao Wang. "Research on Internet of Things Based on SOPC." Applied Mechanics and Materials 195-196 (August 2012): 132–37. http://dx.doi.org/10.4028/www.scientific.net/amm.195-196.132.

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An Internet of things system using Cyclone EP2C8 FPGA chip of Altera is designed and researched in this paper, which integrated NiosII soft-core processor, memory, functional interfaces with SOPC (system on a programmable chip) technology. The μC/OS-II embedded operating system is transplanted here to realize the network communication through driving the network chip. Simultaneously, the message stored in card can be correctly identified, recorded, added up by RFID technology, and sent to internet according to the requirement of communication. Thus, the internet of things function is realized.

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29

Huang, LinYun, Young-Pil Lee, Yong-Seon Moon, and Young-Chul Bae. "Noble Implementation of Motor Driver with All Programmable SoC for Humanoid Robot or Industrial Device." International Journal of Humanoid Robotics 14, no. 04 (2017): 1750028. http://dx.doi.org/10.1142/s0219843617500281.

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Currently, as the requirements for simple implementations in the motor control technologies increase, System-on-Chip (SoC) device such as Zynq All Programmable SoC was devised to meet those requirements. Because this CPU and FPGA can be assembled into one SoC device, we can consolidate motor-control functions and additional processing tasks into a single SoC device. The control algorithms, networking and other tasks, are off-loaded to the programmable logic that can include multiple control cores and multiple control system. This SoC system with a single chip can allow the hardware design with

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Sklyarov, Valery, Iouliia Skliarova, and João Silva. "On-Chip Reconfigurable Hardware Accelerators for Popcount Computations." International Journal of Reconfigurable Computing 2016 (2016): 1–11. http://dx.doi.org/10.1155/2016/8972065.

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Popcount computations are widely used in such areas as combinatorial search, data processing, statistical analysis, and bio- and chemical informatics. In many practical problems the size of initial data is very large and increase in throughput is important. The paper suggests two types of hardware accelerators that are (1) designed in FPGAs and (2) implemented in Zynq-7000 all programmable systems-on-chip with partitioning of algorithms that use popcounts between software of ARM Cortex-A9 processing system and advanced programmable logic. A three-level system architecture that includes a gener

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Ibraimov, M. K. "IMPLEMENTATION OF FUNCTIONAL BLOCK RADIO UNIT BASED ON SYSTEM-ON-CHIP." Eurasian Physical Technical Journal 20, no. 4 (46) (2023): 74–80. http://dx.doi.org/10.31489/2023no4/74-80.

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This article discusses the implementation of the Radio Unit functional block based on the System-on-Chip. The primary focus was on integrating Radio Unit blocks such as modulation and Fast Fourier Transform on Field-Programmable Gate Array. Technical aspects of design, module testing, and Radio Unit block performance optimization are thoroughly examined. The results demonstrate that when separating the functionality of the 7.3 technology Fifth Generation (5G) radio block, the modulation module uses the minimum Field-Programmable Gate Array resources compared to other blocks. The Fast Fourier T

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32

Cong, Vo. "Industrial robot arm controller based on programmable System-on-Chip device." FME Transactions 49, no. 4 (2021): 1025–34. http://dx.doi.org/10.5937/fme2104025c.

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Field-programmable gate arrays (FPGAs) and, recently, System on Chip (SoC) devices have been applied in a wide area of applications due to their flexibility for real-time implementations, increasing the processing capability on hardware as well as the speed of processing information in real-time. The most important applications based on FPGA/SoC devices are focused on signal/image processing, Internet of Things (IoT) technology, artificial intelligence (AI) algorithms, energy systems applications, automatic control and industrial applications. This paper develops a robot arm controller based o

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33

Ruiz-de-Clavijo, Paulino, German Cano-Quiveu, Jorge Juan, et al. "NanoBoot: A Field-Programmable Gate Array/System-on-Chip Hardware Boot Loader for IoT Devices." Electronics 13, no. 18 (2024): 3731. http://dx.doi.org/10.3390/electronics13183731.

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This paper presents a new boot loader scheme for embedded devices with file system support built as a hardware module. The work focuses on improving the boot loader hardware and the possibility of carrying out a full boot-up process from the dedicated on-chip hardware, using a light file system to store an operating system kernel. To do so, the new full-hardware boot loader is integrated into two Field-Programmable Gate Array (FPGA) System-on-Chip (SoC), capable of launching a Linux kernel from a formatted removable media.

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Lin, Shun-Chieh, Jia-Ching Wang, and Jhing-Fa Wang. "An ARM-Based System-on-a-Programmable-Chip Architecture for Spoken Language Translation." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 9 (2007): 765–69. http://dx.doi.org/10.1109/tcsii.2007.899775.

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35

Bjerge, Kim, Hans O. U. Fynbo, and Jacob G. Johansen. "A system on programmable chip design of a digitizer with improved trapezoidal filter validation." Microprocessors and Microsystems 65 (March 2019): 7–13. http://dx.doi.org/10.1016/j.micpro.2018.12.004.

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Martín del Campo, Fernando, René Cumplido, Roberto Perez-Andrade, and A. G. Orozco-Lugo. "A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation." International Journal of Reconfigurable Computing 2009 (2009): 1–10. http://dx.doi.org/10.1155/2009/912301.

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Channel estimation in wireless communication systems is usually accomplished by inserting, along with the information, a series of known symbols, whose analysis is used to define the parameters of the filters that remove the distortion of the data. Nevertheless, a part of the available bandwidth has to be destined to these symbols. Until now, no alternative solution has demonstrated to be fully satisfying for commercial use, but one technique that looks promising is superimposed training (ST). This work describes a hybrid software-hardware FPGA implementation of a recent algorithm that belongs

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37

Zhu, Juan, and Yue Chen. "Step Motor Control Based on FPGA." Applied Mechanics and Materials 397-400 (September 2013): 1226–29. http://dx.doi.org/10.4028/www.scientific.net/amm.397-400.1226.

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Design a step motor control system based on Field Programmable Gate Array (FPGA). Give the hardware circuit of this system and the program based on very high speed integrated circuit hardware description language (VHDL). Compared to step motor control system based on single chip microcomputer, the processing speed of this system is faster.

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Zhang, Zi Sheng, Peng Bo Ge, Xiao Dong Shi, Bo Feng Liu, and Zhi Qiang Liu. "The Control System of High Voltage Electrostatic Precipitator Based on FPGA." Advanced Materials Research 823 (October 2013): 528–31. http://dx.doi.org/10.4028/www.scientific.net/amr.823.528.

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It is urgent to study a new control system for improving the efficiency of electrostatic precipitator. The System-on-a-Programmable-Chip (SOPC) development board, which belongs to the series of Cyclone of Altera Company, is used as the development platform. Analog Digital (AD) conversion module, voltage control module and overall control module of the electrostatic precipitator are designed and the simulation waveform of the system is analyzed, based on the programmable logic device EP1C12Q240C6 and Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) programming language. T

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Hyodo, Kazuhito, Hirokazu Noborisaka, Keijiro Yamamoto, and Takashi Yada. "Development of a Portable Multipurpose Controller for Mechatronics Education." Journal of Robotics and Mechatronics 19, no. 2 (2007): 223–31. http://dx.doi.org/10.20965/jrm.2007.p0223.

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The control module we developed for mechatronics education, consists of a Field-programmable gate array (FPGA), a Programmable System-On-Chip (PSoC) and Game Boy Advance (GBA). The FPGA and PSoC provide a reconfigurable peripheral module and the GBA provides computational power and an interactive user interface. The interactive user interface is very useful for developing educational materials, and the control module enables educators to develop a variety of educational materials.

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Juang, Jih Gau, and Zong Ru Yu. "Application of Embedded System to Intelligent Control Based on CMAC-SoPC." Applied Mechanics and Materials 58-60 (June 2011): 2251–56. http://dx.doi.org/10.4028/www.scientific.net/amm.58-60.2251.

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This paper presents a control problem of a twin rotor MIMO system (TRMS) based on the system on programmable chip (SoPC). The control system utilizes the cerebellar model articulation controller (CMAC) as a compensator for PID control. The CMAC has fast learning capability that can provide real time compensation for PID controller. In the hardware implementation, HCTL-2016 is used to encode AB phase voltage into digital signals. Verilog HDL is utilized to encode program that can receive and trigger signals from HCTL-2016 on Altera Nios II FPGA. By coding the programmable chip control signal ca

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Shieh, Cheng Shion. "From Simulation to FPGA Control Circuit Implementation for Wind Power with Battery Charging." Advanced Materials Research 588-589 (November 2012): 777–80. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.777.

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While application of field-programmable gate array (FPGA) chip has been extensively investigated, the charging control is relatively unexplored. This paper proposes a flow chart of energy storage for wind power system with Lead-Acid battery whose charging control is constructed by Very High Speed Integrated Circuit Hardware Description Language (VHDL) code. This research focuses on the proposed digital control algorithm can be directly downloaded into field-programmable gate array (FPGA) chip after simulation finishing. This saves greatly time on hardware circuit design. A simulation is presen

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Gerlein, Eduardo A., Gabriel Díaz-Guevara, Henry Carrillo, Carlos Parra, and Enrique Gonzalez. "Embbedded System-on-Chip 3D Localization and Mapping—eSoC-SLAM." Electronics 10, no. 12 (2021): 1378. http://dx.doi.org/10.3390/electronics10121378.

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This paper discusses a novel embedded system-on-chip 3D localization and mapping (eSoC-LAM) implementation, that followed a co-design approach with the primary aim of being deployed in a small system on a programmable chip (SoPC), the Intel’s (a.k.a Altera) Cyclone V 5CSEMA5F31C6N, available in the Terasic’s board DE1-SoC. This computer board incorporates an 800 MHz Dual-core ARM Cortex-A9 and a Cyclone V FPGA with 85k programmable logic elements and 4450 Kbits of embedded memory running at 50 MHz. We report experiments of the eSoC-LAM implementation using a Robosense’s 3D LiDAR RS-16 sensor i

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Shkil, Alexander, Dariia Rakhlis, Inna Filippenko, Valentyn Korniienko, and Tetiana Rozhnova. "Automated design of embedded digital signal processing systems on SOC platform." INNOVATIVE TECHNOLOGIES AND SCIENTIFIC SOLUTIONS FOR INDUSTRIES, no. 1 (27) (July 2, 2024): 192–203. http://dx.doi.org/10.30837/itssi.2024.27.192.

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The object of the study is the procedures for automated design and analysis of digital signal processing algorithms on the SoC technology platform. The subject of the study is models, methods and procedures for designing and optimal selection of SoC components for the implementation of digital signal processing algorithms for audio spectrum. The aim of the study is to develop models and procedures for determining the possibilities of a compromise distribution of signal processing algorithm computations in the cycle of computer-aided design on the SoC technology platform in terms of performance

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Zhu, Qi. "Front-End Design of High-Resolution Video Communication System Based on SoPC." Applied Mechanics and Materials 608-609 (October 2014): 670–73. http://dx.doi.org/10.4028/www.scientific.net/amm.608-609.670.

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Using high-resolution CCD chip and high-speed A/D converter chip, the design of the Video Communication System is given in this article, which successfully realizes the drive of the high-resolution area CCD and achieves the digital image signal. Based on the thought of SoPC’s (System on Programmable Chip) high integration, on the ALTERA company's DE2 platform, FPGA is used to achieve the driving timing of CCD, Silicon delay lines are used to properly align the pixel rate CCD clock signals with respect to one another, and the push-pull transistor circuits are designed to translate TTL level dri

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Acevedo, Pedro, Martín Fuentes, Joel Durán, Mónica Vázquez, and Carlos Díaz. "Pulse Generator for Ultrasonic Piezoelectric Transducer Arrays Based on a Programmable System-on-Chip (PSoC)." Advances in Science, Technology and Engineering Systems Journal 2, no. 3 (2017): 205–9. http://dx.doi.org/10.25046/aj020327.

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Snider, Ross, Matthew Blunt, Trevor Vannoy, Dustin Sobrero, Dylan Wickham, and Tyler Davis. "Implementing the open master hearing aid on a system-on-chip field programmable gate array." Journal of the Acoustical Society of America 148, no. 4 (2020): 2508. http://dx.doi.org/10.1121/1.5146971.

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Wang, Cong, Yi Long Liu, Peng Long Jiang, Qing Zhen Zhang, Fei Tao, and Lin Zhang. "Multiple Faults Detection with SoC Dynamic Reconfiguration System Based on FPGA." Advanced Materials Research 694-697 (May 2013): 2642–45. http://dx.doi.org/10.4028/www.scientific.net/amr.694-697.2642.

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Multiple faults detection has great significance in practice. A dynamic reconfiguration SoC (System on Chip) system based on FPGA (Field Programmable Gate Array) is designed to realize multiple faults detection and reduce the detection time. Also, a framework of software platform and a case study for demonstrating and validating the SoC dynamic reconfiguration system are proposed.

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Li, Xue Zhe, and Xu Ming Wang. "The Design and Implementation of a Multifunctional Programmable Signal Generator." Applied Mechanics and Materials 190-191 (July 2012): 1074–78. http://dx.doi.org/10.4028/www.scientific.net/amm.190-191.1074.

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Signal source with high precision and programmable is needed in modern scientific research, communication system, teaching apparatus, electronic measurement and so on. In the paper, a portable signal generator is proposed, which has a core of AT89C51 and programmable DDS integrated chip AD9833. The paper also introduces the principle and implementation of system project. The generator can output sinusoidal wave, square wave, triangle wave, dc voltage, and it has manual and SPC two working mode, can implement PC SPC output through RS232 communication interface. Experiments show that the system

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Lázaro, Jesús, Unai Bidarte, Leire Muguira, Carlos Cuadrado, and Jaime Jiménez. "Fast and efficient address search in System-on-a-Programmable-Chip using binary trees." Computers & Electrical Engineering 96 (December 2021): 107403. http://dx.doi.org/10.1016/j.compeleceng.2021.107403.

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Jin, Jie, and Li Cui. "Fully Integrated Memristor and Its Application on the Scroll-Controllable Hyperchaotic System." Complexity 2019 (January 10, 2019): 1–8. http://dx.doi.org/10.1155/2019/4106398.

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In this paper, a fully integrated memristor emulator using operational amplifiers (OAs) and analog multipliers is simulated. Based on the fully integrated memristor, a scroll-controllable hyperchaotic system is presented. By controlling the nonlinear function with programmable switches, the memristor-based hyperchaotic system achieves controllable scroll numbers. Moreover, the memristor-based hyperchaotic system is fully integrated in one single chip, and it achieves lower supply voltage, lower power dissipation, and smaller chip area. The fully integrated memristor and memristor-based hyperch

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