Relevant bibliographies by topics / SystemC TLM

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'SystemC TLM'

Author: Grafiati
Published: 4 June 2021
Last updated: 1 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'SystemC TLM.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "SystemC TLM"

1

Le, Hoang M., Daniel Grosse, and Rolf Drechsler. "Automatic TLM Fault Localization for SystemC." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 8 (August 2012): 1249–62. http://dx.doi.org/10.1109/tcad.2012.2188800.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Monton, Màrius, Jakob Engblom, and Mark Burton. "Checkpointing for Virtual Platforms and SystemC-TLM." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 1 (January 2013): 133–41. http://dx.doi.org/10.1109/tvlsi.2011.2181881.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Jovanovic, S., and S. Weber. "Modélisation SystemC-TLM de systèmes à base de processeur." J3eA 18 (2019): 1009. http://dx.doi.org/10.1051/j3ea/20191009.

Full text
Abstract:
Nous présentons un ensemble de travaux pratiques qui seront dispensés au sein du Master EEA - Électronique Embarquée à l'université de Lorraine dans le cadre du module « Modélisation SystemC ». Ces TP sont destinés à initier les étudiants à la modélisation de systèmes et circuits numériques en SystemC-TLM et sont organisés autour de la suite logicielle open source Eclipse et de la chaine de compilation gcc pour la simulation, test et vérification.
APA, Harvard, Vancouver, ISO, and other styles
4

Chen, Mingsong, Prabhat Mishra, and Dhrubajyoti Kalita. "Automatic RTL Test Generation from SystemC TLM Specifications." ACM Transactions on Embedded Computing Systems 11, no. 2 (July 2012): 1–25. http://dx.doi.org/10.1145/2220336.2220350.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Zimmermann, Thomas, Mathias Mora, Sebastian Steinhorst, Daniel Mueller-Gritschneder, and Andreas Jossen. "Analysis of Dissipative Losses in Modular Reconfigurable Energy Storage Systems Using SystemC TLM and SystemC-AMS." ACM Transactions on Design Automation of Electronic Systems 24, no. 4 (July 24, 2019): 1–33. http://dx.doi.org/10.1145/3321387.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Bombieri, Nicola, Franco Fummi, Valerio Guarnieri, and Graziano Pravadelli. "Testbench Qualification of SystemC TLM Protocols through Mutation Analysis." IEEE Transactions on Computers 63, no. 5 (May 2014): 1248–61. http://dx.doi.org/10.1109/tc.2012.301.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Pierre, Laurence, and Luca Ferro. "A Tractable and Fast Method for Monitoring SystemC TLM Specifications." IEEE Transactions on Computers 57, no. 10 (October 2008): 1346–56. http://dx.doi.org/10.1109/tc.2008.74.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Bombieri, Nicola, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli, Francesco Stefanni, Tara Ghasempouri, Michele Lora, Giovanni Auditore, and Mirella Negro Marcigaglia. "Reusing RTL Assertion Checkers for Verification of SystemC TLM Models." Journal of Electronic Testing 31, no. 2 (March 20, 2015): 167–80. http://dx.doi.org/10.1007/s10836-015-5514-8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Cheng, Zhongqi, and Rainer Dömer. "Analyzing Variable Entanglement for Parallel Simulation of SystemC TLM-2.0 Models." ACM Transactions on Embedded Computing Systems 18, no. 5s (October 19, 2019): 1–20. http://dx.doi.org/10.1145/3358194.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

ESCOBAR-JUZGA, F. A., and F. E. SEGURA-QUIJANO. "PERFORMANCE ANALYSIS OF A JPEG ENCODER MAPPED ONTO A VIRTUAL MPSoC-NoC ARCHITECTURE USING TLM 2.0.1." Journal of Circuits, Systems and Computers 22, no. 05 (May 9, 2013): 1350036. http://dx.doi.org/10.1142/s0218126613500369.

Full text
Abstract:
Networks on Chip (NoCs) are commonly used to integrate complex embedded systems and multiprocessor platforms due to their scalability and versatility. Modeling tools used at the functional level use SystemC to perform hardware–software co-design and error correction concurrently, thus, reducing time to market. This work analyzes a JPEG encoding algorithm mapped onto a configurable M × N, mesh/torus, NoC platform described in SystemC with the transaction level modeling (TLM) standard; timing constraints for both, the router and network interface controller, are assigned according to a hardware description language (HDL) model written for this purpose. Processing nodes are also described as SystemC threads and their computation delays are assigned depending on the amount and cost of the operations they perform. The programming model employed is message passing. We start by describing and profiling the JPEG algorithm as a task graph; then, four partitioning proposals are mapped onto three NoCs of different size. Our analysis comprises changes in topology, virtual channel depth, routing algorithms, network speed and task-node assignments. Through several high-level simulations we evaluate the impact of each parameter and we show that, for the proposed model, most improvements come from the algorithm partitioning.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "SystemC TLM"

1

Montón, i. Macián Màrius. "Checkpointing for virtual platforms and systemC-TLM-2.0." Doctoral thesis, Universitat Autònoma de Barcelona, 2010. http://hdl.handle.net/10803/32099.

Full text
Abstract:
Un dels avantatges d'usar plataformes virtuals o prototipat virtual enlloc del maquinari real pel desenvolupament de programari encastat és la capacitat d'alguns simuladors de fer captures del seu estat. Si el model del sistema complet és prou detallat, pot tardar uns quants minuts (inclús hores) per simular l'engegada d'un Sistema Operatiu. Si es pren una captura just després de que ha acabat d'engegar, cada cop que calgui corre el programari encastat, els dissenyadors poden simplement recuperar la captura i continuar-la. Recuperar una captura normalment porta pocs segons. Aquest guany es trasllada en una major productivitat, especialment quan es treballa amb sistemes encastat, amb programari complex sobre Sistemes Operatius com en els dispositius actuals. En aquesta tesi es presenta en primer lloc el treball realitzat per afegir un llenguatge de descripció de sistemes anomenat SystemC a dues plataformes virtuals diferents. Aquesta tasca es realitzà per una eina comercial i desprès es traslladà a una plataforma de codi obert. També es presenta una sèrie de modificacions al llenguatge SystemC per suportar la captura d'instantànies. Aquestes modificacions faran possible poder agafar l'estat de la simulació en SystemC i salvar-les al disc. Més tard, la simulació es pot recuperar en el mateix estat on es trobava, sense canvis en els seus components. Aquestes millores ajudaran al llenguatge SystemC a ser més àmpliament usat en el món de les Plataformes Virtuals.
One advantage of using a virtual platform or virtual prototype over real hardware for embedded software development and testing is the ability of some simulators to take checkpoints of their state. If the entire system model is detailed enough, it might take several minutes (or even hours) to simulate booting the O.S. If a snapshot of the simulation is saved just after it has finished booting, each time it is necessary to run the embedded software, designers can simply restore the snapshot and go. Restarting a checkpoint typically takes a few seconds. This can translate into a major productivity gain, especially when working with embedded system with complex SW stacks and O.S. like modern embedded devices. In this dissertation we present in firstly our work on adding a description level language as SystemC to two Virtual Platforms. This work was done for a commercial Virtual Platform, and later translated to a open-sourced Platform. This thesis also presents a set of modifications to SystemC language to support checkpointing. These modifications will make it possible to take the state of a SystemC running simulation and save it to disk. Later, the same simulation can be restored to the same point it was before, without any change to the simulated modules. These changes would help SystemC to be suitable for use by Virtual Platforms as a description language.
APA, Harvard, Vancouver, ISO, and other styles
2

Ferro, Luca. "Vérification de propriétés logico-temporelles de spécifications SystemC TLM." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00633069.

Full text
Abstract:
Au-delà de la formidable évolution en termes de complexité du circuit électronique en soi, son adoption et sa diffusion ont connu, au fil des dernières années, une explosion dans un très grand nombre de domaines distincts. Un système sur puce peut incorporer une combinaison de composants aux fonctionnalités très différentes. S'assurer du bon fonctionnement de chaque composant, et du système complet, est une tâche primordiale et épineuse. Dans ce contexte, l'Assertion-Based Verification (ABV) a considérablement gagné en popularité ces dernières années : il s'agit d'une démarche de vérification où des propriétés logico-temporelles, exprimées dans des langages tels que PSL ou SVA, spécifient le comportement attendu du design. Alors que la plupart des solutions d'ABV existantes se limitent au niveau transfert de registres (RTL), la contribution décrite dans cette thèse s'efforce de résoudre un certain nombre de limitations et vise ainsi une solution mature pour le niveau transactionnel (TLM) de SystemC. Une technique efficace de construction de moniteurs de surveillance à partir de propriétés PSL est proposée : cette technique, inspirée d'une approche originale existante pour le niveau RTL, est ici adaptée à SystemC TLM. Une méthode spécifique de surveillance des actions de communication à haut niveau d'abstraction est également détaillée. Les possibilités offertes par la technique présentée sont significativement étendues en proposant, pour les propriétés écrites en langage PSL, à la fois un support formel et une mise en oeuvre pratique pour des variables auxiliaires globales et locales, qui constituent un élément essentiel lors des spécifications à haut niveau d'abstraction. Tous ces concepts sont également implémentés dans un outil prototype. Afin d'illustrer l'intérêt de la solution proposée, diverses expérimentations sont effectuées avec des designs aux dimensions et complexités différentes. Les résultats obtenus permettent de souligner le fait que la méthode de vérification dynamique suggérée reste applicable pour des designs de taille réaliste.
APA, Harvard, Vancouver, ISO, and other styles
3

Delbergue, Guillaume. "Advances in SystemC/TLM virtual platforms : configuration, communication and parallelism." Thesis, Bordeaux, 2017. http://www.theses.fr/2017BORD0916/document.

Full text
Abstract:
Le marché de l’Internet des Objets (IdO) est en pleine progression. Il va continuer à croître et à se développer à un rythme soutenu dans les prochaines années. Les objets connectés sont constitués de composants électroniques dédiés, de processeurs et de codes logiciels. La conception de tels systèmes constitue aujourd’hui un challenge au niveau industriel. Ce challenge est renforcé par la concurrence du marché et le délai de commercialisation qui impactent directement sur le développement d’un système. Le processus de conception actuel consiste en l’élaboration d’un cahier des charges. Dans un premier temps, l’équipe en charge du développement matériel commence à développer le produit. Ensuite, la partie applicative peut être mise au point par les développeurs logiciels. Une fois le premier prototype matériel disponible, l’équipe logicielle peut alors intégrer sa partie et tenter de la valider fonctionnellement. Cette étape peut mettre en lumière des défauts dans le logiciel mais aussi lors de la conception matérielle. Malheureusement,la découverte ce type d’erreurs intervient beaucoup trop tard dans le processus de conception retardant la commercialisation du système. Afin de sécuriser au plus tôt les développements matériel et logiciel, des méthodologies basées sur le standard SystemC/Transaction Level Modeling (TLM) ont été proposées. Elles permettent de modéliser et de simuler du matériel. Durant les phases amont de conception d’un système, elles permettent de mettre en commun une version virtuelle du (futur) système entre les équipes logicielle et matérielle. Cette version virtuelle est plus couramment appelée plateforme virtuelle. Elle permet de tester et de valider le plus tôt possible lors du cycle de conception, de réduire le coût matériel en limitant la fabrication de prototypes, mais aussi de gagner du temps et donc de l’argent en diminuant les risques. Or, les objets intègrent de plus en plus de fonctionnalités aux niveaux matériel et logiciel. Les besoins ayant évolué, le standard de simulation SystemC/TLM ne répond plus à l’heure actuelle à toutes les attentes. Ces attentes concernent plus particulièrement les aspects liés à la simulation de systèmes composés de nombreuses fonctionnalités, de protocoles de communication disparates mais aussi de modèles complexes et consommateur de temps pendant la simulation. Des activités de recherche ont déjà été menées sur ces sujets. Cependant, elles ont pour la plupart abouti à des solutions qui ne sont pas interopérables. Les solutions existantes ne permettent donc pas de bénéficier de la réutilisation des modèles de la littérature. Afin de répondre à ces problèmes,une solution permettant la configuration de modèles SystemC/TLM a été recherchée. Cette dernière fait désormais partie du standard Configuration, Control and Inspection (CCI). Dans un second temps, la modélisation de protocoles de communication à un haut niveau d’abstraction(TLM Loosely Timed (LT) et Approximately Timed (AT)) a été étudiée, et plus précisément des protocoles de type non bus. Une évolution du standard actuel permettant d’améliorer le support,l’interopérabilité, la réutilisation a été proposée dans le cadre de la thèse. Ensuite, une évolution du standard SystemC et plus précisément du comportement du noyau de simulation a été étudiée pour supporter l’attente d’événements asynchrones. Ce type d’événement ouvre la voie à la parallélisation et la distribution de modèles sur différents threads / machines. Enfin, une solution permettant l’intégration de modèles de Central Processing Units (CPU) intégrés dans QuickEMUlator (QEMU), un émulateur / virtualisateur de système, a été étudiée. Finalement, toutes ces contributions ont été associées à travers la modélisation d’un ensemble d’objets connectés à une passerelle
The market for Internet Of Things (IOT) is on the rise. It is predicted to continue to grow at a sustained pace in the coming years. Connected objects are composed of dedicated electronic components, processors and software. The design of such systems is today a challenge from an industrial point of view. This challenge is reinforced by market competition and time tomarket that directly impact the success of a system. In a current design process involvesthe development of a specification. Initially, the team in charge of hardware development beginsto design the system. Second, the application part can be done by software developers. Oncethe first hardware prototype is available, the software team can then integrate their part and try tovalidate the functionality. This step may reveal defects in the software but also in the hardware architecture. Unfortunately, the discovery of these errors occurs far too late in the design process,could impacts the marketing of the system and potentially its success. In order to ensure that the hardware and software designs will work together as early as possible, methodologies based onthe SystemC / Transaction Level Modeling (TLM) standard have been widely adopted. They involvethe modelling and simulation of the proposed hardware architectures. During the initial phasesof a product’s design, they enable the software and hardware team to share a virtual version ofthe (future) system. This virtual version is more commonly referred to as a virtual platform. It facilitates early software development, test and validation; reduces material cost by limiting the number of prototypes; saves time and money by reducing risks. However, connected objects are increasingly incorporating hardware and software features. As the requirements have evolved, theSystemC / TLM simulation standard no longer meets all expectations. It includes aspects related to the simulation of systems composed of many functionality, disparate communication protocolsbut also complex and time consuming models during the simulation. Some works have already been carried out on these subjects. However, as the number of components increases, all formsof interoperability of models and tools become increasingly difficult to handle. Moreover, mostof the research has resulted in solutions that are not inter-operable and can not reuse existingmodels. To solve these problems, this thesis proposes a solution for configuring SystemC / TLMmodels. It is now part of the standard Configuration, Control and Inspection (CCI). In a secondstep, the modeling of high-level abstraction communication protocols (TLM Loosely Timed (LT)and Approximately Timed (AT)) has been studied, as it relates to non-bus protocols. An evolution of the standard to improve support, interoperability and reuse is also proposed. In a third step,a change of the SystemC standard and more precisely of the behavior of the simulation kernelhas been studied to support asynchronous events. These open the way to parallelization and distribution of models on different threads / machines. In a fourth step, a solution to integrate Central Processing Units (CPU) models integrated in Quick EMUlator (QEMU), a system emulator/ virtualizer, has been studied. Finally, all these contributions have been applied in the modeling ofa set of objects connected to a gateway
APA, Harvard, Vancouver, ISO, and other styles
4

Hayat, Zeeshan. "Evaluating Parallelization Potential for a SystemC/TLM-based Virtual Platform." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-254883.

Full text
Abstract:
System on chip (SoC) solutions, with integrated hardware and embedded software, are increasing in size and complexity. To cope with the market demand for complex SoC, the abstraction level used during development is raised to allow co-development of software (SW) and hardware (HW). Functional and bit-accurate simulators, referred to as Virtual Platforms, play a vital role in co-development of HW and SW. A virtual platform supports early development, testing, and verification of the embedded SW. However, as the complexity of SoC is increasing so does the complexity of virtual platforms, which is a major bottleneck in the performance of the virtual platforms.SystemC is an industry standard supporting development of hardware models. SystemC uses co-routine semantics, also known as co-operative multitasking, for the control of simulation. A single process is active at any time. This means that the potential for parallelism, by executing a SystemC simulation on multiple cores in a modern multi-core processor, is not utilized.This thesis work proposes a parallelization algorithm for SystemC simulations, where one SystemC thread controls a set of parallel host threads. A proof of concept trace-driven simulator is developed to verify the results from the proposed algorithm. Also, an optimized algorithm is proposed which improves the simulation speed. Furthermore, the behavior of the simulator is analyzed by looking into traces, from the Linux kernel and user application level traces, with the help of an open source tracing framework known as LTTng.The trace-driven simulator is used for evaluation of the parallelization potential for SVP, a virtual platform used at Ericsson. The evaluation makes it possible to determine, for the ideal case when the threads execute independently, the maximum possible speedup for a given test case. Using test cases from production usage, an evaluation of the possible performance improvements for SVP can be done.
System på chip (SoC) -lösningar, med integrerad hårdvara och inbyggd programvara, ökar i storlek och komplexitet. För att klara av marknadens efterfrågan på komplexa SoC höjs den abstraktionsnivå som används under utveckling, för att möjliggöra samutveckling av programvara (SW) och hårdvara (HW). Funktionella och bitexakta simulatorer, benämnda virtuella plattformar, spelar en viktig roll vid samutveckling av HW och SW. En virtuell plattform stöder tidig utveckling, samt testning och verifiering av den inbäddade programvaran. Eftersom komplexiteten i SoC ökar så ökar även komplexiteten hos virtuella plattformar, vilket begränsar prestandan för de virtuella plattformarna.SystemC är en industristandard som stöder utveckling av hårdvarumodeller. SystemC använder händelse-styrd simulering. I ett give tidsögonblick är endast en process aktiv. Detta innebär att potentialen för parallelism, genom att utföra en SystemC-simulering på flera kärnor i en modern multi-core-processor, inte utnyttjas.Detta examensarbete presenterar en parallelliseringsalgoritm för SystemC-simuleringar, där en SystemC-tråd styr en uppsättning parallella värdtrådar. En data-driven simulator, som använder sig av inspelade data från en virtuell plattform, utvecklad för att verifiera resultaten från den föreslagna algoritmen. Dessutom föreslås en optimerad algoritm som förbättrar simuleringshastigheten. Dessutom analyseras beteendet hos simulatorn genom att presentera process-akiviteter, från Linuxkärnan samt från applikationen, met de hulp van een open source tracing framework bekend als LTTng.Den data-drivna simulatorn används för utvärdering av parallelliseringspotentialen för SVP, en virtuell plattform som används på Ericsson. Utvärderingen gör det möjligt att, för det ideala fallet när trådarna exekverar helt parallellt bestämma maximal möjlig hastighet för ett givet testfall. Genom att använda testfall från produktionskod kan en utvärdering av möjliga prestandaförbättringar för SVP utföras.
APA, Harvard, Vancouver, ISO, and other styles
5

Li, Fangyan. "Simulation multi-moteurs multi-niveaux pour la validation des spécifications système et optimisation de la consommation." Thesis, Nice, 2016. http://www.theses.fr/2016NICE4008/document.

Full text
Abstract:
Ce travail vise la modélisation au niveau système, en langage SystemC-AMS, et la simulation d'un émetteur-récepteur au standard Bluetooth Low Energy (BLE). L'objectif est d'analyser la relation entre les performances, en termes de BER et la consommation d'énergie du transceiver. Le temps de simulation d’un tel système, à partir de cas d’étude (use case) réaliste, est un facteur clé pour le développement d’une telle plateforme. De plus, afin d’obtenir des résultats de simulation le plus précis possible, les modèles « haut niveau » doivent être raffinés à partir de modèles plus bas niveau où de mesure. L'approche dite Meet-in-the-Middle, associée à la méthode de modélisation équivalente en Bande Base (BBE, BaseBand Equivalent), a été choisie pour atteindre les deux conditions requises, à savoir temps de simulation « faible » et précision des résultats. Une simulation globale d'un système de BLE est obtenue en intégrant le modèle de l'émetteur-récepteur dans une plateforme existante développée en SystemC-TLM. La simulation est basée sur un système de communication de deux dispositifs BLE, en utilisant différents scénarios (différents cas d'utilisation de BLE). Dans un premier temps nous avons modélisé et validé chaque bloc d’un transceiver BT. Devant le temps de simulation prohibitif, les blocs RF sont réécrits en utilisant la méthodologie BB, puis raffinés afin de prendre en compte les non-linéarités qui vont impacter le couple consommation, BER. Chaque circuit (chaque modèle) est vérifié séparément, puis une première simulation système (point à point entre un émetteur et un récepteur) est effectuée
This work aims at system-level modelling a defined transceiver for Bluetooth Low energy (BLE) system using SystemC-AMS. The goal is to analyze the relationship between the transceiver performance and the accurate energy consumption. This requires the transceiver model contains system-level simulation speed and the low-level design block power consumption and other RF specifications. The Meet-in-the-Middle approach and the Baseband Equivalent method are chosen to achieve the two requirements above. A global simulation of a complete BLE system is achieved by integrating the transceiver model into a SystemC-TLM described BLE system model which contains the higher-than-PHY levels. The simulation is based on a two BLE devices communication system and is run with different BLE use cases. The transceiver Bit-Error-Rate and the energy estimation are obtained at the end of the simulation. First, we modelled and validated each block of a BT transceiver. In front of the prohibitive simulation time, the RF blocks are rewritten by using the BBE methodology, and then refined in order to take into account the non-linearities, which are going to impact the couple consumption, BER. Each circuit (each model) is separately verified, and then a first BLE system simulation (point-to-point between a transmitter and a receiver) has been executed. Finally, the BER is finally estimated. This platform fulfills our expectations, the simulation time is suitable and the results have been validated with the circuit measurement offered by Riviera Waves Company. Finally, two versions of the same transceiver architecture are modelled, simulated and compared
APA, Harvard, Vancouver, ISO, and other styles
6

Belhadj, Amor Zeineb. "Validation de systèmes sur puce complexes du niveau transactionnel au niveau transfert de registres." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT083/document.

Full text
Abstract:
Cette thèse se situe dans le contexte de la vérification fonctionnelle des circuits intégrés complexes. L’objectif de ce travail est de créer un flot de vérification conjoint au flot de conception basé sur une technique appelée "vérification basée sur les assertions(ABV)". Le concept de base du flot est le raffinement automatique des spécifications formelles données sous la forme d’assertions PSL du niveau TLM au niveau RTL. La principale difficulté est la disparité des deux domaines : au niveau TLM, les communications sont modélisées par des appels de fonctions atomiques. Au niveau RTL, les échanges sont assurés par des signaux binaires évoluant selon un protocole de communication précis. Sur la base d’un ensemble de règles de transformation temporelles formelles, nous avons réalisé un outil permettant d’automatiser le raffinement de ces spécifications. Comme le raffinement des modèles, le raffinement des assertions n’est pas entièrement automatisable : des informations temporelles et structurelles doivent être fournies par l’utilisateur. L’outil réalise la saisie de ces informations de façon ergonomique, puis procède automatiquement à la transformation temporelle et structurelle de l’assertion. Il permet la génération d’assertions RTL mais aussi hybrides. Les travaux antérieurs dans ce domaine sont peu nombreux et les solutions proposées imposent de fortes restrictions sur les assertions considérées. À notre connaissance, le prototype que nous avons mis en oeuvre est le premier outil qui réalise un raffinement temporel fondé sur la sémantique formelle d’un langage de spécification standard (PSL)
The context of this thesis is the functional verification of complex integrated circuits.The objective of our work is to create a seamless verification flow joint to the design flowand based on a proved technique called Assertions-Based Verification (ABV). The mainchallenge of TLM to RTL refinement is the disparity of these two domains : at TLM,communications are modeled as atomic function calls handling all the exchanged data.At RTL, communications are performed by signals according to a specific communicationprotocol. The proposed temporal transformation process is based on a set of formaltransformation rules. We have developed a tool performing the automatic refinement ofPSL specifications. As for design refinement assertion refinement is not fully automated.Temporal and structural information must be provided by the user, using an ergonomicinterface. The tool allows the generation of assertions in RTL but also hybrid assertions.Little work has been done before in this area, and the proposed solutions suffer from severerestrictions. To our knowledge, our prototype is the first tool that performs a temporaltransformation of assertions based on the formal semantics of a standard specificationlanguage (PSL)
APA, Harvard, Vancouver, ISO, and other styles
7

Flórez, Martha Johanna Sepúlveda. "Estimativa de desempenho de uma NoC a partir de seu modelo em SYSTEMC-TLM." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14122006-152854/.

Full text
Abstract:
The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.
The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.
APA, Harvard, Vancouver, ISO, and other styles
8

Viaud, Emmanuel. "Modélisation SystemC d'architectures multi-processeurs intégrées sur puce au niveau transactionnel avec représentation du temps." Paris 6, 2009. http://www.theses.fr/2009PA066118.

Full text
Abstract:
Cette thèse présente les principes théoriques et l'implémentation pratique d'une méthode originale de modélisation transactionnelle avec temps (Transaction Level Modeling with Time, TLM-T) de plates-formes numériques multi-processeurs complexes à mémoire partagée. S'appuyant sur le niveau d'abstraction TLM (standard de l'Open SystemC Initiative), cette méthode rend possible l'exploration architecturale et facilite le développement du logiciel embarqué, tout en considérant les phénomènes de contention dynamique ignorés par TLM qui impactent grandement les performances temporelles. La méthode présentée permet d'obtenir un gain d'un ordre de grandeur par rapport à la simulation précise au cycle tout en gardant une précision temporelle des résultats obtenus de l'ordre de 5%.
APA, Harvard, Vancouver, ISO, and other styles
9

Karlsson, Sara. "Micro NPU for Baseband Interconnect." Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103681.

Full text
Abstract:
The aim of this work is to investigate the possibility to implement a configurable NPU (Network Processing Unit) in the next generation of Ericsson’s EMCAs (Ericsson Multi Core Architecture). The NPU is constructed so that it can be configured for either Ethernet or xIO-s, as either a transmitter or a receiver. The motive for doing the work is that many protocols have similar functions and there could be possible advantages to have a configurable protocol choice in future hardware. A model of a NPU will be created in SystemC using the TLM 2.0 interface. The model will be analyzed to evaluate its complexity regarding a possible modification to also make it configurable for CPRI. The result that is presented is that it would be possible to implement a configurable NPU in the future EMCAs. The result is based on the conclusion that the protocols use many similar functions and most of the blocks could be made configurable for use with different protocols. Configurable blocks would benefit a configurable NPU as it would require fewer resources than separate blocks for each protocol.
APA, Harvard, Vancouver, ISO, and other styles
10

Liang, Lei. "Design and Implementation of an Extendable SoC Virtual Platform in SystemC-TLM 2.0." Thesis, KTH, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-98661.

Full text
Abstract:
With the increasing design complexity for SoC development, the workload for hardware designer and verification engineer is becoming larger and larger. On the other hand, software and hardware development is unable to be carried out in parallel. This creates a bottleneck in the current design flow. Also, it will be very difficult to deal with the hardware problems which are found during the software development process. To overcome these problems, design at higher level needs to be applied. SystemC is a language which enables the design at the system level and the TLM-2.0 contains different standardized SystemC interface classes, which ensures the portability and interoperability of different IPs. In this thesis, an extendable SoC virtual platform is implemented in SystemC. It can give exactly the same functions as the design specification required. A standardized SystemC module template is designed which owns all different interfaces of the virtual platform. The template can provide lots of convenience for future module development. One method for wrapping a C/C++ into SystemC is given and a basic framework structure is implemented so that the existing C++/Simics modules can work in the designed SystemC virtual platform. Finally, the comparison on simulation time and workload between RTL modules and SystemC modules is made, which demonstrates that large development time can be saved by using this virtual platform for software development.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "SystemC TLM"

1

Wong, Allan K. Y., Jackei H. K. Wong, Wilfred W. K. Lin, Tharam S. Dillon, and Elizabeth J. Chang. Semantically Based Clinical TCM Telemedicine Systems. Berlin, Heidelberg: Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-46024-5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Hasegawa, Akira, ed. Massive WDM and TDM Soliton Transmission Systems. Dordrecht: Springer Netherlands, 2002. http://dx.doi.org/10.1007/0-306-47125-6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Tam zamanında tedarik sözleşmesi. Ankara: Yetkin Yayınları, 2011.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Jeffery, Hicks, and Microsoft Corporation, eds. Windows PowerShell: TFM. Napa, Calif: Sapien Press, 2006.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

Specifying systems: The TLA+ language and tools for hardware and software engineers. Boston: Addison-Wesley, 2003.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Emre, Aynur. Tam zamanında üretim sisteminin ülkemizdeki uygulamaları ve sorunları. Ankara: Millı̂ Prodüktivite Merkezi, 1995.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Lamport, Leslie. Specifying systems: The TLA [plus] language and tools for hardware and software engineers. Boston: Addison-Wesley, 2003.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Jones, Don. Windows PowerShell 2.0: TFM. 3rd ed. Napa, Calif: SAPIEN, 2010.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Akira, Hasegawa. Massive WDM and TDM soliton transmission systems: A ROSC symposium. New York: Kluwer Academic, 2002.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

System wyborczy do samorządu terytorialnego w Polsce na tle europejskim. Toruń: Wydawn. Adam Marszałek, 2008.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "SystemC TLM"

1

Black, David C., Jack Donovan, Bill Bunton, and Anna Keist. "OSCI TLM." In SystemC: From the Ground Up, 207–21. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-69958-5_16.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Maillet-Contoz, Laurent, and Jean-Philippe Strassen. "TLM Modeling Techniques." In Transaction Level Modeling with SystemC, 57–94. Boston, MA: Springer US, 2005. http://dx.doi.org/10.1007/0-387-26233-4_3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Black, David C., Jack Donovan, Bill Bunton, and Anna Keist. "Why SYSTEMC: ESL and TLM." In SystemC: From the Ground Up, 1–18. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-0-387-69958-5_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Greaves, David, and Mehboob Yasin. "TLM POWER3: Power Estimation Methodology for SystemC TLM 2.0." In Lecture Notes in Electrical Engineering, 53–68. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-01418-0_4.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Traulsen, Claus, Jérôme Cornet, Matthieu Moy, and Florence Maraninchi. "A SystemC/TLM Semantics in Promela and Its Possible Applications." In Model Checking Software, 204–22. Berlin, Heidelberg: Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-73370-6_14.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Steiner, Lukas, Matthias Jung, Felipe S. Prado, Kirill Bykov, and Norbert Wehn. "DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator." In Lecture Notes in Computer Science, 110–26. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-60939-9_8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Hajisheykhi, Reza, Ali Ebnenasir, and Sandeep S. Kulkarni. "Evaluating the Effect of Faults in SystemC TLM Models Using UPPAAL." In Software Engineering and Formal Methods, 175–89. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-10431-7_13.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Zhang, Zhenkai, and Xenofon Koutsoukos. "Modeling Time-Triggered Ethernet in SystemC/TLM for Virtual Prototyping of Cyber-Physical Systems." In IFIP Advances in Information and Communication Technology, 318–30. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-38853-8_29.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Sauer, Christian, Hans-Martin Bluethgen, and Hans-Peter Loeb. "A Framework for Distributed, Loosely-Synchronized Simulation of Complex SystemC/TLM Models." In Lecture Notes in Electrical Engineering, 135–53. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-24457-0_8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Stamatiadis-Smidt, Hilke, and Harald zur Hausen. "TNM-System." In Thema Krebs, 303–5. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/978-3-662-10418-7_88.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "SystemC TLM"

1

Le, Hoang M., Daniel Große, and Rolf Drechsler. "Automatic Fault Localization for SystemC TLM Designs." In 2010 11th International Workshop on Microprocessor Test and Verification (MTV). IEEE, 2010. http://dx.doi.org/10.1109/mtv.2010.15.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Alemzadeh, Homa, Marco Cimei, Paolo Prinetto, and Zainalabedin Navabi. "Facilitating testability of TLM FIFO: SystemC implementations." In Test Symposium (EWDTS). IEEE, 2010. http://dx.doi.org/10.1109/ewdts.2010.5742035.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Guarnieri, Valerio, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, and Raimund Ubar. "Mutation analysis for SystemC designs at TLM." In 2011 12th Latin American Test Workshop - LATW. IEEE, 2011. http://dx.doi.org/10.1109/latw.2011.5985925.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Le, Hoang M., Daniel Grosse, and Rolf Drechsler. "Scalable Fault Localization for SystemC TLM Designs." In Design Automation and Test in Europe. New Jersey: IEEE Conference Publications, 2013. http://dx.doi.org/10.7873/date.2013.022.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Maraninchi, Florence, Matthieu Moy, Jerome Cornet, Laurent Maillet-Contoz, Claude Helmstetter, and Claus Traulsen. "SystemC/TLM semantics for heterogeneous system-on-chip validation." In 2008 Joint International IEEE Northeast Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA). IEEE, 2008. http://dx.doi.org/10.1109/newcas.2008.4606376.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Grosse, Daniel, Hoang M. Le, and Rolf Drechsler. "Induction-Based Formal Verification of SystemC TLM Designs." In 2009 10th International Workshop on Microprocessor Test and Verification (MTV). IEEE, 2009. http://dx.doi.org/10.1109/mtv.2009.16.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Zhaorong Xiong, Jinian Bian, and Yanni Zhao. "An assertion-based verification method for SystemC TLM." In 2010 International Conference on Communications, Circuits and Systems (ICCCAS). IEEE, 2010. http://dx.doi.org/10.1109/icccas.2010.5581859.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Sfar, Salaheddine Hamza, Rached Tourki, and Imed Bennour. "Stepwise SystemC/TLM-2 models structuring and optimizations." In 2016 11th International Design & Test Symposium (IDT). IEEE, 2016. http://dx.doi.org/10.1109/idt.2016.7843040.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Mingsong Chen, Prabhat Mishra, and Dhrubajyoti Kalita. "Towards RTL test generation from SystemC TLM specifications." In 2007 IEEE International High Level Design Validation and Test Workshop. IEEE, 2007. http://dx.doi.org/10.1109/hldvt.2007.4392793.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Yu Lo, Lucky Lo Chi, and Samar Abdi. "Automatic SystemC TLM generation for custom communication platforms." In 2007 25th International Conference on Computer Design ICCD 2007. IEEE, 2007. http://dx.doi.org/10.1109/iccd.2007.4601878.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "SystemC TLM"

1

Partin, J. K., G. D. Lassahn, and J. R. Davidson. Automatic TLI recognition system. Part 1: System description. Office of Scientific and Technical Information (OSTI), May 1994. http://dx.doi.org/10.2172/10166991.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Lassahn, G. D. Automatic TLI recognition system, general description. Office of Scientific and Technical Information (OSTI), February 1997. http://dx.doi.org/10.2172/481877.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Lassahn, G. D. Automatic TLI recognition system, programmer`s guide. Office of Scientific and Technical Information (OSTI), February 1997. http://dx.doi.org/10.2172/481865.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Lassahn, G. D. Automatic TLI recognition system, user`s guide. Office of Scientific and Technical Information (OSTI), February 1997. http://dx.doi.org/10.2172/481878.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Lassahn, G. D. Automatic TLI recognition system beta prototype testing. Office of Scientific and Technical Information (OSTI), June 1996. http://dx.doi.org/10.2172/266745.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Lassahn, G. D., J. K. Partin, and J. R. Davidson. Automatic TLI recognition system evaluation using AMPS data. Office of Scientific and Technical Information (OSTI), March 1995. http://dx.doi.org/10.2172/130622.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Serhrouchni, A., and H. Labiod. TLS Authentication Using Intelligent Transport System (ITS) Certificates. Edited by M. Msahli, N. Cam-Winget, and W. Whyte. RFC Editor, September 2020. http://dx.doi.org/10.17487/rfc8902.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Snyder, D. D., Scott C. MacInnes, and Jennifer L. Hare. A Fast 4-D TEM System for UXO Characterization. Fort Belvoir, VA: Defense Technical Information Center, July 2003. http://dx.doi.org/10.21236/ada442592.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Snyder, D. D. A Fast 4-D TEM System for UXO Characterization. Fort Belvoir, VA: Defense Technical Information Center, November 2004. http://dx.doi.org/10.21236/ada607147.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Partin, J. K., G. D. Lassahn, and J. R. Davidson. Automatic TLI recognition system. Part 2: User`s guide. Office of Scientific and Technical Information (OSTI), May 1994. http://dx.doi.org/10.2172/10166988.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'SystemC TLM' for particular source types:
Journal articles Dissertations / Theses Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography