To see the other types of publications on this topic, follow the link: SystemC TLM.
Dissertations / Theses on the topic 'SystemC TLM'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 dissertations / theses for your research on the topic 'SystemC TLM.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Montón, i. Macián Màrius. "Checkpointing for virtual platforms and systemC-TLM-2.0." Doctoral thesis, Universitat Autònoma de Barcelona, 2010. http://hdl.handle.net/10803/32099.
Full textAbstract:
Un dels avantatges d'usar plataformes virtuals o prototipat virtual enlloc del maquinari real pel desenvolupament de programari encastat és la capacitat d'alguns simuladors de fer captures del seu estat.
Si el model del sistema complet és prou detallat, pot tardar uns quants minuts (inclús hores) per simular l'engegada d'un Sistema Operatiu. Si es pren una captura just després de que ha acabat d'engegar, cada cop que calgui corre el programari encastat, els dissenyadors poden simplement recuperar la captura i continuar-la. Recuperar una captura normalment porta pocs segons. Aquest guany es trasllada en una major productivitat, especialment quan es treballa amb sistemes encastat, amb programari complex sobre Sistemes Operatius com en els dispositius actuals.
En aquesta tesi es presenta en primer lloc el treball realitzat per afegir un llenguatge de descripció de sistemes anomenat SystemC a dues plataformes virtuals diferents. Aquesta tasca es realitzà per una eina comercial i desprès es traslladà a una plataforma de codi obert.
També es presenta una sèrie de modificacions al llenguatge SystemC per suportar la captura d'instantànies. Aquestes modificacions faran possible poder agafar l'estat de la simulació en SystemC i salvar-les al disc. Més tard, la simulació es pot recuperar en el mateix estat on es trobava, sense canvis en els seus components. Aquestes millores ajudaran al llenguatge SystemC a ser més àmpliament usat en el món de les Plataformes Virtuals.One advantage of using a virtual platform or virtual prototype over real hardware for embedded software development and testing is the ability of some simulators to take checkpoints of their state. If the entire system model is detailed enough, it might take several minutes (or even hours) to simulate booting the O.S. If a snapshot of the simulation is saved just after it has finished booting, each time it is necessary to run the embedded software, designers can simply restore the snapshot and go. Restarting a checkpoint typically takes a few seconds. This can translate into a major productivity gain, especially when working with embedded system with complex SW stacks and O.S. like modern embedded devices. In this dissertation we present in firstly our work on adding a description level language as SystemC to two Virtual Platforms. This work was done for a commercial Virtual Platform, and later translated to a open-sourced Platform. This thesis also presents a set of modifications to SystemC language to support checkpointing. These modifications will make it possible to take the state of a SystemC running simulation and save it to disk. Later, the same simulation can be restored to the same point it was before, without any change to the simulated modules. These changes would help SystemC to be suitable for use by Virtual Platforms as a description language.
2
Ferro, Luca. "Vérification de propriétés logico-temporelles de spécifications SystemC TLM." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00633069.
Full textAbstract:
Au-delà de la formidable évolution en termes de complexité du circuit électronique en soi, son adoption et sa diffusion ont connu, au fil des dernières années, une explosion dans un très grand nombre de domaines distincts. Un système sur puce peut incorporer une combinaison de composants aux fonctionnalités très différentes. S'assurer du bon fonctionnement de chaque composant, et du système complet, est une tâche primordiale et épineuse. Dans ce contexte, l'Assertion-Based Verification (ABV) a considérablement gagné en popularité ces dernières années : il s'agit d'une démarche de vérification où des propriétés logico-temporelles, exprimées dans des langages tels que PSL ou SVA, spécifient le comportement attendu du design. Alors que la plupart des solutions d'ABV existantes se limitent au niveau transfert de registres (RTL), la contribution décrite dans cette thèse s'efforce de résoudre un certain nombre de limitations et vise ainsi une solution mature pour le niveau transactionnel (TLM) de SystemC. Une technique efficace de construction de moniteurs de surveillance à partir de propriétés PSL est proposée : cette technique, inspirée d'une approche originale existante pour le niveau RTL, est ici adaptée à SystemC TLM. Une méthode spécifique de surveillance des actions de communication à haut niveau d'abstraction est également détaillée. Les possibilités offertes par la technique présentée sont significativement étendues en proposant, pour les propriétés écrites en langage PSL, à la fois un support formel et une mise en oeuvre pratique pour des variables auxiliaires globales et locales, qui constituent un élément essentiel lors des spécifications à haut niveau d'abstraction. Tous ces concepts sont également implémentés dans un outil prototype. Afin d'illustrer l'intérêt de la solution proposée, diverses expérimentations sont effectuées avec des designs aux dimensions et complexités différentes. Les résultats obtenus permettent de souligner le fait que la méthode de vérification dynamique suggérée reste applicable pour des designs de taille réaliste.
3
Delbergue, Guillaume. "Advances in SystemC/TLM virtual platforms : configuration, communication and parallelism." Thesis, Bordeaux, 2017. http://www.theses.fr/2017BORD0916/document.
Full textAbstract:
Le marché de l’Internet des Objets (IdO) est en pleine progression. Il va continuer à croître et à se développer à un rythme soutenu dans les prochaines années. Les objets connectés sont constitués de composants électroniques dédiés, de processeurs et de codes logiciels. La conception de tels systèmes constitue aujourd’hui un challenge au niveau industriel. Ce challenge est renforcé par la concurrence du marché et le délai de commercialisation qui impactent directement sur le développement d’un système. Le processus de conception actuel consiste en l’élaboration d’un cahier des charges. Dans un premier temps, l’équipe en charge du développement matériel commence à développer le produit. Ensuite, la partie applicative peut être mise au point par les développeurs logiciels. Une fois le premier prototype matériel disponible, l’équipe logicielle peut alors intégrer sa partie et tenter de la valider fonctionnellement. Cette étape peut mettre en lumière des défauts dans le logiciel mais aussi lors de la conception matérielle. Malheureusement,la découverte ce type d’erreurs intervient beaucoup trop tard dans le processus de conception retardant la commercialisation du système. Afin de sécuriser au plus tôt les développements matériel et logiciel, des méthodologies basées sur le standard SystemC/Transaction Level Modeling (TLM) ont été proposées. Elles permettent de modéliser et de simuler du matériel. Durant les phases amont de conception d’un système, elles permettent de mettre en commun une version virtuelle du (futur) système entre les équipes logicielle et matérielle. Cette version virtuelle est plus couramment appelée plateforme virtuelle. Elle permet de tester et de valider le plus tôt possible lors du cycle de conception, de réduire le coût matériel en limitant la fabrication de prototypes, mais aussi de gagner du temps et donc de l’argent en diminuant les risques. Or, les objets intègrent de plus en plus de fonctionnalités aux niveaux matériel et logiciel. Les besoins ayant évolué, le standard de simulation SystemC/TLM ne répond plus à l’heure actuelle à toutes les attentes. Ces attentes concernent plus particulièrement les aspects liés à la simulation de systèmes composés de nombreuses fonctionnalités, de protocoles de communication disparates mais aussi de modèles complexes et consommateur de temps pendant la simulation. Des activités de recherche ont déjà été menées sur ces sujets. Cependant, elles ont pour la plupart abouti à des solutions qui ne sont pas interopérables. Les solutions existantes ne permettent donc pas de bénéficier de la réutilisation des modèles de la littérature. Afin de répondre à ces problèmes,une solution permettant la configuration de modèles SystemC/TLM a été recherchée. Cette dernière fait désormais partie du standard Configuration, Control and Inspection (CCI). Dans un second temps, la modélisation de protocoles de communication à un haut niveau d’abstraction(TLM Loosely Timed (LT) et Approximately Timed (AT)) a été étudiée, et plus précisément des protocoles de type non bus. Une évolution du standard actuel permettant d’améliorer le support,l’interopérabilité, la réutilisation a été proposée dans le cadre de la thèse. Ensuite, une évolution du standard SystemC et plus précisément du comportement du noyau de simulation a été étudiée pour supporter l’attente d’événements asynchrones. Ce type d’événement ouvre la voie à la parallélisation et la distribution de modèles sur différents threads / machines. Enfin, une solution permettant l’intégration de modèles de Central Processing Units (CPU) intégrés dans QuickEMUlator (QEMU), un émulateur / virtualisateur de système, a été étudiée. Finalement, toutes ces contributions ont été associées à travers la modélisation d’un ensemble d’objets connectés à une passerelleThe market for Internet Of Things (IOT) is on the rise. It is predicted to continue to grow at a sustained pace in the coming years. Connected objects are composed of dedicated electronic components, processors and software. The design of such systems is today a challenge from an industrial point of view. This challenge is reinforced by market competition and time tomarket that directly impact the success of a system. In a current design process involvesthe development of a specification. Initially, the team in charge of hardware development beginsto design the system. Second, the application part can be done by software developers. Oncethe first hardware prototype is available, the software team can then integrate their part and try tovalidate the functionality. This step may reveal defects in the software but also in the hardware architecture. Unfortunately, the discovery of these errors occurs far too late in the design process,could impacts the marketing of the system and potentially its success. In order to ensure that the hardware and software designs will work together as early as possible, methodologies based onthe SystemC / Transaction Level Modeling (TLM) standard have been widely adopted. They involvethe modelling and simulation of the proposed hardware architectures. During the initial phasesof a product’s design, they enable the software and hardware team to share a virtual version ofthe (future) system. This virtual version is more commonly referred to as a virtual platform. It facilitates early software development, test and validation; reduces material cost by limiting the number of prototypes; saves time and money by reducing risks. However, connected objects are increasingly incorporating hardware and software features. As the requirements have evolved, theSystemC / TLM simulation standard no longer meets all expectations. It includes aspects related to the simulation of systems composed of many functionality, disparate communication protocolsbut also complex and time consuming models during the simulation. Some works have already been carried out on these subjects. However, as the number of components increases, all formsof interoperability of models and tools become increasingly difficult to handle. Moreover, mostof the research has resulted in solutions that are not inter-operable and can not reuse existingmodels. To solve these problems, this thesis proposes a solution for configuring SystemC / TLMmodels. It is now part of the standard Configuration, Control and Inspection (CCI). In a secondstep, the modeling of high-level abstraction communication protocols (TLM Loosely Timed (LT)and Approximately Timed (AT)) has been studied, as it relates to non-bus protocols. An evolution of the standard to improve support, interoperability and reuse is also proposed. In a third step,a change of the SystemC standard and more precisely of the behavior of the simulation kernelhas been studied to support asynchronous events. These open the way to parallelization and distribution of models on different threads / machines. In a fourth step, a solution to integrate Central Processing Units (CPU) models integrated in Quick EMUlator (QEMU), a system emulator/ virtualizer, has been studied. Finally, all these contributions have been applied in the modeling ofa set of objects connected to a gateway
4
Hayat, Zeeshan. "Evaluating Parallelization Potential for a SystemC/TLM-based Virtual Platform." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-254883.
Full textAbstract:
System on chip (SoC) solutions, with integrated hardware and embedded software, are increasing in size and complexity. To cope with the market demand for complex SoC, the abstraction level used during development is raised to allow co-development of software (SW) and hardware (HW). Functional and bit-accurate simulators, referred to as Virtual Platforms, play a vital role in co-development of HW and SW. A virtual platform supports early development, testing, and verification of the embedded SW. However, as the complexity of SoC is increasing so does the complexity of virtual platforms, which is a major bottleneck in the performance of the virtual platforms.SystemC is an industry standard supporting development of hardware models. SystemC uses co-routine semantics, also known as co-operative multitasking, for the control of simulation. A single process is active at any time. This means that the potential for parallelism, by executing a SystemC simulation on multiple cores in a modern multi-core processor, is not utilized.This thesis work proposes a parallelization algorithm for SystemC simulations, where one SystemC thread controls a set of parallel host threads. A proof of concept trace-driven simulator is developed to verify the results from the proposed algorithm. Also, an optimized algorithm is proposed which improves the simulation speed. Furthermore, the behavior of the simulator is analyzed by looking into traces, from the Linux kernel and user application level traces, with the help of an open source tracing framework known as LTTng.The trace-driven simulator is used for evaluation of the parallelization potential for SVP, a virtual platform used at Ericsson. The evaluation makes it possible to determine, for the ideal case when the threads execute independently, the maximum possible speedup for a given test case. Using test cases from production usage, an evaluation of the possible performance improvements for SVP can be done.System på chip (SoC) -lösningar, med integrerad hårdvara och inbyggd programvara, ökar i storlek och komplexitet. För att klara av marknadens efterfrågan på komplexa SoC höjs den abstraktionsnivå som används under utveckling, för att möjliggöra samutveckling av programvara (SW) och hårdvara (HW). Funktionella och bitexakta simulatorer, benämnda virtuella plattformar, spelar en viktig roll vid samutveckling av HW och SW. En virtuell plattform stöder tidig utveckling, samt testning och verifiering av den inbäddade programvaran. Eftersom komplexiteten i SoC ökar så ökar även komplexiteten hos virtuella plattformar, vilket begränsar prestandan för de virtuella plattformarna.SystemC är en industristandard som stöder utveckling av hårdvarumodeller. SystemC använder händelse-styrd simulering. I ett give tidsögonblick är endast en process aktiv. Detta innebär att potentialen för parallelism, genom att utföra en SystemC-simulering på flera kärnor i en modern multi-core-processor, inte utnyttjas.Detta examensarbete presenterar en parallelliseringsalgoritm för SystemC-simuleringar, där en SystemC-tråd styr en uppsättning parallella värdtrådar. En data-driven simulator, som använder sig av inspelade data från en virtuell plattform, utvecklad för att verifiera resultaten från den föreslagna algoritmen. Dessutom föreslås en optimerad algoritm som förbättrar simuleringshastigheten. Dessutom analyseras beteendet hos simulatorn genom att presentera process-akiviteter, från Linuxkärnan samt från applikationen, met de hulp van een open source tracing framework bekend als LTTng.Den data-drivna simulatorn används för utvärdering av parallelliseringspotentialen för SVP, en virtuell plattform som används på Ericsson. Utvärderingen gör det möjligt att, för det ideala fallet när trådarna exekverar helt parallellt bestämma maximal möjlig hastighet för ett givet testfall. Genom att använda testfall från produktionskod kan en utvärdering av möjliga prestandaförbättringar för SVP utföras.
5
Li, Fangyan. "Simulation multi-moteurs multi-niveaux pour la validation des spécifications système et optimisation de la consommation." Thesis, Nice, 2016. http://www.theses.fr/2016NICE4008/document.
Full textAbstract:
Ce travail vise la modélisation au niveau système, en langage SystemC-AMS, et la simulation d'un émetteur-récepteur au standard Bluetooth Low Energy (BLE). L'objectif est d'analyser la relation entre les performances, en termes de BER et la consommation d'énergie du transceiver. Le temps de simulation d’un tel système, à partir de cas d’étude (use case) réaliste, est un facteur clé pour le développement d’une telle plateforme. De plus, afin d’obtenir des résultats de simulation le plus précis possible, les modèles « haut niveau » doivent être raffinés à partir de modèles plus bas niveau où de mesure. L'approche dite Meet-in-the-Middle, associée à la méthode de modélisation équivalente en Bande Base (BBE, BaseBand Equivalent), a été choisie pour atteindre les deux conditions requises, à savoir temps de simulation « faible » et précision des résultats. Une simulation globale d'un système de BLE est obtenue en intégrant le modèle de l'émetteur-récepteur dans une plateforme existante développée en SystemC-TLM. La simulation est basée sur un système de communication de deux dispositifs BLE, en utilisant différents scénarios (différents cas d'utilisation de BLE). Dans un premier temps nous avons modélisé et validé chaque bloc d’un transceiver BT. Devant le temps de simulation prohibitif, les blocs RF sont réécrits en utilisant la méthodologie BB, puis raffinés afin de prendre en compte les non-linéarités qui vont impacter le couple consommation, BER. Chaque circuit (chaque modèle) est vérifié séparément, puis une première simulation système (point à point entre un émetteur et un récepteur) est effectuéeThis work aims at system-level modelling a defined transceiver for Bluetooth Low energy (BLE) system using SystemC-AMS. The goal is to analyze the relationship between the transceiver performance and the accurate energy consumption. This requires the transceiver model contains system-level simulation speed and the low-level design block power consumption and other RF specifications. The Meet-in-the-Middle approach and the Baseband Equivalent method are chosen to achieve the two requirements above. A global simulation of a complete BLE system is achieved by integrating the transceiver model into a SystemC-TLM described BLE system model which contains the higher-than-PHY levels. The simulation is based on a two BLE devices communication system and is run with different BLE use cases. The transceiver Bit-Error-Rate and the energy estimation are obtained at the end of the simulation. First, we modelled and validated each block of a BT transceiver. In front of the prohibitive simulation time, the RF blocks are rewritten by using the BBE methodology, and then refined in order to take into account the non-linearities, which are going to impact the couple consumption, BER. Each circuit (each model) is separately verified, and then a first BLE system simulation (point-to-point between a transmitter and a receiver) has been executed. Finally, the BER is finally estimated. This platform fulfills our expectations, the simulation time is suitable and the results have been validated with the circuit measurement offered by Riviera Waves Company. Finally, two versions of the same transceiver architecture are modelled, simulated and compared
6
Belhadj, Amor Zeineb. "Validation de systèmes sur puce complexes du niveau transactionnel au niveau transfert de registres." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT083/document.
Full textAbstract:
Cette thèse se situe dans le contexte de la vérification fonctionnelle des circuits intégrés complexes. L’objectif de ce travail est de créer un flot de vérification conjoint au flot de conception basé sur une technique appelée "vérification basée sur les assertions(ABV)". Le concept de base du flot est le raffinement automatique des spécifications formelles données sous la forme d’assertions PSL du niveau TLM au niveau RTL. La principale difficulté est la disparité des deux domaines : au niveau TLM, les communications sont modélisées par des appels de fonctions atomiques. Au niveau RTL, les échanges sont assurés par des signaux binaires évoluant selon un protocole de communication précis. Sur la base d’un ensemble de règles de transformation temporelles formelles, nous avons réalisé un outil permettant d’automatiser le raffinement de ces spécifications. Comme le raffinement des modèles, le raffinement des assertions n’est pas entièrement automatisable : des informations temporelles et structurelles doivent être fournies par l’utilisateur. L’outil réalise la saisie de ces informations de façon ergonomique, puis procède automatiquement à la transformation temporelle et structurelle de l’assertion. Il permet la génération d’assertions RTL mais aussi hybrides. Les travaux antérieurs dans ce domaine sont peu nombreux et les solutions proposées imposent de fortes restrictions sur les assertions considérées. À notre connaissance, le prototype que nous avons mis en oeuvre est le premier outil qui réalise un raffinement temporel fondé sur la sémantique formelle d’un langage de spécification standard (PSL)The context of this thesis is the functional verification of complex integrated circuits.The objective of our work is to create a seamless verification flow joint to the design flowand based on a proved technique called Assertions-Based Verification (ABV). The mainchallenge of TLM to RTL refinement is the disparity of these two domains : at TLM,communications are modeled as atomic function calls handling all the exchanged data.At RTL, communications are performed by signals according to a specific communicationprotocol. The proposed temporal transformation process is based on a set of formaltransformation rules. We have developed a tool performing the automatic refinement ofPSL specifications. As for design refinement assertion refinement is not fully automated.Temporal and structural information must be provided by the user, using an ergonomicinterface. The tool allows the generation of assertions in RTL but also hybrid assertions.Little work has been done before in this area, and the proposed solutions suffer from severerestrictions. To our knowledge, our prototype is the first tool that performs a temporaltransformation of assertions based on the formal semantics of a standard specificationlanguage (PSL)
7
Flórez, Martha Johanna Sepúlveda. "Estimativa de desempenho de uma NoC a partir de seu modelo em SYSTEMC-TLM." Universidade de São Paulo, 2006. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14122006-152854/.
Full textAbstract:
The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.
8
Viaud, Emmanuel. "Modélisation SystemC d'architectures multi-processeurs intégrées sur puce au niveau transactionnel avec représentation du temps." Paris 6, 2009. http://www.theses.fr/2009PA066118.
Full textAbstract:
Cette thèse présente les principes théoriques et l'implémentation pratique d'une méthode originale de modélisation transactionnelle avec temps (Transaction Level Modeling with Time, TLM-T) de plates-formes numériques multi-processeurs complexes à mémoire partagée. S'appuyant sur le niveau d'abstraction TLM (standard de l'Open SystemC Initiative), cette méthode rend possible l'exploration architecturale et facilite le développement du logiciel embarqué, tout en considérant les phénomènes de contention dynamique ignorés par TLM qui impactent grandement les performances temporelles. La méthode présentée permet d'obtenir un gain d'un ordre de grandeur par rapport à la simulation précise au cycle tout en gardant une précision temporelle des résultats obtenus de l'ordre de 5%.
9
Karlsson, Sara. "Micro NPU for Baseband Interconnect." Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103681.
Full textAbstract:
The aim of this work is to investigate the possibility to implement a configurable NPU (Network Processing Unit) in the next generation of Ericsson’s EMCAs (Ericsson Multi Core Architecture). The NPU is constructed so that it can be configured for either Ethernet or xIO-s, as either a transmitter or a receiver. The motive for doing the work is that many protocols have similar functions and there could be possible advantages to have a configurable protocol choice in future hardware. A model of a NPU will be created in SystemC using the TLM 2.0 interface. The model will be analyzed to evaluate its complexity regarding a possible modification to also make it configurable for CPRI. The result that is presented is that it would be possible to implement a configurable NPU in the future EMCAs. The result is based on the conclusion that the protocols use many similar functions and most of the blocks could be made configurable for use with different protocols. Configurable blocks would benefit a configurable NPU as it would require fewer resources than separate blocks for each protocol.
10
Liang, Lei. "Design and Implementation of an Extendable SoC Virtual Platform in SystemC-TLM 2.0." Thesis, KTH, Elektroniksystem, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-98661.
Full textAbstract:
With the increasing design complexity for SoC development, the workload for hardware designer and verification engineer is becoming larger and larger. On the other hand, software and hardware development is unable to be carried out in parallel. This creates a bottleneck in the current design flow. Also, it will be very difficult to deal with the hardware problems which are found during the software development process. To overcome these problems, design at higher level needs to be applied. SystemC is a language which enables the design at the system level and the TLM-2.0 contains different standardized SystemC interface classes, which ensures the portability and interoperability of different IPs. In this thesis, an extendable SoC virtual platform is implemented in SystemC. It can give exactly the same functions as the design specification required. A standardized SystemC module template is designed which owns all different interfaces of the virtual platform. The template can provide lots of convenience for future module development. One method for wrapping a C/C++ into SystemC is given and a basic framework structure is implemented so that the existing C++/Simics modules can work in the designed SystemC virtual platform. Finally, the comparison on simulation time and workload between RTL modules and SystemC modules is made, which demonstrates that large development time can be saved by using this virtual platform for software development.
11
Becker, Denis. "Simulation Parallèle en SystemC/TLM de Composants Matériels décrits pour la Synthèse de Haut-Niveau." Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAM082/document.
Full textAbstract:
Les systèmes sur puce sont constitués d'une partie matérielle (un circuit intégré) et d'une partie logicielle (un programme) qui utilise les ressources matérielles de la puce. La conséquence de cela est que le logiciel d'un système sur puce est intrinsèquement lié à sa partie matérielle. Les composants matériels d'accélération sont des facteurs clés de différenciation d'un produit à l'autre.Il est nécessaire de pouvoir simuler ces systèmes très tôt lors de leur conception; bien avant que la puce ne soit physiquement disponible, et même avant que la puce ne soit complètement spécifiée. Pour cela, un modèle du système sur puce est réalisé à l'aide du langage SystemC, au niveau d'abstraction TLM (Transaction Level Modeling). La partie matérielle d'un système sur puce est constituée de composants, qui s'exécutent en parallèle. Pour autant, la simulation avec le simulateur SystemC de référence est séquentielle. Ceci permet de garantir les bonnes propriétés des simulations SystemC, en particulier la reproductibilité et le confort d'écriture des modèles.Les travaux de cette thèse portent sur la simulation parallèle de modèles SystemC/TLM. L'objectif de l'exécution parallèle est d'accélérer les simulations dans un mode d'utilisation correspondant à la phase de développement, où il est primordial de disposer de simulations qui donnent rapidement un résultat. Afin de cerner le problème de performance remarqué sur des modèles complexes à STMicroelectronics, le premier travail de cette thèse a été d'analyser le profil d'exécution d'une étude de cas représentative de la complexité actuelle des platformes SystemC/TLM. Pour cette étude, nous avons développé un outil de collecte de traces et de visualisation. Les résultats de cette analyse ont indiqué que la lenteur d'exécution en simulation était due à la complexité des composants matériels d'accélération. L'étude de l'état de l'art en simulation parallèle de modèles SystemC nous a conduit à chercher d'autres pistes que celles actuellement existantes.Pour réaliser les composants matériels plus rapidement, et permettre d'augmenter la réutilisabilité de composants d'un projet à l'autre, le flot de conception HLS (High Level Synthesis) est utilisé, notamment à STMicroelectronics. Ce flot de conception permet, à partir de la description d'une fonction en C/C++, de générer un plan de composant matériel qui va réaliser la même fonction. La description des composants est découpée en sous-fonctions, individuellement plus simples. Afin d'obtenir de bonnes performances, les sous-fonctions sont assemblées en chaîne, à travers laquelle circulent les données à traiter. Il est indispensable de pouvoir réutiliser le code écrit pour la HLS dans les simulations SystemC/TLM@: cette situation deviendra de plus en plus fréquente, et il n'a pas assez de temps pour réécrire ces modèles dans ces projets courts.Nous avons développé une infrastructure de simulation parallèle permettant d'intégrer et de simuler efficacement des composants de traitement de données écrits pour la HLS. L'application de cette infrastructure à un exemple a permis d'accélérer l'exécution de la simulation d'un facteur 1.6 avec 4 processeurs. Au-delà de ce résultat, les conclusions principales de cette thèse sont que la simulation parallèle de modèles à haut niveau d'abstraction, en SystemC/TLM, passe par la combinaison de plusieurs techniques de parallélisation. Il est également important d'identifier les parties parallélisables dans des simulations industrielles, notamment pour les nouveaux défis que sont les simulations multi-physiques et l'internet des objetsSystems on chip consists in a hardware part (an integrated circuit) and a software part (a program) that uses the hardware resources of the chip. Consequently, the embedded software is intrinsically connected to the chip hardware. Hardware acceleration components are key differentiation factors from one product to another.It is necessary to simulate systems on chip very early in the design flow; before the chip is physically available and even before its full specification. For such simulations, developers write a model of the system on chip in SystemC, at the TLM (Transaction Level Modeling) abstraction level. The hardware part of a chip consists in components that behave in parallel with each other. However, the reference SystemC simulator execute simulations sequentially. The sequential execution enables to keep good properties of SystemC simulations, namely reproducibility and ease of model writing.This thesis work address the parallel execution of SystemC/TLM simulations. The goal of parallel simulation is to speed up simulations, in the context of the model development, where it is important to quickly get results. In order to identify the performance problem of complex models at STMicroelectronics, the first step of this thesis was to analyse the execution profile of a case study, representative of the complexity of current platforms. For this study, we developed a trace recording and visualization tool. The results of this study indicated that the performance critical parts of the simulation are hardware acceleration components. Studying existing parallel simulation approaches led us to look for other parallel simulation techniques.To speed up the development of hardware acceleration components, and increase the reusability from one project to another, the HLS (High Level Synthesis) design flow is used, notably at STMicroelectronics. This design flow enables to generate a logically synthesizable model of a component, from a high level behavioral description in C/C++. This design flow also constraints the development: it is split in sub-functions, assembled in a pipeline. The code written for HLS must be re-used in SystemC/TLM models: this situation will become more and more frequent and there is no time to rewrite the models of such components within short delays.We developed a parallel simulation infrastructure enabling the integration and efficient simulation of hardware components written for HLS.We applied this infrastructure to an example platform, which resulted in speeding up the simulation. Beyond this result, one of the main conclusion of this thesis is that parallel simulation of abstract SystemC/TLM models will require to combine multiple parallelization techniques. Future research work can identify other types of potential parallelism in industrial models. This will become critical with the new challenges of simulation, as multi-physical simulations and internet of things
12
Funchal, Giovanni. "Contributions to the Transaction-Level Modeling of Systems-on-a-Chip." Thesis, Grenoble, 2011. http://www.theses.fr/2011GRENM061.
Full textAbstract:
Cette thèse porte sur la modélisation des systèmes-sur-puce au niveau transactionnel, une approche connue sous le nom de prototypage virtuel. Les prototypes virtuels sont d'un grand intérêt industriel parce qu'ils permettent de démarrer certaines activités (telles que le développement du logiciel embarqué) plus tôt dans le flot de conception. Du fait que cette approche est relativement nouvelle, un grand nombre de problèmes de modélisation sont encore ouverts. En particulier, il est essentiel de comprendre à quel point un modèle donné est proche du système hypothétique qu'il est sensé représenter. C'est un problème difficile car nous n'avons pas les moyens de réaliser une comparaison objective, vu que le système modélisé n'est pas disponible physiquement au moment de la modélisation. Nous avons besoin d'une méthodologie pour traiter ces difficultés, qui s'étendent au-delà de simples exigences objectives et de l'analyse de besoin fonctionnel. Dans ce contexte, l'industrie cherche des directives de modélisation claires, fondées sur l'expérience et l'identification des pratiques actuelles et des problèmes récurrents. Dans cette thèse, nous présentons une étude compréhensive d'un large éventail de considérations techniques impliquées dans le flot de conception du logiciel et du matériel qui constituent un système-sur-puce typique. Nous utilisons ces connaissances pour identifier une source particulière de divergence entre le modèle et le système modélisé. Nous montrons que cette divergence masque certains bogues du logiciel sur le prototype virtuel. Nous mettons en évidence la pratique de modélisation à l'origine de cette situation. Deuxièmement, nous essayons d'identifier des problèmes liés à l'utilisation du langage de modélisation dans les pratiques actuelles. Nous prétendons que, d'une part, ces problèmes sont dûs à la confusion entre les concepts de la modélisation transactionnelle et leur implémentation dans le langage standard de l'industrie ; et d'autre part que ce n'est qu'en menant des comparaisons avec un autre langage que l'on pourrait quantifier leur étendue. Pour ce faire, nous proposons un cadre d'application spécialement conçu pour guider l'étude des concepts fondamentaux de la modélisation transactionnelle. Entre autres, nous introduisons une nouvelle méthode pour la modélisation du temps dans les simulateurs à événements discrets. Cette méthode dévoile la différence entre une action instantanée et une tâche avec durée. Ensuite, elle l'exploite de plusieurs manières : pour enrichir les outils de visualisation de traces ; pour dériver une définition claire de chevauchement de tâches ; pour accélérer la simulation à moindre effort, en parallélisant l'exécution d'actions se déroulant à des temps simulés différents ; et pour révéler des bogues subtiles en tenant compte du fait que les actions à des temps simulés différents ne sont pas forcément synchroniséesThis thesis deals with modeling of Systems-on-a-Chip (SoC) at the Transactional Level (TLM), an approach also known as virtual prototyping. Virtual prototypes are of special industrial interest because they allow some activities (such as embedded software development) to start earlier in the design flow. Because this approach is relatively new, several modeling issues are still open. In particular, there is an increasing need for understanding how close a given model is to the hypothetical system it is intended to represent. This is a difficult problem specially because we lack a way to perform an objective comparison, since the modeling activity is prior to the physical existence of the modeled system. A methodology is required to address these concerns, going beyond classical objective and functional quality requirements. In this context, the industry searches for clear modeling guidelines based on experience and the identification of the current modeling practices and known recurring problems. In this thesis, we present a comprehensive study of a range of technical considerations involved in the design flow of the hardware and software that constitutes a typical SoC. We use this knowledge to identify one particular source of divergence between the model and the modeled system. We show that this divergence causes some software bugs to become hidden in the virtual prototype and we correlate this situation to the corresponding modeling practice. Secondly, we attempt to identify language-dependency issues in the modeling practices. We claim that it is only by confronting with an alternative language that we could measure the extent to which common modeling issues were caused by mixing up conceptual transaction-level modeling with its implementation in the current industry standard language. Therefore, we propose a complete experimentation framework specifically designed to help in the study of fundamental concepts beneath TLM. Amongst other features, this framework introduces a novel approach to modeling time in discrete-event simulators that distinguishes between instantaneous actions and tasks that take time. We show that this notion can be exploited to enrich trace visualization tools; to derive a clear definition of overlapping tasks; to effortlessly achieve an important simulation speedup by enabling parallel execution of actions occurring at different simulation times; and to expose subtle bugs by removing the constraint that actions at different simulation times are necessarily synchronized
13
Michl, Kamil. "Paměťový subsystém v SystemC." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2020. http://www.nusl.cz/ntk/nusl-417235.
Full textAbstract:
This thesis deals with the design and implementation of a processor simulation memory subsystem. The memory subsystem is designed using the Transaction Level Modeling approach. The implementation is done in C++ language utilizing the SystemC library. The processor simulation is adopted from the Codasip company simulator. The objective is to create a functional connection between the processor and the memory inside the simulator. This connection supports communication protocols of AHB3-lite, AXI4-lite, CPB, and CPB-lite buses. The new implementation of the aforementioned connection and the memory is integrated into the original simulator. The resulting simulator is tested using unit tests.
14
Sotiropoulos, Pesiridis Konstantinos. "Parallel Simulation of SystemC Loosely-Timed Transaction Level Models." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-227806.
Full textAbstract:
Parallelizing the development cycles of hardware and software is becoming the industry’s norm for reducing time to market for electronic devices. In the absence of hardware, software development is based on a virtual platform; a fully functional software model of a system under development, able to execute unmodified code. A Transaction Level Model, expressed with the SystemC TLM 2.0 language, is one of the many possible ways for constructing a virtual platform. Under SystemC’s simulation engine, hardware and software is being co-simulated. However, the sequential nature of the reference implementation of the SystemC’s simulation kernel, is a limiting factor. Poor simulation performance often constrains the scope and depth of the design decisions that can be evaluated. It is the main objective of this thesis’ project to demonstrate the feasibility of parallelizing the co-simulation of hardware and software using Transaction Level Models, outside SystemC’s reference simulation environment. The major obstacle identified is the preservation of causal relations between simulation events. The solution is obtained by using the process synchronization mechanism known as the Chandy/Misra/Bryantt algorithm. To demonstrate our approach and evaluate under which conditions a speedup can be achieved, we use the model of a cache-coherent, symmetric multiprocessor executing a synthetic application. Two versions of the model are used for the comparison; the parallel version, based on the Message Passing Interface 3.0, which incorporates the synchronization algorithm and an equivalent sequential model based on SystemC TLM 2.0. Our results indicate that by adjusting the parameters of the synthetic application, a certain threshold is reached, above which a significant speedup against the sequential SystemC simulation is observed. Although performed manually, the transformation of a SystemC TLM 2.0 model into a parallel MPI application is deemed feasible.
15
Huck, Emmanuel. "Simulation de haut niveau de systèmes d'exploitations distribués pour l'exploration matérielle et logicielle d'architectures multi-noeuds hétérogènes." Phd thesis, Université de Cergy Pontoise, 2011. http://tel.archives-ouvertes.fr/tel-00781961.
Full textAbstract:
Concevoir un système embarqué implique de trouver un compromis algorithme/architecture en fonction des contraintes temps-réel. Thèse : pour concevoir un MPSoC et plus particulièrement avec les circuits reconfigurables modifiant le support d'exécution en cours de fonctionnement, la nécessaire validation des comportements fluctuants d'un système réactif impose une évaluation préalable que l'on peut réaliser par simulation (de haut niveau) tout en permettant l'exploration de l'espace de conception architectural, matériel mais aussi logiciel, au plus tôt dans le flot de conception. Le point de vue du gestionnaire de la plateforme est adopté pour explorer à haut niveau les réactions du système aux choix de partitionnement impactés par l'algorithmique des services du système d'exploitation et leurs implémentations possibles. Pour cela un modèle modulaire de services d'OS simule fonctionnellement et conjointement en SystemC le matériel, les tâches logicielles et le système d'exploitation, répartis sur plusieurs noeuds d'exécution hétérogènes communicants. Ce modèle a permis d'évaluer l'architecture temps-réel idéale d'une application dynamique de vision robotique conjointement à l'exploration des services de gestion d'une zone reconfigurable modélisée. Ce modèle d'OS a aussi été intégré dans un simulateur de MPSoC hétérogène d'une puissance estimé à un Tera opérations par seconde.
16
Pečkys, Vaidotas. "Sparčiosios magistralės aukšto abstrakcijos lygio modelio sudarymas ir analizė." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2005. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2005~D_20050526_192727-86987.
Full textAbstract:
In this work was studying literature related to object orientated programming tools for hardware design, capabilities for modeling and synthesis of high-level models of abstraction. It was founded-out the operating principles of high-speed bus and created prototype of such bus in TLM level. It was created methodology for transformation of high-speed bus prototype to RTL level. This methodology was used for transformation of high-speed bus prototype to RTL level. Transformed module was synthesized to gate level. Simulation speed of high-speed bus model in TLM was compared with simulation speed of model in behavioral level. It was demonstrated universality and reuse capabilities of TLM models.
17
Moy, Matthieu. "Techniques et outils pour la vérification de Systèmes-sur-Puce au niveau transaction." Phd thesis, Grenoble INPG, 2005. http://tel.archives-ouvertes.fr/tel-00311033.
Full textAbstract:
Les travaux présentés dans ce document portent sur la vérificationde modèles de systèmes sur puce, au niveau transactionnel (TLM).
Nous présentons le niveau transactionnel et ses variantes, et
rappelons en quoi ce nouveau niveau d'abstraction est aujourd'hui
nécessaire en plus du niveau de transfert de registre (RTL) pour
répondre aux contraintes de productivités et de qualités de plus en
plus fortes, et comment il s'intègre dans le flot de conception.
Nous présentons un nouvel outil, LusSy, permettant la vérification
formelle de modèles transactionnels écrits en SystemC. Sa structure
interne s'apparente à celle d'un compilateur: Une partie frontale,
Pinapa, qui lit le programme source, une extraction de la
sémantique, Bise, dans notre formalisme intermédiaire \hpiom, une
série d'optimisations dans le composant Birth, et des générateurs
de code pour les outils de preuves pour Lustre et SMV.
Lussy est conçu et écrit de manière à avoir aussi peu de limitation
que possible sur la forme du code SystemC accepté en entrée. \pinapa
utilise une approche innovante qui lui permet de s'affranchir de la
plupart des limitations dont souffrent les outils similaires.
L'extraction de la sémantique implémente plusieurs constructions TLM
qu'aucun autre outil disponible aujourd'hui ne gère. Il ne demande
pas d'annotation manuelle du code source, toute la chaîne étant
entièrement automatisée.
Lussy est capable de prouver formellement des propriétés sur des
modèles de petites taille, et ses composants sont réutilisables pour
des outils de preuve compositionnelle, ou d'analyse de code autre
que le model-checking qui passeront mieux à l'échelle que l'approche
actuelle.
Nous présentons les principes de chaque étape de la transformation,
ainsi que notre implémentation. Les résultats sont donnés pour des
exemples simples et petits, et pour une étude de cas de taille
moyenne, EASY. Les expérimentations avec Lussy nous ont permis de
comparer les différents outils de preuves que nous avons utilisés,
et d'évaluer l'efficacité des optimisations que nous avons
implémentées.
18
Cenni, Fabio. "Modélisation à haut niveau de systèmes hétérogènes, interfaçage analogique /numérique." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00721972.
Full textAbstract:
L'objet de la thèse est la modélisation de systèmes hétérogènes intégrant différents domaines de la physique et à signaux mixtes, numériques et analogiques (AMS). Une étude approfondie de différentes techniques d'extraction et de calibration de modèles comportementaux de composants analogiques à différents niveaux d'abstraction et de précision est présentée. Cette étude a mis en lumière trois approches principales qui ont été validées par la modélisation de plusieurs applications issues de divers domaines: un amplificateur faible bruit (LNA), un capteur chimique basé sur des ondes acoustiques de surface (SAW), le développement à plusieurs niveaux d'abstraction d'un capteur CMOS vidéo, et son intégration dans une plateforme industrielle. Les outils développés sont basés sur les extensions AMS du standard IEEE 1666 SystemC mais les techniques proposées sont facilement transposables à d'autres langages tels que VHDL-AMS ou Verilog-AMS utilisés en conception de dispositifs mixtes.
19
Chen, Dian. "Transmission line modelling (TLM) of physical systems." Thesis, University of Sheffield, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.361632.
Full text
20
Chughtai, Farooq Khalid. "Accurate Performance Exploration of System-on-Chip using TLM." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-92231.
Full textAbstract:
Increased complexity of system-on-chips (SoC) makes performance exploration with register transfer level (RTL) models to be both time consuming and to appear too late in the design cycle. Instead of RTL, transaction level models (TLM) have emerged as a dominant candidate for modeling of these complex SoCs. Transaction level models are abstracting implementation details and are therefore less complex to implement and execute much faster than RTL. However, an open issue is to define and measure how accurate TLM models are as compared to RTL. In this thesis, accuracy of a TLM model is defined and quantified by introducing metrics that are used to compare RTL and TLM models. The metrics introduced are transaction time, start time, relative throughput and transaction reordering. From the metrics, an error between RTL and TLM is calculated and presented. The thesis discusses how to generate proper stimuli for models, collect the metric, and how to calculate and represent the error to the designer. The proposed methodology for accuracy measurement is using TLM2 definitions and may therefore be applied to any TLM model. This methodology is applied to experiment a multi-port memory that is modeled as an approximately timed TLM. Defined metrics are collected from the same scenarios applied to both RTL and TLM models. Accuracy measurements at system and sub-system level can be integrated with the verification environment to systematically develop and refine accurate TLM models for performance exploration
21
Burton, James D. "Parallel simulation of hydraulic systems using transmission-line modelling (TLM)." Thesis, University of Bath, 1994. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.387215.
Full text
22
Runåker, Björn. "Distributed system simulation with host-based target offloading." Thesis, KTH, Skolan för datavetenskap och kommunikation (CSC), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-165177.
Full textAbstract:
Scaling of TLM (Transaction Level Modeling) simulations for performance is difficult. In this project I will go through several causes of poor performance. This paper describes several simulation engines that use SystemC that are connected so they together simulate next generation radio base station. It also describes how to build a virtual network in, for security reasons, constrained environment where both virtual and physical equipment can connect the simulated target. Furthermore, it describes how to use the virtual network to improve the overall performance of the simulation. It is shown how the virtual network is used to distribute the simulation and offloading the simulated target to accomplish the performance goal.Det är svårt att skala upp en simulering baserad på TLM (Transaction Level Modeling). I detta projekt kommer jag att gå igenom flera orsaker till dålig prestanda. Denna rapport beskriver flera olika simuleringsmotorer som använder SystemC och som är kopplade så att de tillsammans simulerar nästa generation radiobasstationer. Här beskrivs också hur man bygger ett virtuellt nätverk som hanterar begränsningar som finns av säkerhetsskäl, och trots detta kan koppla ihop virtuell och fysisk utrustning till det simulerade målsystemet. Dessutom anges hur detta virtuella nät används för att förbättra den övergripande prestandan i simuleringen. Detta görs genom att utnyttja det virtuella nätet för att distribuera simuleringen och avlasta målsystemet.
23
Jonutis, Vytautas, and Mindaugas Jaraminas. "Vaizdų atpažinimo sistemos projektavimas ir tyrimas." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2008. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2008~D_20080811_151809-23043.
Full textAbstract:
Darbe analizuojamas vaizdo apdorojimo sistemos modelis, kuris yra modeliuojamas. Pradinė modelio specifikacija yra aprašoma funkciniame lygyje. Modelio architektūrai modeliuoti mes naudojame transakcijų lygio SystemC, naudodamiesi ja mes galime greitai ir patogiai nustatyti, kokia turėtų būti modeliuojamos sistemos architektūra. Funkcinis modelis yra transformuojamas į sisteminį lygį naudojantis SystemC transakcijų modeliavimo kalba. Naudojantis pradine specifikacija ir TLM modeliu pereiname prie sintezuojamo aprašo. Transformuodami pradinį modelį aukštame abstrakcijos lygyje, mes sprendžiame sistemos architektūros problemą. Transformuodami aukšto lygio modelį į SystemC sintezuojamą aprašą, mes sprendžiame kintamųjų ir algoritmų transformavimo problemas.In this work we analyzing video preprocessing system model. Primary model specifications are described in functional level. It is hard to decide what system architecture should be, so we used SystemC TLM modeling language, because it gives us easier way to change system architecture Using SystemC transaction level modeling (TLM) the functional primary specification are transformed from functional model to system level. To get synthesizable model we use primary specification and TLM model. We solve many system architecture problems while we where working on primary model transformation to high abstraction system. Transforming high abstraction level model to SystemC synthesizable code we solve variables selection problems and algorithms conversation problem.
24
Koay, Adeline Lay Kuen. "Transmission line matrix (TLM) based thermal management and control of spatially distributed systems." Thesis, University of Hull, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.417159.
Full text
25
Kumar, Rethinagiri Santhosh. "Une approche système pour l'estimation de la consommation de puissance des plateformes MPSoC." Phd thesis, Université de Valenciennes et du Hainaut-Cambresis, 2013. http://tel.archives-ouvertes.fr/tel-00921894.
Full textAbstract:
Avec l'essor des nouvelles technologies d'intégration sur silicium submicroniques, la consommation de puissance dans les systèmes sur puce multiprocesseur (MPSoC) est devenue un facteur primordial au niveau du flot de conception. La prise en considération de ce facteur clé dés les premières phases de conception, joue un rôle primordial puisqu'elle permet d'augmenter la fiabilité des composants et de réduire le temps d'arrivée sur le marché du produit final. Dans cette thèse, nous proposons une méthodologie efficace pour l'estimation de la consommation de puissance des plateformes MPSoC. Cette méthodologie repose sur une combinaison d'une analyse fonctionnelle de la puissance (FLPA) pour l'obtention des modèles de consommation et d'une technique de simulation au niveau transactionnel (TLM) pour calculer la puissance de l'ensemble du système. Fondamentalement, FLPA est proposée pour modéliser le comportement des processeurs en terme de consommation afin d'obtenir des modèles paramétrés de haut niveau. Dans ce travail, FLPA est étendue pour mettre en place des modèles de puissance génériques pour les différentes parties du système (mémoire, logique reconfigurable, etc.). En outre, un environnement de simulation a été développé au niveau transactionnel afin d'évaluer avec précision les activités utilisées dans les modèles de consommation. La combinaison de ces deux parties conduit à une estimation de la puissance hybride qui donne un meilleur compromis entre la précision et la vitesse. La méthodologie proposée a plusieurs avantages: elle estime la consommation du système embarqué dans tous ses éléments et conduit à des estimations précises sans matériel coûteux et complexe. La méthodologie proposée est évolutive pour explorer des architectures complexes embarquées. Notre outil d'estimation de puissance au niveau du système PETS (Power Estimation Tool at System-level) est développé sur la base de la méthodologie proposée. L'efficacité de notre outil PETS en termes de précision et rapidité est validée par des architectures embarquées monoprocesseur et multiprocesseur conçues autour des plateformes OMAP (3530 et 5912) et FPGA Pro Xilinx Virtex II.
26
Sinclair-Williams, M. J. M. "Disability and safety management systems in TQM and non-TQM organisations." Thesis, University of Surrey, 1998. http://epubs.surrey.ac.uk/844353/.
Full textAbstract:
Historically society has, at various periods in time, protected the health, safety and welfare of those most disadvantaged by using socially based collective mechanisms. Within the United Kingdom the model used to achieve this collective protection has developed from proscription, under the Factories Acts, to a more self-regulatory and risk based approach advocated by Lord Roben's under the Health and Safety at Work etc. Act 1974 and its relevant statutory provisions. The body tasked with providing examples of good practice and regulating the provisions of the Act, The Health and Safety Executive, advocate a management-led model using the principles of total quality management (TQM). This model is one which purports to focus on a systematic and empowered approach by involving all staff in the evaluation and reduction of systematic error within processes throughout the whole organisation. It can be argued that the contemporary disadvantaged are no longer the children of the industrial revolution but are those members of society who seek employment yet are handicapped by society through disability or impairment- the paradigm of disability. This study sought to explore this paradigm of disability and TQM within the context of two contrasting industrial sectors - the engineering and retail sectors. The study sought to break new ground by exploring whether the TQM model, which advocates system totality, reduction in variation and continuous improvement as fundamental principles, does in fact provide improved cognitive adequacy (a construct of institutional responsibility, communication and problem resolution) within the paradigm of disability. The study used a triangulation methodology to collect qualitative data at the individual and institutional level. This involved a number of phases comprising group discussions, focus groups and self-completed questionnaires (n=1135) by economically active disabled, impaired and handicapped individuals and at the organisational level case study analysis (n=8) and self-completed questionnaires (n=2181) by institutional key players. Although the construct of disability is multifaceted, the study concluded that at the individual level a number of factors were perceived to be ranked higher and as such more important to disabled employees in maintaining their health, safety and welfare. These were further classified into 'software' and 'hardware' domains of a safety management system with institutional social support being most important. Social support comprised support, communication and trust and was perceived to be low at the organisational level. At the institutional or organisational level social support can be measured using the theory of cognitive adequacy comprising responsibility, communication and problem resolution. When measured at the organisational level, via the policy domain, cognitive adequacy was once more concluded to be low or absent. These results applied equally to individuals within both the retail and engineering sectors. The study also concluded that, at the organisational level, safety systems which can be categorised as formal did not exist to meet the needs of the disabled within the organisations studied. This was particularly evident at the policy domain level where it was noted that few companies had included provisions for the allocation of specifically defined responsibility and control. However there existed many informal sub-systems which had developed through group dynamics and personal interrelations. In many cases those tasked with operational responsibility were unaware of such sub-systems. There also existed many barriers within the disability paradigm to both the duty holder and disabled employees meeting specific duties under the Health and Safety at Work etc. Act 1974. In particular communication, both verbal and non-verbal, presented the highest ranked barrier to organisations achieving a high cognitive adequacy condition. Each construct was measured using contingency tables and log-linear analysis to determine any association between TQM and non-TQM organisations for the paradigm of disability. Significant differences in data acquisition, performance measurement and problem resolution existed between TQM and Non-TQM organisations. However in relation to the paradigm of disability, the study concluded that the data supported the null hypothesis that, in the context of the paradigm of disability, no significant differences were exhibited between the safety management systems (SMS) of organisations who had adopted TQM and those that had not. Holistically this study has provided a deeper understanding of the complexity of the disabled paradigm and safety provisions at work.
27
Schellkopf, Leonard. "Investigation of Polymer Systems in Solutions with Electron Microscopy and Scattering Methods." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-167948.
Full textAbstract:
This work is focused on the visualization and thus in the aid in finding explanations for the behavior of polymer structures as they exist in solution. For this aim, preparation and imaging techniques based on cryo-TEM protocols were developed for a large variety of polymeric specimens using new commercially available devices and the results were compared with the findings of other means of structural investigations. The systems used in this work were chosen, as their investigations can be adapted to other polymer systems by slight adaptation of the preparation procedures.
28
Barber, Kristin M. "Improving Bug Visibility using System-Level Assertions and Transactions." University of Cincinnati / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1377875020.
Full text
29
Morais, Tiago Gualberto. "Lembrança de Nhô Tim." Universidade de São Paulo, 2018. http://www.teses.usp.br/teses/disponiveis/27/27159/tde-05122018-094222/.
Full textAbstract:
Este trabalho investiga as relações entre a exploração da terra realizada pela prática da mineração e estratégias de produção de memória a partir da proposta de um diálogo artístico na comunidade do bairro Resplendor, na cidade de Igarapé-MG. Esta região de recente urbanização destaca-se, especialmente, pelas transformações da paisagem em decorrência da proximidade com grandes empreendimentos: o centro de arte contemporânea Inhotim; a economia mineradora; a instalação de presídios (Bicas I e II) e a construção de conjuntos habitacionais populares. Partindo de uma série de intervenções nesta localidade realizada em 11 de setembro de 2016, a qual possui no objeto Lembrança de Nhô Tim seu eixo central, propus a elaboração desta publicação impressa de caráter ficcional reunindo registros audiovisuais, documentos, imagens de trabalhos artísticos e depoimentos desta experiência e seus desdobramentos ao longo deste curso de mestrado. Aspira-se ampliar as compreensões artísticas contemporâneas envoltas em práticas capazes de aglutinar aspectos envolvidos com o sistema da arte, o convívio comunitário e com a invenção de memórias.This work studies the connections between the exploitation of land carried out by the practice of mining and strategies of memory production made from the proposal of an artistic dialogue in the community of Resplendor, in the city of Igarapé- -MG. This region of recent urbanization stands out, especially, considering the transformations of the landscape due to the presence of large enterprises: the Center of Contemporary Art Inhotim; mining economy; installation of the prisons (Bicas I and II) and the establishment of popular housing. Starting from a series of interventions in this location, realized on September 11th 2016, which has the object Souvenir of Nhô Tim as it\'s central axis, I proposed the elaboration of this printed publication which has a fictional character and gathers audiovisual records, documentation, images of art works and testimonies of this experience and its unfolding during the course of this Masters degree program. The aim is to broaden the contemporary art comprehension wrapped in practices capable of agglutinating aspects involved in art systems, community living and with the invention of memories.
30
Wichmann, Tim [Verfasser]. "Symbolische Reduktionsverfahren für nichtlineare DAE-Systeme / Tim Wichmann." Aachen : Shaker, 2004. http://d-nb.info/1172612706/34.
Full text
31
Li, Tientien. "An Object-Oriented Telemetry Format Management (TFM) System." International Foundation for Telemetering, 1990. http://hdl.handle.net/10150/613427.
Full textAbstract:
International Telemetering Conference Proceedings / October 29-November 02, 1990 / Riviera Hotel and Convention Center, Las Vegas, NevadaThe telemetry format is a key piece of information utilized by both the flight segment and the ground segment of a mission. During the evolution of a mission, the telemetry format is usually going through many changes and refinements. Sometimes, a format may even evolve from mission to mission. The conventional Relational Data Base Management Systems (RDBMS) do not work well with telemetry formats because of the multidimensional nature of most telemetry formats. To reduce the complexity of managing dynamic telemetry formats, an innovative Telemetry Format Management (TFM) system has been designed. The TFM system utilizes new object-oriented concepts in managing the creation, the evolution, and the utilization of telemetry formats. It supports common telemetry formats including: Time-Division Multiplexed (TDM) telemetry formats and packet telemetry formats. By using the TFM system, one can greatly simplify most tasks associated with the development of telemetry formats. This paper describes the architecture, design concepts, and operational philosophy of the TFM system.
32
Mendes, João Reis Costa. "Real time mobile system for support in firefighting environments." Master's thesis, FCT _ UNL, 2009. http://hdl.handle.net/10362/2719.
Full textAbstract:
Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresThis dissertation addresses work being performed within the context of the Fire Forest Finder system, fulfilling the requests for a multi-information application intended for a vehicle mounted mobile device. The main objective of this dissertation is to provide a solution running on a PDA device that provides support in Fire Fighting environments. The user has access to: multi-information data of the theater of operations, an automotive navigation system (TomTom Navigator™) and a text messaging capability. The hardware present on this system is a DLoG X7™ industrial graded PDA that possesses the right sturdiness for this task. The software developed consists of three distinct interfaces: an appropriately customized TomTom Navigator™ interface for the end-users of this system and two additional applications were created to allow a proper visualization of the available information and also have an interface with text messaging input/output capabilities; It is important to refer that the GSM protocol, text messaging service in particular was the chosen communication mean due to the fact that this network has, at the time this dissertation was finished, the better and most reliable coverage of remote areas, such as the forests for which this system is intended to. In terms of experimental validation a series of performance, intuitiveness and usability tests were performed and analyzed in detail with the purpose of demonstrating the validity of the ideas presented. The thesis is completed by the depiction of the achieved results with the subsequent discussion and identification of open points as a result of the work done.
33
Vidgen, Richard. "A multiple perspective approach to information system quality." Thesis, University of Salford, 1996. http://usir.salford.ac.uk/14779/.
Full textAbstract:
The motivation for this research is a concern with the high rate of information system failures reported in the academic literature and in practitioner publications. It is proposed that the adoption of the customer-centred ideals and methods of quality management in information system development will increase the likelihood of the delivery of successful information systems. The approach taken in the research is to work with the ideas of multiple perspectives - organizational effectiveness, work-life quality, and technical artefact quality - and multiple stakeholders. The research approach is to use action research. The fieldwork comprises three phases. The first phase involved interviewing system developers and the second phase consisted of two case studies of implemented information systems. This preliminary analysis, together with a theoretical investigation of the foundations of quality, was used to inform the development of a quality approach to information system development. The information system development methodology (ISDM) is based upon Multiview, a multiple perspective approach to information system development, and the total quality management method used is quality function deployment. The resultant hybrid methodology is known as ISDM/Q. The ISDM/Q is tested using action research on a live system development project concerned with the development of a wind tunnel control and data collection system. Extensive organizational analysis was conducted to place this software development within a wider organizational context, involving quality requirements workshops and quality planning. The outcomes of the research are assessed in terms of the learning recorded with respect to the framework of ideas, the methodology (ISDM/Q) and the domain in which the action research took place. The field work showed that there were benefits to using a quality metaphor in information system development but that this would require a significant change in the culture and style of information system development organizations. A practical contribution of the research is the development of quality function deployment for information system development.
34
Hodder, Carl Alexander. "Quality management system development." Thesis, University of Canterbury. Engineering Management, 2013. http://hdl.handle.net/10092/7443.
Full textAbstract:
With Chiptech’s current growth rate and size it has become necessary to develop a Quality Management System to enable repeatability, meet customer demands, and protect Chiptech from staff turnover. ISO 9001 was identified as a base for development, with the imperative that the system identified and developed must deliver value for Chiptech. Several frameworks were investigated, along with journal articles and discussions with industry members in order to determine the aspects that would deliver value, and determine the key success factors. Two factors were identified as critical: employee involvement, and the utilisation of metrics – both of which were leveraged for the project results and recommendations.
The systems developed have already proved they offer benefits, however, in order to maintain performance Chiptech must a) keep evaluating the measured results, b) ensure that quality forms an integral part of the organisational culture and, c) continue the systematic approach of continual improvement.
35
Li, Jiatong. "TLS Library for Isolated Enclaves : Optimizing the performance of TLS libraries for SGX." Thesis, KTH, Kommunikationssystem, CoS, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-241245.
Full textAbstract:
Nowadays cloud computing systems handle large amounts of data and process this data across different systems. It is essential to considering data security vulnerabilities and data protection. One means of decreasing security vulnerabilities is to partition the code into distinct modules and then isolate the execution of the code together with its data. Intel’s Software Guard Extension (SGX) provides security critical code isolation in an enclave. By isolating the code’s execution from an untrusted zone (an unprotected user platform), code integrity and confidentiality are ensured. Transport Layer Security (TLS) is responsible for providing integrity and confidentiality for communication between two entities. Several TLS libraries support cryptographic functions both for an untrusted zone and an enclave. Different TLS libraries have different performance when used with Intel’s SGX. It is desirable to use the best performance TLS library for specific cryptographic functions. This thesis describes a performance evaluation several popular TLS libraries performance on Intel SGX. Using the evaluation results and combining several different TLS libraries together, the thesis proposes a new solution to improve the performance of TLS libraries on Intel SGX. The performance is best when invoking the best specific TLS library based upon the data size – as there is a crossover in performance between the two best libraries. This solution also maintains the versatility of the existing cryptographic functions.Numera hanterar molnberäkningssystem stora mängder data och bearbetar dessa data över olika system. Det är viktigt att ta itu med datasäkerhetsproblem och dataskydd. Ett sätt att minska säkerhetsproblem är att partitionera koden i olika moduler och sedan isolera kodens exekvering tillsammans med dess data. Intel’s Software Guard Extension (SGX) tillhandahåller säkerhetskritisk kodisolering i en enklav. Genom att isolera kodens körning från en otillförlitlig zon (en oskyddad användarplattform) säkerställs kodintegritet och sekretess. Transport Layer Security (TLS) ansvarar för att ge integritet och konfidentialitet för kommunikation mellan två enheter. Flera TLS-bibliotek stödjer kryptografiska funktioner både för en osäker zon och en enklav. Olika TLS-bibliotek har olika prestanda när de används med Intel’s SGX. Det är önskvärt att använda TLS-bibliotekets bästa prestanda för specifika kryptografiska funktioner. Denna avhandling beskriver en prestationsutvärdering av flera populära TLS-bibliotekens prestanda på Intel SGX. Genom att använda utvärderingsresultaten och kombinera flera olika TLS-bibliotek tillsammans, presenterar avhandlingen en ny design och lösning för att förbättra prestanda för TLS-bibliotek på Intel SGX. Den resulterande prestanda åberopar TLS-bibliotekets bästa prestanda inom en viss datastorlek samtidigt som krypteringsfunktionerna är mångsidiga.
36
Chengliang, Li, and Zhang Qishan. "THE DEVELOPMENT OF TELEMETRY SYSTEM IN CHINA." International Foundation for Telemetering, 1993. http://hdl.handle.net/10150/608845.
Full textAbstract:
International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, NevadaTelemetry as a research interest began to appear in the early days of this century. Since then it has gained great progress with its application fields growing all the time. This paper reviews briefly the history of telemetry introduces its state-of-the-art technology. The research activities and technological levels in this field inside China are included.
37
Veneri, Valentina. "Riorganizzazione di un distribution center mediante le tecniche di lean production: il caso Gambro Dasco spa." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2013. http://amslaurea.unibo.it/6382/.
Full textAbstract:
La Lean Production è un tema di estrema attualità per tutte le aziende che abbiano compreso l’importanza di produrre di più, con le risorse che si hanno a disposizione, eliminando sistematicamente tutte le attività che non creano valore aggiunto.
La Produzione Snella è diventato un metodo per incrementare la competitività, riducendo l’incertezza e aumentando il servizio fornito al cliente.
Nella realtà attuale vi è ancora una scarsa diffusione dei concetti Lean. Le cause di questo problema sono imputabili soprattutto alla cultura del management aziendale, alla mancanza di efficaci strumenti tecnologici a supporto, e in alcuni casi, la scarsa disponibilità delle imprese ad abbracciare la filosofica “snella”.
La presente tesi, dopo una panoramica introduttiva su l’origine e l’evoluzione del Pensiero Snello e l’analisi di tutti i tools disponibili per combattere lo spreco; si propone di analizzare l’applicazione degli stessi in Gambro Dasco, multinazionale biomedicale leader nella vendita delle sue apparecchiature per dialisi.
38
Wilson, Marya L. "Total quality management (TQM) at the University Centers." Menomonie, WI : University of Wisconsin--Stout, 2006. http://www.uwstout.edu/lib/thesis/2006/2006wilsonm.pdf.
Full text
39
Clark, Michael Colin. "The role(s) of ISO 9000 quality management systems in the management of educational institutions : an empirical and theoretical analysis." Thesis, University of Wolverhampton, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.297605.
Full text
40
Rieger, Dorothee. "Swahili as a tense prominent language." Universitätsbibliothek Leipzig, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:15-qucosa-90589.
Full textAbstract:
Swahili ist keineswegs eine besonders „exotische“ Sprache, aber dennoch fällt es schwer, eine gu-te moderne Grammatik des Standard-Swahili (Kiswahili sanifu) zu finden. Insbesondere die Inter-pretation der vorkommenden Tempora, Aspekte oder Modi des Verbs sind in den erhältlichen Grammatiken diskrepant bis widersprüchlich. Der Artikel versucht, einen systematischen Ansatz für eine strukturelle Matrix des TAM-Systems im Swahili herauszuarbeiten. Dabei beziehe ich mich auf die von Shankara Bhat in The Prominence of Tense, Aspect and Mood (1999) vorge-schlagene typologische Methode. Bhat legt dar, dass nicht jede Sprache jede Dimension von TAM gleich gewichtet, sondern dass jeweils eine davon vorherrscht. Eine Analyse von TAM in einer be-stimmten Sprache muss sich daher an der prominenten Dimension orientieren. Im Artikel wird herausgearbeitet, dass das Tempus die strukturierende Dimension im Swahili darstellt und dass im Gegensatz dazu der Aspekt nicht systematisch grammatikalisiert ist. Dabei war es nötig, die im Swahili vorkommenden TAM-Formen funktional zu interpretieren und zu benennen, da diese in der aktuellen Literatur teilweise sehr unterschiedlich analysiert werden.
41
Lammering, Tim [Verfasser]. "Integration of aircraft systems into conceptual design synthesis / Tim Lammering." Aachen : Hochschulbibliothek der Rheinisch-Westfälischen Technischen Hochschule Aachen, 2014. http://d-nb.info/1056993960/34.
Full text
42
Hohm, Tim [Verfasser]. "Modeling of Gene Regulative Networks in Developmental Systems / Tim Hohm." Aachen : Shaker, 2010. http://d-nb.info/1124364641/34.
Full text
43
Tröbs, Holger. "Sprachtypologie, TAM-Systeme und historische Syntax im Manding (West-Mande)." Köln Köppe, 2007. http://d-nb.info/987695282/04.
Full text
44
Sapparth, David James. "Refining Topographic Line Maps for Use with Ground Based Night Vision Systems." Queensland University of Technology, 2002. http://eprints.qut.edu.au/15877/.
Full textAbstract:
This study aims to refine the current cartographic standards and specifications used by the Australian Defence Force to produce the 1:50 000 scale Topographic Line Map (TLM) so that TLMs can be read with both normal chromatic vision and with achromatic NVG vision. The proliferation and integration of Night Vision Goggles (NVG) into the Australian Army has increased the operating capacity of forces at night. The Australian Army has incorporated NVG into standard operating procedures and training to the effect that Australian military personnel do not operate, at night, without NVG. The increased use of NVG in the Australian Army has required existing systems to be modified or redesigned to be effective within the limitations of NVG. The inability to read TLMs effectively with NVG is an identified problem within the Australian Army. This research has investigated the problems associated with using NVG and the information, which cannot be read on TLMs with NVG. This information was compared to a survey of features on a TLM that are critical for successful military operations. The combined information determined which features on a TLM were to be refined to enable effective reading with NVG. The scope of this research limited refinements to current or previous cartographic standards and specifications used by the Australian Army to produce TLMs. Refinements were limited to symbology, size, and colour and three critical information features of contours, watercourses and vegetation. The problems of cartographic design for a dual vision system (chromatic/achromatic) were investigated and it was determined that the common factor of value contrast exhibits the greatest effect on the refinement process. Prototype TLMs were produced and tested with normal and NVG vision to determine the best cartographic portrayal of the critical information features, without compromising the Figure/ground relationship, balance and cognitive meanings of the TLM. A final product was produced from the prototype experiment results providing a TLM for use with both normal and NVG vision. The refined TLM has changed contours from brown to black without changes to symbology or size and watercourses from 0.1mm width to 0.2mm width without changing colour or symbology. Vegetation was retained at the current standard and specification.
45
WANG, YANXIA. "HIGH SPEED TURBO TCM OFDM FOR UWB AND POWERLINE SYSTEM." Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3198.
Full textAbstract:
Turbo Trellis-Coded Modulation (TTCM) is an attractive scheme for higher data rate transmission, since it combines the impressive near Shannon limit error correcting ability of turbo codes with the high spectral efficiency property of TCM codes. We build a punctured parity-concatenated trellis codes in which a TCM code is used as the inner code and a simple parity-check code is used as the outer code. It can be constructed by simple repetition, interleavers, and TCM and functions as standard TTCM but with much lower complexity regarding real world implementation. An iterative bit MAP decoding algorithm is associated with the coding scheme. Orthogonal Frequency Division Multiplexing (OFDM) modulation has been a promising solution for efficiently capturing multipath energy in highly dispersive channels and delivering high data rate transmission. One of UWB proposals in IEEE P802.15 WPAN project is to use multi-band OFDM system and punctured convolutional codes for UWB channels supporting data rate up to 480Mb/s. The HomePlug Networking system using the medium of power line wiring also selects OFDM as the modulation scheme due to its inherent adaptability in the presence of frequency selective channels, its resilience to jammer signals, and its robustness to impulsive noise in power line channel. The main idea behind OFDM is to split the transmitted data sequence into N parallel sequences of symbols and transmit on different frequencies. This structure has the particularity to enable a simple equalization scheme and to resist to multipath propagation channel. However, some carriers can be strongly attenuated. It is then necessary to incorporate a powerful channel encoder, combined with frequency and time interleaving. We examine the possibility of improving the proposed OFDM system over UWB channel and HomePlug powerline channel by using our Turbo TCM with QAM constellation for higher data rate transmission. The study shows that the system can offer much higher spectral efficiency, for example, 1.2 Gbps for OFDM/UWB which is 2.5 times higher than the current standard, and 39 Mbps for OFDM/HomePlug1.0 which is 3 times higher than current standard. We show several essential requirements to achieve high rate such as frequency and time diversifications, multi-level error protection. Results have been confirmed by density evolution. The effect of impulsive noise on TTCM coded OFDM system is also evaluated. A modified iterative bit MAP decoder is provided for channels with impulsive noise with different impulsivity.Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
46
Käck, Emil. "TLS Decryption in passive monitoring system with server private key." Thesis, Umeå universitet, Institutionen för datavetenskap, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-184490.
Full textAbstract:
Many network operators need to be able to ensure that customers get the level of service they pay for. To avoid bandwidth and server performance bottlenecks, and easily troubleshoot network problems, the network providers need to be able to see what payload data is sent. Modern networks encrypt data when sending it between nodes that makes passive monitoring more complex. A prevalent encryption mechanism on an IP-based network is TLS that needs to be decrypted. This article’s purpose is to check if it is possible to decrypt TLS traffic in a passive monitoring system with the server’s private key. This is done by implementing a decryptor in a passive monitoring system in the programming language Java. The implemented solution intercepts the traffic, takes out relevant data from the traffic, and derives the session key from that data. How this is done is dependent on what cipher suite is used for the session. Because of delimitations and lack of time the solution is only able to decrypt the cipher suite TLS_RSA_WITH_AES_128_CBC_SHA256. The result showed that it is possible to decrypt TLS traffic and should be possible for more than the specified cipher suite. But there exists a major problem that's called forward secrecy. This is used in the key exchange algorithm called Diffie–Hellman and makes it impossible to decrypt with only server private key. The conclusion is that it is possible but because of forward secrecy, it is not recommended. TLS 1.3 only uses cipher suites with the key exchange algorithm Diffie–Hellman and the forward secrecy functionality is important for security.
47
Rydholm, Jonas. "Implementering av underhållssystem vid en tillverkande industri." Thesis, Högskolan Väst, Avdelningen för maskinteknik och naturvetenskap, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:hv:diva-7760.
Full textAbstract:
Företaget som studien utförts på upplever ett problem vid hanteringen av underhållsarbete i fabriken. Processerna för felrapportering och beställning av reservdelar är tidskrävande och involverar arbete från flera olika parter. Merparten av allt underhållsarbete som utförs är av oplanerat slag och ett fungerande uppföljningsarbete för att komma till rätta med de pro-duktionsstörningar som äger rum i processen saknas. Syftet med examensarbetet har varit att skapa underlag för att förbättra företagets effektivitet genom att optimera underhållsarbetet med hjälp av förslag till ett underhållssystem och olika tillvägagångssätt för att effektivisera underhållsarbetet. Under arbetets gång har en underhållsloggbok utformats i Excel. Loggboken används till att logga alla underhållsarbeten som inträffar i produktionen. Dessa arbeten ligger till grund för merparten av de beräkningar som utförts under projektet. Beräkningarna syftade till att kartlägga var i processen flest fel inträffar och av vilken karaktär dessa fel är. För att påvisa potentialen i ett utvecklat underhållsarbete beräknades även vilka vinstmöjligheter som kan åstadkommas genom implementering av ett underhållssystem och nya arbetsmetoder. Studien resulterade i ett förslag till ett underhållssystem som anses lämpligt utefter företagets situation och problem. Utöver införandet av ett underhållssystem stod det även klart att fö-retaget behöver minska mängden oplanerade produktionsstopp. För att lyckas med detta är det viktigt att operatörerna involveras i underhållsarbetet och utför alla arbeten av enklare slag. Underhållsavdelningen kan då, tack vare mer frigjord tid fokusera på att finna grundor-saker till problem och utföra planerade underhåll för att minska mängden oplanerade under-håll. Att effektivisera underhållsarbetet och införa Total productive maintenance (TPM) är en tidskrävande process som kan ta många år. För att underlätta för företaget och minska risken för att trilla tillbaks i gamla vanor utformades en implementeringsmodell för TPM. Modellen är ämnad som ett framtida arbete för företaget i arbetet med att utveckla effektiviteten på företaget ytterligare.The company in the study was experiencing a problem when it comes to dealing with maintenance-work. The processes for bug tracking and ordering of spare parts is time con-suming and involves work from several different people. Most of all maintenance work performed is unplanned and a functioning follow-up work is missing. The purpose of the thesis was to help improving the company's efficiency by optimizing the maintenance work. This was achieved by a proposal for a maintenance system and vari-ous approaches to improve the maintenance work. During the project a maintenance log book was been designed in Excel. The log book is used to log all maintenance activities that occur in the production. These logs are the basis for most of the calculations carried out during the project. The calculations aimed to identify where in the process most errors occur and what the na-ture of those errors are. To demonstrate the potential of a maintenance system the profit opportunities that can be achieved through the implementation of a maintenance system and new working methods were calculated. The study resulted in a proposal for a maintenance system that suited the company's needs, situation and problems. In addition to the introduction of a maintenance system, it was also clear that the company needs to reduce the amount of unplanned downtime. To achieve this it is important to involve the operators with maintenance work and they shall perform all the works of the simpler kind. The maintenance department can then, thanks to the re-leased time, focus on finding the root causes of problems and perform scheduled mainte-nance to reduce the amount of unplanned maintenance. Improving the maintenance work and introduce Total Productive Maintenance (TPM) is a time consuming process that might go on for years. In order to facilitate the work and re-duce the risk of falling back into old habits an implementation model was designed for the TPM-work. The model is intended as a future work for the company to facilitate the work of reaching even higher efficiency.
48
Dalibor, Berić. "Model informacionog sistema za podršku upravljanju industrijskim preduzećima." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2019. https://www.cris.uns.ac.rs/record.jsf?recordId=110609&source=NDLTD&language=en.
Full textAbstract:
Na osnovu istraživanja u ovoj disertaciji i implemetiranogsoftverskog rešenja za podršku upravljanju industrijskimpreduzećima utvrđeno je da sama implementacija ERP sistema nijedovoljna, i da su potrebni MES sistemi koji pružaju informacije urealnom vremenu koje pomažu da se donese odluka u cilju unapređenjaproizvodnih sistema i omogućuju kontrolu nad svim elementimaproizvodnog procesa, prema osnovnim načelima LEAN proizvodnje iTQM.Based on the research in this dissertation and implementation оf softwaresolution for support of management of industrial enterprises it was found thatimplementation of ERP systems is not sufficient, and it is necessaryimplementation of MES systems which provide real-time information formaking a decision for improvement of the production system and enablecontrol of all elements of the manufacturing process, according to the basicprinciples of LEAN production and TQM.
49
Ludurczak, Willy. "Capteur d’humidité en Si poreux pour la fiabilité des systems in package." Thesis, Bordeaux 1, 2008. http://www.theses.fr/2008BOR12244/document.
Full textAbstract:
La problématique de cette thèse est l’amélioration de la fiabilité des systèmes électroniques encapsulés, concernant l’herméticité et les perturbations causées par les infiltrations d’humidité. Le travail consiste en l’étude d’un capteur pour mesurer in situ le taux d’humidité dans les cavités des systèmes encapsulés. Comparativement aux actuelles techniques d’évaluation de l’herméticité, l’intérêt du dispositif réside dans la généralisation du test à chaque cavité, le contrôle de l’atmosphère de la cavité sur une longue période d’utilisation, et la correction automatique de la dérive occasionnée (packaging intelligent). Deux structures en Si poreux (SP) ont été étudiées pour réaliser des capteurs, et ont d’abord été caractérisées d’un point de vue morphologique. Les deux couches ont la même porosité de 45 %. Les mesures de sorption d’azote appliquées aux théories BET et BJH ont montré que SP1 et SP2 présentaient respectivement des surfaces spécifiques de 330 et 223 m²/g, et des diamètres poreux moyens de 4,3 et 5.5 nm. Une nouvelle méthode de caractérisation basée sur le traitement d’image de surface de Si poreux est présentée. La méthode permet d’estimer les distributions de taille de pore (DTP), porosité, surface spécifique et fraction volumique d’oxyde. Elle est validée par la cohérence des résultats obtenus, comparés à ceux donnés par les théories de sorption. Outre le caractère complet de l’analyse, les avantages de cette méthode sont sa simplicité de mise en œuvre, sa non restriction à une gamme de taille de pores, et l’absence d’hypothèse mathématique sur l’estimation de la DTP. Les tests électriques ont montré que SP1 présentait une résistance supérieure à SP2 et que le capteur basé sur SP1 présentait une plus grande sensibilité vis-à-vis de la prise d’humidité : -90 % entre 0 et 80 % d’humidité relative. La spécificité du transport électrique dans les structures étudiées a été mise en évidence expérimentalement, conduisant à l’hypothèse d’une barrière de potentiels à l’interface Si - Si poreux. La plus grande résistance présentée par SP1 a été explicitée par sa plus grande fraction volumique d’oxyde, ainsi que les effets plus prononcés de confinement quantique et de déplétion de surface. L’utilité d’un capteur d’humidité in situ en Si poreux pour l’herméticité des systems in package a été démontrée par les résultats expérimentaux d’un prototypeThis work deals with the improvement of reliability of packaged electronic devices, concerning the hermeticity and the disturbances caused by moisture infiltration. As an analysis method of sealing quality of Systems in Package (SiP), a study of humidity sensors for in situ moisture level evaluation of SiP microcavities is presented. Compared to others analysis methods, the interest of the present one is its global utility for all manufactured chips, the capability to monitor the cavities atmosphere over a long period, and the possibility of automatic drifts correction. Two porous silicon (PS) based structures have been studied to make sensors. First we performed morphological analyses of PS layers. Both have a porosity of 45 %. Nitrogen sorption measurements applied to BET and BJH theories showed that PS1 and PS2 respectively present specific areas of 330 and 223 m²/g and mean pore diameters of 4.3 and 5.5 nm. A new analysis method based on processing of PS surface images is presented. It allows the estimation of pore size distribution (PSD), porosity, specific area, and volumic oxide ratio. The method has been validated by the closeness between its results and sorption theories results. In addition to the method’s completeness, it presents several advantages such as easy-to-use application, no restriction on PSD range, and no computing hypothesis on PSD evaluation. Electrical measurements showed that PS1 resistance is higher than PS2 resistance, and that sensitivity of PS1 based sensors exposed to moisture variation is superior: -90 % from 0 to 80 % relative humidity. Specificity of carriers transport in PS structures has been experimentally underlined; leading to the hypothesis of a potential barrier between PS and non porous Si. Higher resistance has been explained by the higher volumic oxide ratio of PS1, and the more developed quantum confinement and depletion surface effects. Utility of such in situ PS moisture sensor for SiP hermeticity has been demonstrated by preliminary experimental results
50
Chen, An. "Buffer-efficient RTA algorithms in optical TDM networks /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20CHENA.
Full text