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Journal articles on the topic 'SystemC TLM'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Le, Hoang M., Daniel Grosse, and Rolf Drechsler. "Automatic TLM Fault Localization for SystemC." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 8 (August 2012): 1249–62. http://dx.doi.org/10.1109/tcad.2012.2188800.

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2

Monton, Màrius, Jakob Engblom, and Mark Burton. "Checkpointing for Virtual Platforms and SystemC-TLM." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 1 (January 2013): 133–41. http://dx.doi.org/10.1109/tvlsi.2011.2181881.

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3

Jovanovic, S., and S. Weber. "Modélisation SystemC-TLM de systèmes à base de processeur." J3eA 18 (2019): 1009. http://dx.doi.org/10.1051/j3ea/20191009.

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Nous présentons un ensemble de travaux pratiques qui seront dispensés au sein du Master EEA - Électronique Embarquée à l'université de Lorraine dans le cadre du module « Modélisation SystemC ». Ces TP sont destinés à initier les étudiants à la modélisation de systèmes et circuits numériques en SystemC-TLM et sont organisés autour de la suite logicielle open source Eclipse et de la chaine de compilation gcc pour la simulation, test et vérification.

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Chen, Mingsong, Prabhat Mishra, and Dhrubajyoti Kalita. "Automatic RTL Test Generation from SystemC TLM Specifications." ACM Transactions on Embedded Computing Systems 11, no. 2 (July 2012): 1–25. http://dx.doi.org/10.1145/2220336.2220350.

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Zimmermann, Thomas, Mathias Mora, Sebastian Steinhorst, Daniel Mueller-Gritschneder, and Andreas Jossen. "Analysis of Dissipative Losses in Modular Reconfigurable Energy Storage Systems Using SystemC TLM and SystemC-AMS." ACM Transactions on Design Automation of Electronic Systems 24, no. 4 (July 24, 2019): 1–33. http://dx.doi.org/10.1145/3321387.

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Bombieri, Nicola, Franco Fummi, Valerio Guarnieri, and Graziano Pravadelli. "Testbench Qualification of SystemC TLM Protocols through Mutation Analysis." IEEE Transactions on Computers 63, no. 5 (May 2014): 1248–61. http://dx.doi.org/10.1109/tc.2012.301.

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Pierre, Laurence, and Luca Ferro. "A Tractable and Fast Method for Monitoring SystemC TLM Specifications." IEEE Transactions on Computers 57, no. 10 (October 2008): 1346–56. http://dx.doi.org/10.1109/tc.2008.74.

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Bombieri, Nicola, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli, Francesco Stefanni, Tara Ghasempouri, Michele Lora, Giovanni Auditore, and Mirella Negro Marcigaglia. "Reusing RTL Assertion Checkers for Verification of SystemC TLM Models." Journal of Electronic Testing 31, no. 2 (March 20, 2015): 167–80. http://dx.doi.org/10.1007/s10836-015-5514-8.

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9

Cheng, Zhongqi, and Rainer Dömer. "Analyzing Variable Entanglement for Parallel Simulation of SystemC TLM-2.0 Models." ACM Transactions on Embedded Computing Systems 18, no. 5s (October 19, 2019): 1–20. http://dx.doi.org/10.1145/3358194.

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10

ESCOBAR-JUZGA, F. A., and F. E. SEGURA-QUIJANO. "PERFORMANCE ANALYSIS OF A JPEG ENCODER MAPPED ONTO A VIRTUAL MPSoC-NoC ARCHITECTURE USING TLM 2.0.1." Journal of Circuits, Systems and Computers 22, no. 05 (May 9, 2013): 1350036. http://dx.doi.org/10.1142/s0218126613500369.

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Networks on Chip (NoCs) are commonly used to integrate complex embedded systems and multiprocessor platforms due to their scalability and versatility. Modeling tools used at the functional level use SystemC to perform hardware–software co-design and error correction concurrently, thus, reducing time to market. This work analyzes a JPEG encoding algorithm mapped onto a configurable M × N, mesh/torus, NoC platform described in SystemC with the transaction level modeling (TLM) standard; timing constraints for both, the router and network interface controller, are assigned according to a hardware description language (HDL) model written for this purpose. Processing nodes are also described as SystemC threads and their computation delays are assigned depending on the amount and cost of the operations they perform. The programming model employed is message passing. We start by describing and profiling the JPEG algorithm as a task graph; then, four partitioning proposals are mapped onto three NoCs of different size. Our analysis comprises changes in topology, virtual channel depth, routing algorithms, network speed and task-node assignments. Through several high-level simulations we evaluate the impact of each parameter and we show that, for the proposed model, most improvements come from the algorithm partitioning.

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Conti, Massimo, Marco Caldari, Matteo Gianfelici, Adriana Ricci, and Franco Ripa. "SystemC/TLM Controller for Efficient NAND Flash Management in Electronic Musical Instruments." Electronics 7, no. 5 (May 18, 2018): 75. http://dx.doi.org/10.3390/electronics7050075.

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12

Gao, Yanyan, and Xi Li. "A Semantics-based Translation Method for Automated Verification of SystemC TLM Designs." Journal of Electronic Testing 29, no. 5 (October 2013): 685–95. http://dx.doi.org/10.1007/s10836-013-5406-8.

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13

Allem, Khaled, El-Bay Bourennane, and Youcef Khelfaoui. "A Service-Oriented Component-Based Framework for Dynamic Reconfiguration Modeling Targeting SystemC/TLM." International Journal of Reconfigurable Computing 2021 (August 3, 2021): 1–31. http://dx.doi.org/10.1155/2021/5584391.

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To deal with the complex design issues of Dynamically Reconfigurable Systems-on-Chip (DRSoCs), it is extremely relevant to raise the abstraction level in which models are expressed. A high abstraction level allows great flexibility and reusability while bypassing low-level implementation details. In this context, model-driven engineering (MDE) provides support to build and transform precise and structured models for a particular purpose at different levels of abstraction. Indeed, high-level models are successively refined to low-level models until reaching the executable ones. Thus, this paper presents an MDE-based framework for DRSoCs design enabling the transformation of UML/MARTE specifications to SystemC/TLM implementation. To achieve a high degree of expressiveness for modeling dynamic reconfiguration, we use a suitable software engineering approach based on service-oriented component architecture. Since MARTE does not cover the common features of dynamic reconfiguration domain and service orientation concepts, new stereotypes are created by refinement to add missing capabilities to the profile. Likewise, SystemC does not provide native support for dynamic reconfiguration, thus leading us to adopt a design pattern based solution for DRSoCs implementation in compliance with standards. The proposed framework is validated through a reconfigurable active 3-way crossover case study in which we demonstrate the practicability of the approach by gradual model transformations with reduced implementation effort and significant design productivity gain.

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Cheema, Muhammad Omer, Lionel Lacassagne, and Omar Hammami. "System-Platforms-Based SystemC TLM Design of Image Processing Chains for Embedded Applications." EURASIP Journal on Embedded Systems 2007 (2007): 1–14. http://dx.doi.org/10.1155/2007/71043.

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Cheema, MuhammadOmer, Lionel Lacassagne, and Omar Hammami. "System-Platforms-Based SystemC TLM Design of Image Processing Chains for Embedded Applications." EURASIP Journal on Embedded Systems 2007, no. 1 (2007): 071043. http://dx.doi.org/10.1186/1687-3963-2007-071043.

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16

El Hariti, Zineb, Abdelhakim Alali, Mohamed Sadik, and Kaoutar Aamali. "Cosimulation of Power and Temperature Models at the SystemC/TLM for a Soft-Core Processor." Advances in Materials Science and Engineering 2020 (February 11, 2020): 1–7. http://dx.doi.org/10.1155/2020/2567915.

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Nowadays, modern embedded applications are becoming more and more complex and resource demanding. Fortunately, Systems on Chip (SoC) are one of the keys used to follow their requirements that stand in need of high performance while maintaining a low-power profile. On one hand, today, due to the limited power budget imposed by the batteries, power is the limiting factor of the logic CMOS. On the other hand, the downscaling of the technology node for 65 nm and beyond, based on the International Technology Roadmap for Semiconductors (ITRS) as a reference, has not only resulted in huge energy consumption but also increased the temperature chip. To address this challenge, designing at the system level is the suitable measure to tackle with the complexity of the Systems on Chip, aiming at having better adjustment between timing and accuracy for power and temperature estimations. We present in this paper, at the first stage, two models describing the static and dynamic power at the physical level. These models are implemented on an open virtual platform Model Power-Consumption and Temperature in SystemC/TLM (LIBTLMPWT) based on a representative SoC architecture. At the second stage, we focus on power, especially the thermal behaviour of the chip while running three benchmarks set on the game of life application for two different technology nodes.

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Boukhechem, Sami, and El-Bay Bourennane. "SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication." International Journal of Reconfigurable Computing 2008 (2008): 1–10. http://dx.doi.org/10.1155/2008/902653.

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Transaction-level modeling (TLM) is a promising technique to deal with the increasing complexity of modern embedded systems. This model allows a system designer to model a complete application, composed of hardware and software parts, at several levels of abstraction. For this purpose, we use systemC, which is proposed as a standardized modeling language. This paper presents a transaction-level modeling cosimulation methodology for modeling, validating, and verifying our embedded open architecture platform. The proposed platform is an open source multiprocessor system-on-chip (MPSoC) platform, integrated under the synthesis tool for adaptive and reconfigurable system-on-chip (STARSoC) environment. It relies on the integration between an open source instruction set simulators (ISSs), OR1Ksim platform, and the systemC simulation environment which contains other components (wishbone bus, memories, , etc.). The aim of this work is to provide designers with the possibility of faster and efficient architecture exploration at a higher level of abstractions, starting from an algorithmic description to implementation details.

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18

Becker, Denis, Matthieu Moy, and Jérôme Cornet. "Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study." Electronics 5, no. 4 (May 17, 2016): 22. http://dx.doi.org/10.3390/electronics5020022.

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19

Kuehnle, Matthias, Andre Wagner, Alisson V. Brito, and Juergen Becker. "Modeling and Implementation of a Power Estimation Methodology for SystemC." International Journal of Reconfigurable Computing 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/439727.

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This work describes a methodology to model power consumption of logic modules. A detailed mathematical model is presented and incorporated in a tool for translation of models written in VHDL to SystemC. The functionality for implicit power monitoring and estimation is inserted at module translation. The translation further implements an approach to wrap RTL to TLM interfaces so that the translated module can be connected to a system-level simulator. The power analysis is based on a statistical model of the underlying HW structure and an analysis of input data. The flexibility of the C++ syntax is exploited, to integrate the power evaluation technique. The accuracy and speed-up of the approach are illustrated and compared to a conventional power analysis flow using PPR simulation, based on Xilinx technology.

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20

Bushager, Aisha, and Mark Zwolinski. "Evaluating system security using Transaction Level Modelling." Facta universitatis - series: Electronics and Energetics 27, no. 1 (2014): 137–51. http://dx.doi.org/10.2298/fuee1401137b.

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The design of secure systems requires the use of security analysis techniques. Security objectives have to be considered during the early stages of system development and design; an executable model will give the designer the advantage of exploring the vulnerabilities early, and therefore enhancing the system security. In this work we create an executable model of a smart card system using SystemC with the Transaction Level Modelling (TLM) extensions. The model includes the security protocols and transactions. The model is used to compare a number of authentication mechanisms with different probabilities of failure. In addition, a number of probable attacks, including theft of a private key and denial of service were modelled to examine the vulnerabilities. The executable model shows that security protocols and transactions can be effectively simulated in order to design improvements to withstand different types of security attacks.

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21

Safar, Mona, Magdy A. El-Moursy, Ahmed Tarek, Ahmed Emad, Ahmed Hesham, Ashraf Salem, and Mohsen Mahroos. "Fast Transaction-Level Model for Direct Memory Access Controller." Journal of Circuits, Systems and Computers 28, no. 04 (March 31, 2019): 1950059. http://dx.doi.org/10.1142/s0218126619500592.

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Transaction-Level Modeling (TLM) has been widely used in system-level design in the past few years. Simulation speed of Virtual Platforms (VPs) depends mainly on the transactions which are initiated by the Programmer’s View (PV) models of the VP devices. PV models are required to run at highest simulation speed. Data bus width as a hardware (HW) parameter should not reduce simulation speed of the modeled transactions. Furthermore, HW-related parameters should only be accounted for when considering timing of the models. A fast SystemC-TLM model is developed for the widely used ARM PrimeCell PL080 DMAC IP. The performance of the proposed model is validated against a developed RTL model for the same device. The effect of the transactions granularity on simulation speed is determined. Different programmed transfers are simulated and compared with open-source Quick Emulator (QEMU)-based models. The developed model is compared with the developed RTL, the open-source QEMU model, and the existing ARM Fast Model (AFM). It is shown that simulation time of the developed model is reduced by two orders of magnitude as compared to the other existing models.

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22

Oliveira, Helder F. A., Alisson V. Brito, Joseana M. F. R. Araujo, and Elmar U. K. Melcher. "An Approach for Power Estimation at Electronic System Level using Distributed Simulation." Journal of Integrated Circuits and Systems 11, no. 3 (December 28, 2016): 159–70. http://dx.doi.org/10.29292/jics.v11i3.440.

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The present research aims to develop an approach using HLA (High Level Architecture), enabling the cre-ation of a distributed and heterogeneous environment, composed by different tools and models to obtain a better trade-off between accuracy and run time in power estimation. These models can be described in different languages and/or abstraction levels, as well as use different power estimation approaches. The use of HLA enables the synchronized and distributed simulation of the elements that compose the simulation environment. The approach must allow the collecting and grouping of power estimation data in a centralized manner. As a case study, an MPSoC (MultiProcessor System-on-Chip) ESL/TLM model, described in C++/SystemC, and an ESL model, created on Ptolemy framework, have been used. The experimental results show the flexibility of the approach, which promotes an integrated view of power estimation data.

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23

Sun, Guanyi, Shengnan Xu, Xu Wang, Dawei Wang, Eugene Tang, Yangdong Deng, and Sun Chan. "A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips." VLSI Design 2011 (September 15, 2011): 1–17. http://dx.doi.org/10.1155/2011/726014.

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Today's System-on-Chips (SoCs) design is extremely challenging because it involves complicated design tradeoffs and heterogeneous design expertise. To explore the large solution space, system architects have to rely on system-level simulators to identify an optimized SoC architecture. In this paper, we propose a system-level simulation framework, System Performance Simulation Implementation Mechanism, or SPSIM. Based on SystemC TLM2.0, the framework consists of an executable SoC model, a simulation tool chain, and a modeling methodology. Compared with the large body of existing research in this area, this work is aimed at delivering a high simulation throughput and, at the same time, guaranteeing a high accuracy on real industrial applications. Integrating the leading TLM techniques, our simulator can attain a simulation speed that is not slower than that of the hardware execution by a factor of 35 on a set of real-world applications. SPSIM incorporates effective timing models, which can achieve a high accuracy after hardware-based calibration. Experimental results on a set of mobile applications proved that the difference between the simulated and measured results of timing performance is within 10%, which in the past can only be attained by cycle-accurate models.

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24

XIA, BINGBING, FEI QIAO, ZIDONG DU, DI ZHU, and HUAZHONG YANG. "A "NEAR-THE-BEST" SYSTEM-LEVEL DESIGN METHODOLOGY OF MULTI-CORE H.264 VIDEO DECODER BASED ON THE PARALLELIZED MULTI-CORE SIMULATOR." Journal of Circuits, Systems and Computers 21, no. 07 (November 2012): 1250058. http://dx.doi.org/10.1142/s0218126612500582.

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H.264 video decoder is a good choice for embedded video processing applications because of its higher compression ratio than MPEG2, although it has higher requirements of run-time computational resource. Multi-core system is the future of the embedded processor design for its power efficiency and multi-thread parallelization capability, and can be used to fit well with the requirements for such video processing algorithms. To simulate and evaluate the performance of these multi-core systems effectively, a design flow at the system level is developed, at the higher level, the combination of TLM language (SystemC) and shared-memory parallel programming model (OpenMP) is used for such transaction-level simulation, and at the lower level, a multi-core simulator based on the extension of the SimpleScalar 3.0 ToolSet is developed for the cycle-accurate level simulation. Compared with other high-level simulation methods, ours has the ability to realize the true-parallelization simulation. What is more, experiments show that such simulation methodology can effectively simulate these complex multi-core applications in a short time to get the appropriate core number and the task allocation strategy (much less than RTL-level simulation) and the results can get at less than 15% deviated from the ideal ones calculated based on Amadal's Law, so the parallelization strategy obtained from such simulation is the best one that can be further applied for the RTL-level design of the final multi-core system.

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Imamalieva, S. Z., I. F. Mehdiyeva, I. R. Amiraslanov, and M. B. Babanly. "Investigation of the Tl2 Te-Tl9 ErTe6 and Tl5 Te3 - Tl9 ErTe6 systems." Applied solid state chemistry 4 (December 31, 2018): 76–81. http://dx.doi.org/10.18572/2619-0141-2018-4-5-76-81.

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26

Mun, JeOk, and SungPil Yoon. "Literature Review of Key Success Factors of Management Innovation Actions in Domestic - Focused on Six Sigma, TQM, Lean Six Sigma, ERP, TPM, BPR, Project Management, System Engineering -." Journal of the Korean society for quality management 44, no. 3 (September 30, 2016): 639–48. http://dx.doi.org/10.7469/jksqm.2016.44.3.639.

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27

Moreno, P., M. Ruiz, and F. J. Gorines. "TBM Process Data Management System." International Journal of Engineering and Technology 7, no. 5 (December 2015): 431–34. http://dx.doi.org/10.7763/ijet.2015.v7.832.

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28

Fazlagić, Jan. "Specificity of Finnish education system in comparison to Polish system." e-mentor 2015, no. 2(59) (April 30, 2015): 4–15. http://dx.doi.org/10.15219/em59.1164.

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29

Oliveira, Tiago, Denise Stringhini, and Jose Jailson Santos Craibas. "A Practical and Systemic Curricular Approach to Teach Computer Systems." IEEE Latin America Transactions 17, no. 08 (August 2019): 1349–62. http://dx.doi.org/10.1109/tla.2019.8932345.

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Kukharenko, Vladimir, Kirill Ziborov, Rafael Sadykov, and Ruslan Rezin. "Verification of HotStuff BFT Consensus Protocol With TLA+/TLC in an Industrial Setting." SHS Web of Conferences 93 (2021): 01006. http://dx.doi.org/10.1051/shsconf/20219301006.

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The extent of formal verification methods applied in industrial projects has always been limited. The proliferation of distributed ledger systems (DLS), also known as blockchain, is rapidly changing the situation. Since the main area of DLSs’ application is the automation of financial transactions, the properties of predictability and reliability are critical for implementing such systems. The actual behavior of the DLS is largely determined by the chosen consensus protocol, which properties require strict specification and formal verification. Formal specification and verification of the consensus protocol is necessary but not sufficient. It is also required to ensure that the software implementation of the DLS nodes complies with this protocol. Finally, the verified software implementation of the protocol must run on a fairly reliable operating system. The financial focus of DLS application has also led to the emergence of the so-called smart contracts, which are an important part of the applied implementations of specific business processes based on DLSs. Therefore, the verifiability of smart contracts is also a critical requirement for industrial DLSs. In this paper, we describe an ongoing industrial project between a large Russian airline and three universities – Innopolis University (IU), Moscow Institute of Physics and Technology (MIPT) and Lomonosov Moscow State University (MSU). The main expected project result is a DLS for more flexible refueling of aircrafts, verified at least at the four technological levels described above. After brief project overview, we focus on our experience with the formal specification and verification of HotStuff, a leader-based fault-tolerant protocol that ensures reaching distributed consensus in the presence of Byzantine processes. The formal specification of the protocol is performed in the TLA+ language and then verified with a specialized TLC tool to verify models based on TLA+ specifications.

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Abdi, Samar, Yonghyun Hwang, Lochi Yu, Gunar Schirner, and Daniel D. Gajski. "Automatic TLM Generation for Early Validation of Multicore Systems." IEEE Design & Test of Computers 28, no. 3 (May 2011): 10–19. http://dx.doi.org/10.1109/mdt.2010.117.

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32

Christopoulos, C., and P. Naylor. "Coupling between electromagnetic fields and multiconductor transmission systems using TLM." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 1, no. 1 (March 1988): 31–43. http://dx.doi.org/10.1002/jnm.1660010106.

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Naylor, P., and C. Christopoulos. "Coupling between electromagnetic fields and multimode transmission systems using TLM." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2, no. 4 (December 1989): 227–40. http://dx.doi.org/10.1002/jnm.1660020406.

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Dinavahi, V. "Transient Analysis of Systems With Multiple Nonlinear Elements Using TLM." IEEE Transactions on Power Systems 19, no. 4 (November 2004): 2102–3. http://dx.doi.org/10.1109/tpwrs.2004.836165.

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35

Gross, U., and P. Hagemann. "Modern TEM systems architecture." Proceedings, annual meeting, Electron Microscopy Society of America 44 (August 1986): 602–5. http://dx.doi.org/10.1017/s0424820100144486.

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By addition of analytical equipment, scanning transmission accessories and data processing equipment the basic transmission electron microscope (TEM) has evolved into a comprehensive information gathering system. This extension has led to increased complexity of the instrument as compared with the straightforward imaging microscope, since in general new information capacity has required the addition of new control hardware. The increased operational complexity is reflected in a proliferation of knobs and buttons.In the conventional electron microscope design the operating panel of the instrument has distinct control elements to alter optical conditions of the microscope column in different modes. As a consequence a multiplicity of control functions has been inevitable. Examples of this are the three pairs of focus and magnification controls needed for TEM imaging, diffraction patterns, and STEM images.

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Jiehui Xie, Jiehui Xie, Fuyin Wang Fuyin Wang, Yao Pan Yao Pan, Zhengliang Hu Zhengliang Hu, and Yongming Hu Yongming Hu. "Optical fiber acoustic sensing multiplexing system based on TDM/SFDM." Chinese Optics Letters 13, no. 1 (2015): 010401–10404. http://dx.doi.org/10.3788/col201513.010401.

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Kim. "Development of simulation equipment system on EPB shield TBM hood operation." Journal of Korean Tunnelling and Underground Space Association 16, no. 2 (2014): 193. http://dx.doi.org/10.9711/ktaj.2014.16.2.193.

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GONZÁLEZ VÁZQUEZ, B., J. M. CHOUBERT, E. PAUL, and J. P. CANLER. "Comment éviter le colmatage irréversible des installations de biofiltration ?" Techniques Sciences Méthodes, no. 11 (November 20, 2020): 71–86. http://dx.doi.org/10.36904/tsm/202011071.

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La biofiltration est une technologie compacte et efficace pour le traitement des effluents urbains. Certaines installations sont régulièrement touchées par un colmatage irréversible, nécessitant une opération curative pour retrouver sa capacité de traitement. Une première enquête menée en 2007 avait évalué l’ampleur du colmatage des biofiltres, et sensibilisé exploitants et concepteurs au phénomène. En 2018, une seconde enquête a réévalué l’ampleur du colmatage des biofiltres, a approfondi les causes et les moyens de détection de ce phénomène. Nous avons consulté les 128 biofiltres existants sur le territoire national ainsi que quelques installations d’autres pays européens, afin de collecter des données de construction et d’exploitation de différentes technologies (Biofor, Biostyr, Biolest, Biopur) fonctionnant dans différentes configurations. Nous avons également recueilli les informations concernant les cycles de lavage et la fréquence observée des colmatages irréversibles. Le taux de réponse a été de 33% donnant un échantillon de réponse représentatif du parc de biofiltres français. Nous avons montré que le colmatage irréversible semble en régression et touche principalement les installations en première étape de traitement (après le décanteur primaire). Le risque de colmatage irréversible est important au-delà de 5,8 kg de demande chimique en oxygène (DCO)/m3 matériau/cycle de filtration et de 2,1 kg de matières en suspension (MES)/m3 matériau/cycle. Néanmoins, il est également important pour des charges volumiques inférieures dans le cas d’effluents très organiques (ratios DCO/MES > 3,2), lié à une accumulation importante de biomasse malgré la faible charge en matières en suspension appliquée. L’étude a permis d’énoncer et de hiérarchiser des règles d’exploitation comprenant des indicateurs de dérive vers le colmatage irréversible, ainsi que des moyens de lutte préventifs et curatifs.

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Zhou, Tong, Ling Liu, and Calton Pu. "TAM." ACM SIGMOD Record 28, no. 2 (June 1999): 571–73. http://dx.doi.org/10.1145/304181.304580.

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Pomeroy, S. C., H. R. Williams, and P. Blanchfield. "Evaluation of ultrasonic inspection and imaging systems for robotics using TLM modelling." Robotica 9, no. 3 (July 1991): 283–90. http://dx.doi.org/10.1017/s0263574700006445.

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SUMMARYAirborne ultrasound based sensor systems have been applied to a variety of problems in robotics and advanced manufacturing. These include slot and hole inspection, and systems suitable for workspace imaging and autonomous guided vehicle (AGV) navigation. The transmission line matrix (TLM) method of modelling wave propagation has been used in the evaluation of these systems. The model gives both graphical and numerical outputs, and allows an improved understanding of the interaction of ultrasonic waves and targets to be obtained.

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Bombieri, Nicola, Franco Fummi, and Davide Quaglia. "System/network design-space exploration based on TLM for networked embedded systems." ACM Transactions on Embedded Computing Systems 9, no. 4 (March 2010): 1–32. http://dx.doi.org/10.1145/1721695.1721703.

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Buonaquisti, Anthony D. "Digital Imaging For TEM." Microscopy Today 2, no. 9 (December 1994): 10–11. http://dx.doi.org/10.1017/s1551929500067651.

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Part 1 of this series, in the August '94 issue of this newsletter, contained an overview of digital imaging for TEM. The key point was that digital imaging systems are getting better and costing less. This article contains a brief summary of the pro's and con's of digital imaging for TEM.Although different laboratories have different situations, there are common issues that all can consider when evaluating the value of a digital imaging system for TEM.Information Density: As things stand today, atypical 1024 pixel by 1024 pixel digital imaging system cannot compare with film! Typical film used for EM can display feature sizes as small as 10 μm. This is like having a film negative made up of 10,400 pixels by 7,800 pixels. Put this way it's tough to see how a factor of between 7 and 10 can be ignored.

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Burstyn-Cohen, Tal, and Arielle Hochberg. "TAM Signaling in the Nervous System." Brain Plasticity 7, no. 1 (August 23, 2021): 33–46. http://dx.doi.org/10.3233/bpl-210125.

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Tyro3, Axl and Mertk are members of the TAM family of tyrosine kinase receptors. TAMs are activated by two structurally homologous ligands GAS6 and PROS1. TAM receptors and ligands are widely distributed and often co-expressed in the same cells allowing diverse functions across many systems including the immune, reproductive, vascular, and the developing as well as adult nervous systems. This review will focus specifically on TAM signaling in the nervous system, highlighting the essential roles this pathway fulfills in maintaining cell survival and homeostasis, cellular functions such as phagocytosis, immunity and tissue repair. Dysfunctional TAM signaling can cause complications in development, disruptions in homeostasis which can rouse autoimmunity, neuroinflammation and neurodegeneration. The development of therapeutics modulating TAM activities in the nervous system has great prospects, however, foremost we need a complete understanding of TAM signaling pathways.

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Bistričić, Ante. "PROJECT INFORMATION SYSTEM." Tourism and hospitality management 12, no. 2 (December 2006): 213–24. http://dx.doi.org/10.20867/thm.12.2.19.

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Information system must provide data, information and adequate information technology for: the running of the business process, management (subsystems and business functions etc.), expertise basics for management decision-making and, main business system management. In business systems three dimensions determine management, namely: executive body management, adaptation and development, which includes business processes as well. Therefore we can distinguish two basic business system application fields: a) information executive body subsystem, b) information subsystem development. Information subsystem development provides all the necessary data and information required for the adaptation projects carried out by managers and personnel as well as for the business system development. These projects are carried out on the business system and subsystem level. Information system project is an information system aimed at fulfilling information demands of the main system project, of the maintaining system project, as well as of the project system management. These projects are the result of strategies carried out within business systems. They are aimed at transforming strategies into projects, which are then carried out by business systems in a determined period of time. The quick transformation of strategies into projects together with the quick and higher quality performance, give rise to an advantage in business system competition.

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David Theodore, N., Leslie H. Allen, C. Barry Carter, and James W. Mayer. "TEM characterization of Au/Polysilicon interactions." Proceedings, annual meeting, Electron Microscopy Society of America 48, no. 4 (August 1990): 650–51. http://dx.doi.org/10.1017/s0424820100176381.

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Metal/polysilicon investigations contribute to an understanding of issues relevant to the stability of electrical contacts in semiconductor devices. These investigations also contribute to an understanding of Si lateral solid-phase epitactic growth. Metals such as Au, Al and Ag form eutectics with Si. reactions in these metal/polysilicon systems lead to the formation of large-grain silicon. Of these systems, the Al/polysilicon system has been most extensively studied. In this study, the behavior upon thermal annealing of Au/polysilicon bilayers is investigated using cross-section transmission electron microscopy (XTEM). The unique feature of this system is that silicon grain-growth occurs at particularly low temperatures ∽300°C).Gold/polysilicon bilayers were fabricated on thermally oxidized single-crystal silicon substrates. Lowpressure chemical vapor deposition (LPCVD) at 620°C was used to obtain 100 to 400 nm polysilicon films. The surface of the polysilicon was cleaned with a buffered hydrofluoric acid solution. Gold was then thermally evaporated onto the samples.

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Gruca, Olaf, Monika Tysiąc-Miśta, Aleksandra Czelakowska, Patrycja Łanowy, Miłosz Bichalski, Jakub Dzindzio, Jacek Kasperski, and Marlena Biel. "Relationship of temporomandibular disorders with selected systemic diseases." Prosthodontics 69, no. 1 (March 12, 2019): 68–83. http://dx.doi.org/10.5114/ps/105570.

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Fundenberger, Jean-Jacques, Adam Morawiec, and Emmanuel Bouzy. "Advances in Automatic TEM Based Orientation Mapping." Solid State Phenomena 105 (July 2005): 37–42. http://dx.doi.org/10.4028/www.scientific.net/ssp.105.37.

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The paper is an account of TEM based automatic orientation mapping summarizing more than two years of using the system. Following a brief introduction of the system elements, some representative applications are described. We focus on the characterization of fine-grain materials, mapping of low symmetry materials (metastable chromium carbide) and semi-automatic analysis of misorientations in a fully lamellar polycrystalline (g+a2) TiAl alloy. Moreover, the current state of the TEM based system is discussed and compared to EBSD systems. In particular, the issues of spatial resolution, accuracy, map acquisition time, reliability are considered.

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Squillante, Reinaldo, Diolino Jose dos Santos, Fabricio Junqueira, and Paulo Eigi. "Development of Control Systems for Safety Instrumented Systems." IEEE Latin America Transactions 9, no. 4 (July 2011): 451–57. http://dx.doi.org/10.1109/tla.2011.5993727.

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Aksu, H. A., and M. Salehi. "Joint optimization of TCQ-TCM systems." IEEE Transactions on Communications 44, no. 5 (May 1996): 529–33. http://dx.doi.org/10.1109/26.494293.

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Zhang, Zaichen, and Guangguo Bi. "Turbo TCM schemes for WCDMA systems." Electronics Letters 35, no. 22 (1999): 1925. http://dx.doi.org/10.1049/el:19991330.

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