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Journal articles on the topic 'Systolic array circuits'

Author: Grafiati

Published: 4 June 2021

Last updated: 25 January 2023

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1

AL-RABADI, ANAS N. "REVERSIBLE SYSTOLIC ARRAYS: m-ARY BIJECTIVE SINGLE-INSTRUCTION MULTIPLE-DATA (SIMD) ARCHITECTURES AND THEIR QUANTUM CIRCUITS." Journal of Circuits, Systems and Computers 17, no. 04 (2008): 729–71. http://dx.doi.org/10.1142/s0218126608004472.

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New type of m-ary systolic arrays called reversible systolic arrays is introduced in this paper. The m-ary quantum systolic architectures' realizations and computations of the new type of systolic arrays are also introduced. A systolic array is an example of a single-instruction multiple-data (SIMD) machine in which each processing element (PE) performs a single simple operation. Systolic devices provide inexpensive but massive computation power, and are cost-effective, high-performance, and special-purpose systems that have wide range of applications such as in solving several regular and com

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2

Ho, H., V. Szwarc, and T. Kwasniewski. "A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications." International Journal of Reconfigurable Computing 2009 (2009): 1–14. http://dx.doi.org/10.1155/2009/529512.

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A reconfigurable systolic array (RSA) architecture that supports the realization of DSP functions for multicarrier wireless and multirate applications is presented. The RSA consists of coarse-grained processing elements that can be configured as complex DSP functions that are the basic building blocks of Polyphase-FIR filters, phase shifters, DFTs, and Polyphase-DFT circuits. The homogeneous characteristic of the RSA architecture, where each reconfigurable processing element (PE) cell is connected to its nearest neighbors via configurable switch (SW) elements, enables array expansion for paral

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3

Rayudu, Kurada Verra Bhoga Vasantha, Dhananjay Ramachandra Jahagirdar, and Patri Srihari Rao. "Design and testing of systolic array multiplier using fault injecting schemes." Computer Science and Information Technologies 3, no. 1 (2022): 1–9. http://dx.doi.org/10.11591/csit.v3i1.p1-9.

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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low

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4

Yamazaki, Ichitaro, Jakub Kurzak, Piotr Luszczek, and Jack Dongarra. "Design and Implementation of a Large Scale Tree-Based QR Decomposition Using a 3D Virtual Systolic Array and a Lightweight Runtime." Parallel Processing Letters 24, no. 04 (2014): 1442004. http://dx.doi.org/10.1142/s0129626414420043.

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A systolic array provides an alternative computing paradigm to the von Neumann architecture. Though its hardware implementation has failed as a paradigm to design integrated circuits in the past, we are now discovering that the systolic array as a software virtualization layer can lead to an extremely scalable execution paradigm. To demonstrate this scalability, in this paper, we design and implement a 3D virtual systolic array to compute a tile QR decomposition of a tall-and-skinny dense matrix. Our implementation is based on a state-of-the-art algorithm that factorizes a panel based on a tre

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5

Raut, R., B. B. Bhattacharyya, and S. M. Faruque. "A discrete Fourier transform using switched capacitor circuits in systolic array architecture." IEEE Transactions on Circuits and Systems 37, no. 12 (1990): 1578–80. http://dx.doi.org/10.1109/31.101284.

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6

Torralba, A. "A systolic array with applications to image processing and wire-routing in VLSI circuits." Parallel Computing 17, no. 1 (1991): 85–93. http://dx.doi.org/10.1016/s0167-8191(05)80020-1.

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7

Kondapalli, Soumya, Arjuna Madanayake, and Len Bruton. "Digital Architectures for UWB Beamforming Using 2D IIR Spatio-Temporal Frequency-Planar Filters." International Journal of Antennas and Propagation 2012 (2012): 1–19. http://dx.doi.org/10.1155/2012/234263.

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A design method and an FPGA-based prototype implementation of massively parallel systolic-array VLSI architectures for 2nd-order and 3rd-order frequency-planar beam plane-wave filters are proposed. Frequency-planar beamforming enables highly-directional UWB RF beams at low computational complexity compared to digital phased-array feed techniques. The array factors of the proposed realizations are simulated and both high-directional selectivity and UWB performance are demonstrated. The proposed architectures operate using 2's complement finite precision digital arithmetic. The real-time through

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8

ANDONOV, R., P. QUINTON, S. RAJOPADHYE, and D. WILDE. "A SHIFT REGISTER-BASED SYSTOLIC ARRAY FOR THE UNBOUNDED KNAPSACK PROBLEM." Parallel Processing Letters 05, no. 02 (1995): 251–62. http://dx.doi.org/10.1142/s0129626495000230.

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We present a shift register-based systolic array for a class of recurrences, with dynamic dependencies called knapsack problem recurrences. All previous arrays or parallel implementations led to either low efficiency or to complicated control. To the best of our knowledge, the proposed design is the first realistic pure systolic and optimal array for this pseudo-polynomial, NP-hard problem. The key feature of the array is that it requires almost no control circuitry.

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9

Rasoulinezhad, Seyedramin, Esther Roorda, Steve Wilton, Philip H. W. Leong, and David Boland. "Rethinking Embedded Blocks for Machine Learning Applications." ACM Transactions on Reconfigurable Technology and Systems 15, no. 1 (2022): 1–30. http://dx.doi.org/10.1145/3491234.

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The underlying goal of FPGA architecture research is to devise flexible substrates that implement a wide variety of circuits efficiently. Contemporary FPGA architectures have been optimized to support networking, signal processing, and image processing applications through high-precision digital signal processing (DSP) blocks. The recent emergence of machine learning has created a new set of demands characterized by: (1) higher computational density and (2) low precision arithmetic requirements. With the goal of exploring this new design space in a methodical manner, we first propose a problem

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10

Roorda, Esther, Seyedramin Rasoulinezhad, Philip H. W. Leong, and Steven J. E. Wilton. "FPGA Architecture Exploration for DNN Acceleration." ACM Transactions on Reconfigurable Technology and Systems 15, no. 3 (2022): 1–37. http://dx.doi.org/10.1145/3503465.

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Recent years have seen an explosion of machine learning applications implemented on Field-Programmable Gate Arrays (FPGAs) . FPGA vendors and researchers have responded by updating their fabrics to more efficiently implement machine learning accelerators, including innovations such as enhanced Digital Signal Processing (DSP) blocks and hardened systolic arrays. Evaluating architectural proposals is difficult, however, due to the lack of publicly available benchmark circuits. This paper addresses this problem by presenting an open-source benchmark circuit generator that creates realistic DNN-or

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11

H Bailmare, Ravi, S. J. Honale, and Pravin V Kinge. "Design and Implementation of Adaptive FIR filter using Systolic Architecture." International Journal of Reconfigurable and Embedded Systems (IJRES) 3, no. 2 (2014): 54. http://dx.doi.org/10.11591/ijres.v3.i2.pp54-61.

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<p>The tremendous growth of computer and Internet technology wants a data to be process with a high speed and in a powerful manner. In such complex environment, the conventional methods of performing multiplications are not suitable to obtain the perfect solution. To obtain perfect solution parallel computing is use in contradiction. The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. In order to obtain minimum mean square error and updated value of weight vector effectively, systolic architecture

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12

Azimian, Alireza, Ali Kargaran, and Mohammad Tehrani. "A Novel Systolic Array Architecture for Matrix Multiplication Circuit Design using Carbon Nanotube Technology." International Journal of Computer Applications 172, no. 6 (2017): 1–4. http://dx.doi.org/10.5120/ijca2017915156.

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13

ARJUNA MADANAYAKE, H. L. P., R. J. CINTRA, V. S. DIMITROV, and L. T. BRUTON. "BLOCK-PARALLEL SYSTOLIC-ARRAY ARCHITECTURE FOR 2-D NTT-BASED FRAGILE WATERMARK EMBEDDING." Parallel Processing Letters 22, no. 03 (2012): 1250009. http://dx.doi.org/10.1142/s0129626412500090.

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Number-theoretic transforms (NTTs) have been applied in the fragile watermarking of digital images. A block-parallel systolic-array architecture is proposed for watermarking based on the 2-D special Hartley NTT (HNTT). The proposed core employs two 2-D special HNTT hardware cores, each using digital arithmetic over GF(3), and processes 4 × 4 blocks of pixels in parallel every clock cycle. Prototypes are operational on a Xilinx Sx35-10ff668 FPGA device. The maximum estimated throughput of the FPGA circuit is 100 million 4 × 4 HNTT fragile watermarked blocks per second, when clocked at 100 MHz.

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14

Lounici, Mer Wan, and Xiao Ming Luan. "Implementation of Unitary Music Algorithm Using Xilinx System Generator." Advanced Materials Research 748 (August 2013): 629–33. http://dx.doi.org/10.4028/www.scientific.net/amr.748.629.

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The MUltiple SIgnal Classification MUSIC algorithm is a kind of DOA (Direction Of Arrival) estimation technique based on eigenvalue decomposition, which is also called subspace-based method [5]. In addition of its super resolution capability, MUSIC is very suitable for integration on logic circuit devices such as FPGAs (Field Programmable Gate Array).this paper proposes an implementation of unitary MUSIC algorithm using Xilinx System Generator (XSG). The design proposed uses CORDIC (COordinate Rotation DIgital Computer) -based Triangular Systolic Array for QR- decomposition to deal with EVD (e

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15

Hu, Wenjie, Yuxin Zhang, Hongrui Zhang, and Weigang Chen. "Hardware Acceleration of Identifying Barcodes in Multiplexed Nanopore Sequencing." Electronics 11, no. 16 (2022): 2596. http://dx.doi.org/10.3390/electronics11162596.

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In multiplexed sequencing, the identification of DNA sequencing barcodes can effectively reduce the probability of sample misassignment. However, the great quantity of sequence data requires a high-throughput identification method. Therefore, based on a barcode identification scheme combining cyclic shifting with dynamic programming (DP), this paper proposes, implements and tests a hardware accelerator that can accelerate barcode identification. In the accelerator, considering that the computational complexity of the DP algorithm can be expressed as the multiplication of the lengths of both in

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16

Iwamura, Keiichi, Hideki Imai, and Yasunori Dohi. "A method to reduce the circuit scale for systolic arrays and its application to reed-solomon codecs." Electronics and Communications in Japan (Part III: Fundamental Electronic Science) 73, no. 4 (1990): 23–30. http://dx.doi.org/10.1002/ecjc.4430730403.

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17

Li, Anqi, Jianle Lin, Huimin Li, et al. "A robust and flexible pulse wave sensory array enabling real-time non-invasive blood pressure monitoring." Flexible and Printed Electronics 7, no. 1 (2022): 014014. http://dx.doi.org/10.1088/2058-8585/ac5e0d.

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Abstract Chronical cardiovascular decreases such as hypertension requires real-time and continuous monitoring of blood pressures (BPs). Pulse wave that contains critical and ample information on cardiovascular dynamics is a direct vital sign to extract BP and therefore an epidermal wearable device enabling real-time acquisition of pulse waves becomes necessary. In this work, we propose and study a flexible pulse wave sensory array aiming for real-time wearable pulse wave acquisition with robustness. A piezoelectric sensor together with a thin-film transistor-based sensor interface circuit is u

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18

Nash, J. "Distributed-Memory-Based FFT Architecture and FPGA Implementations." Electronics 7, no. 7 (2018): 116. http://dx.doi.org/10.3390/electronics7070116.

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A new class of fast Fourier transform (FFT) architecture, based on the use of distributed memories, is proposed for field-programmable gate arrays (FPGAs). Prominent features are high clock speeds, programmability, reduced look-up-table (LUT) and register usage, simplicity of design, and a capability to do both power-of-two and non-power-of-two FFTs. Higher clock speeds are a consequence of new algorithms and a more fine-grained structure compared to traditional pipelined FFTs, so clock speeds are typically >500 MHz in 65 nm FPGA technology. The programmability derives from the memory-based

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19

Mathe, Sudha Ellison, and Lakshmi Boppana. "Design and Implementation of a Novel Bit-Parallel Systolic Multiplier Over GF(2m) for Irreducible Pentanomials." Journal of Circuits, Systems and Computers 27, no. 14 (2018): 1850228. http://dx.doi.org/10.1142/s0218126618502286.

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Cryptography in current digital world offers integrity and confidentiality of data being transferred over a communication network. Modern cryptography provides such security through cryptographic algorithms which mainly involve multiplication operation in finite fields. Since the finite field multiplication operation is a computationally intensive operation, various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. In this paper, a modified interleaved multiplication algorithm to perform multiplication of

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