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Relevant bibliographies by topics / Tanner EDA tool write access time and retention time

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Academic literature on the topic 'Tanner EDA tool write access time and retention time'

Author: Grafiati

Published: 3 June 2025

Last updated: 31 July 2025

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Journal articles on the topic "Tanner EDA tool write access time and retention time"

1

Vamsi, J. "Implementation of a 4T DRAM element for faster digital system applications." International Journal of Advanced Research in Science and Technology, 2015, 481–84. http://dx.doi.org/10.62226/ijarst20150534.

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This paper deals with analysis of average power consumption of dram cell designs for the nanometer scale memories. These DRAMs are used in many modern processors’ internal memory. The major contributor of power in dram is the off state leakage current. Improving the power efficiency of a dram cell is critical for the improvement in average power consumption of the overall system. 3T dram cell, 4T dram cells are designed by using TANNER EDA tool and their average power consumption are compared. Average power consumption, write access time, read access time and retention time of 4T, 3T DRAM cell

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2

Nawang, Chhunid, and Kumar Gagnesh. "Analysis of Performance of 3T1D Dynamic Random-Access Memory Cell." April 15, 2016. https://doi.org/10.5281/zenodo.1125567.

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On-chip memories consume a significant portion of the overall die space and power in modern microprocessors. On-chip caches depend on Static Random-Access Memory (SRAM) cells and scaling of technology occurring as per Moore's law. Unfortunately, the scaling is affecting stability, performance, and leakage power which will become major problems for future SRAMs in aggressive nanoscale technologies due to increasing device mismatch and variations. 3T1D Dynamic Random-Access Memory (DRAM) cell is a non-destructive read DRAM cell with three transistors and a gated diode. In 3T1D DRAM cell gated di

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3

"A Gated Diode DRAM Cell for Improved Power and Speed." International Journal of Innovative Technology and Exploring Engineering 8, no. 9 (2019): 3029–33. http://dx.doi.org/10.35940/ijitee.i8091.078919.

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In this paper performance analysis of Gated diode based Dynamic Random Access Memory (GD-DRAM) cell is compare with capacitor based DRAM cell in terms of average power dissipation, propagation delay, read access time and write access time at 250nm technology. The GD-DRAM is also referred as capacitorless DRAM. This gated diode stored data in DRAM which is an alternative solution to capacitor. This gated diode DRAM shows cutback in leakage and access time as compared to capacitor based DRAM. A gated diode is formed by shorting two terminal of MOS transistor i.e. source and drain. When the volta

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4

Praveen, Pushkar, and R. K. Singh. "Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-Threshold Leakage Current with14nm FinFET Technology." ACM Transactions on Design Automation of Electronic Systems, August 24, 2023. http://dx.doi.org/10.1145/3616538.

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Power dissipation is considered one of the important issues in low power Very-large-scale integration (VLSI) circuit design, and is related to the threshold voltage. Generally, the sub-threshold leakage current and the leakage power dissipation are increased by reducing the threshold voltage. The overall performance of the circuit completely depends on this leakage power dissipation. Because this leakage and power consumption causes the components that are functioning by the battery for a long period to washed-out rapidly. In this research, the reversible logic gate-based 9T static random acce

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5

Praveen, Pushkar, and Rakesh Kumar Singh. "Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology." International Journal of Circuit Theory and Applications, June 27, 2024. http://dx.doi.org/10.1002/cta.4143.

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AbstractThe excessive power usage in modern digital equipment is triggered by memory arrays, mainly including Static Random‐Access Memory (SRAM) chips. Many scientists are working to create an SRAM cell that is fast, highly stable, and uses little power. However, the traditional SRAM cells have instability and read/write failure at scaled technology nodes. This study proposes a Differential Power Schmitt‐Trigger Logic 9 Tcompute SRAM (DPSTL‐9 TCSRAM) cell design with high read‐and‐write stability and low energy consumption. In SRAM cells, the sensing amplifier (SA), pre‐charge circuit, row dec

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