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Journal articles on the topic 'Tanner EDA'

Author: Grafiati

Published: 4 June 2025

Last updated: 15 July 2025

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V.P, Visanthi. "FULL ADDER CIRCUIT DESIGN WITH LOW POWER AND HIGH SPEED AT 0.25µM CMOS TECHNOLOGY USING TANNER EDA." International Journal Of Trendy Research In Engineering And Technology 07, no. 01 (2023): 46–48. http://dx.doi.org/10.54473/ijtret.2023.7109.

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A CMOS Full Adder is designed using Tanner EDA Tool based on 0.25µm CMOS Technology. In the arithmetic logic unit (ALU), the full adder cell is one of the most frequently utilized digital circuit components and the fundamental functional unit of all computational circuits. Right now, a lot of work has been done to improve the architecture and functionality of full adder circuit designs. In this research, two innovative 1-bit full adder cell designs are developed using ten transistors and 0.25mm CMOS technology (10-T). Tanner software tools will be used in the design of the CMOS full adder to simulate the schematic and layout as well as compare the schematic and layout for the purpose of determining precise design limitations. As part of this, we are going to perform the simulation of the CMOS full adder using T-SPICE of Tanner EDA and its layout design using the Microwind tool. The parameters such as power consumption, Area, Propagation Delay, and Power Delay Product (PDP) are evaluated to analyze the proposed one-bit full adder

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Alexander, S. "Design and Implementation of Efficient Reversible Multiplier Using Tanner EDA." International Journal of MC Square Scientific Research 5, no. 1 (2013): 15–22. http://dx.doi.org/10.20894/ijmsr.117.005.001.003.

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Vyas, Keerti, Ginni Jain, Vijendra K. Maurya, and Rajeev Mathur. "Illustrative Comparison of MCML and CMOS Design Techniques using Tanner EDA." International Journal of Computer Applications 118, no. 4 (2015): 18–21. http://dx.doi.org/10.5120/20734-3110.

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Singh, Pratiman, and Dr Prashant K.Shah. "Design of Power Gated True Single-Phase-Clocked Flip-Flop." International Journal of Research in Science and Technology 12, no. 03 (2022): 05–10. http://dx.doi.org/10.37648/ijrst.v12i03.002.

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In low-voltage functions, power optimization is critical. This paper shows how to make a low-power Data -Flip flop circuit with header power gating. The architecture's main purpose is to investigate D Flip flop power dissipation in the conceptual design style. Tanner EDA is used to carry out the planned design. The simulation results reveal that using power gating, our suggested cell consumes significantly less energy.

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Rajasekar, B., and K. Ashokkumar. "Low Power 4×4 Bit Multiplier Design Using DADDA, WALLACE Algorithm and Gate Diffusion Input Technology Kotha Vinil Kumar Reddy, Kondamuri Venkata Bala Manikanta Abhinav,." Journal of Computational and Theoretical Nanoscience 16, no. 8 (2019): 3359–66. http://dx.doi.org/10.1166/jctn.2019.8220.

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We designed two different multipliers in order to reduce the power consumption, propagation delay and also area occupied by the multiplier. Previously there is a multiplier using DADDA algorithm that consumes high power and propagation delay also more in order to overcome that problems we designed multiplier using WALLACE algorithm. This multiplier can overcome those drawbacks. For more efficient multiplier we used GDI (Gate Diffusion Input) technology used along with the WALLACE algorithm. This model has been designed using Tanner EDA tool.

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Ms. Amruta Bijwar. "CMRR Boosted Instrumentation Amplifier for Biomedical Application." International Journal of New Practices in Management and Engineering 2, no. 04 (2013): 01–06. http://dx.doi.org/10.17762/ijnpme.v2i04.21.

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This research paper discusses about a design of an amplifier for its use in an Analog Front End for Biomedical signal acquisition. The design of an AFE is also specific to the signal of interest. This paper deals with the design of an Analog Front End using 180nm process. An amplifier is a key component of an AFE. For instrumentation amplifier to satisfy theoretical results the OPAMP used must be close to ideal. The simulations are performed using TANNER EDA tool.

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Siva, Chakra Avinash., Bikkina, and Nekkanti.Mouni. "Design and Implementation of Braun Multiplier using Parallel Prefix Adders." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 4 (2020): 1251–54. https://doi.org/10.35940/ijeat.D8075.049420.

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In the recent trends of any application depends on delay and area consumption. The delay and area of consumption are the two important considerations of the industrial. These two parameters are considered for any industry application. This type of application can be developed by the different methods that are used in VLSI technology. The Braun multiplier was developed by two different methods. The CMOS and GDI methods are used to implement this multiplier. The parallel prefix adders are used in the multiplier. Braun multiplier is helpful for increasing the speed of the system. The Braun multiplier is designed in the Tanner V-13 EDA tool. The results of this type of multiplier were considered in both CMOS and GDI.

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Gyawali, Yadu Prasad, and Mohit Angurala. "Design of Frequency Divider (FD/2 and FD 2/3) Circuits for a Phase Locked Loop." International Journal on Future Revolution in Computer Science & Communication Engineering 8, no. 1 (2022): 27–31. http://dx.doi.org/10.17762/ijfrcsce.v8i1.2103.

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This paper reports on three design of Frequency Divider (FD/2) and Frequency Divider (FD 2/3) circuits. Tanner EDA tool developed on 130nm CMOS technology with a voltage supply of 1.3 V is used to build, model, and compare all circuits. For the FD/2 circuit, E-TSPC Pass Transistor logic uses 1.77 µW, whereas TSPC logic consumes 5.57 µW for the FD 2/3 circuit. It implies that the TSPC logic is the best solution since it meets the speed and power consumption requirements.

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K.G, Dharani. "Design of Low Power and Area Efficient 8 Bit USR Using mGDI Technology." International Journal of Computer Communication and Informatics 3, no. 2 (2021): 25–34. http://dx.doi.org/10.34256/ijcci2123.

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Technology is growing at a faster rate after the evolution of VLSI, which mainly focuses on three major criteria-speed, area and power. All these criteria determine the compactness of a product in order to produce an efficient output at a higher rate by consuming less power. To achieve the above-mentioned factors, an efficient 8-bit Universal Shift Register (USR) has been designed using modified Gate Diffusion Input (mGDI) technique. The results have been simulated using the TANNER EDA tool and found to contribute for low power and area.

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Prof. Shweta Jain. "Design and Analysis of Low Power Hybrid Braun Multiplier using Ladner Fischer Adder." International Journal of New Practices in Management and Engineering 6, no. 03 (2017): 07–12. http://dx.doi.org/10.17762/ijnpme.v6i03.59.

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Multiplier is important in many DSP systems and in many hardware blocks. Multiplier are used in various DSP application like digital filtering, digital communication. This needs parallel array multiplier to attain high speed for execution and better performance. A specific array multiplier is implemented known as Braun design. Braun multiplier is the one which is a kind of parallel multiplier. It contains different CSA count of AND gates. Braun multiplier employing Ripple Carry Adder is developed here having high speed PPA. It will reduce the delay and implemented using Tanner EDA tool.

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Singh, Shiwani, Tripti Sharma, K. G. Sharma, and B. P. Singh. "9T Full Adder Design in Subthreshold Region." VLSI Design 2012 (March 11, 2012): 1–5. http://dx.doi.org/10.1155/2012/248347.

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This paper presents prelayout simulations of two existing 9T and new proposed 9T full adder circuit in subthreshold region to employ in ultralow-power applications. The proposed circuit consists of a new logic which is used to implement Sum module. The proposed design remarkably reduces power-delay product (PDP) and improves temperature sustainability when compared with existing 9T adders. Therefore, in a nut shell proposed adder cell outperforms the existing adders in subthreshold region and proves to be a viable option for ultralow-power and energy-efficient applications. All simulations are performed on 45 nm standard model on Tanner EDA tool version 13.0.

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SIVAKUMAR, S., JUTURU LAKSHMI, RAMANNAGARI KEERTHANA, and K. BHARATH. "HIGH SPEED AND AREA-EFFECTIVE VLSI ARCHITECTURE OF THREE- OPERAND ADDER USING TANNER EDA TOO." International Journal of Advanced Trends in Engineering Science and Technology 6, no. 3 (2021): 5–15. http://dx.doi.org/10.22413/ijatest/2021/v6/i3/4.

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S, Amulya. "Low Power, High Performance PMOS Biased Sense Amplifier." International Journal for Research in Applied Science and Engineering Technology 10, no. 7 (2022): 1763–69. http://dx.doi.org/10.22214/ijraset.2022.45257.

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Abstract: The capacity, functionality, dependability, and durability of the memory sense circuits in the basic cell are all significantly impacted by sense amplifiers in the proposed experiment. We will create two novel circuits that have been suggested in this presentation. This project's suggested circuit is a PMOS biassed sense amplifier with a basic cell that has a high output impedance and reduces the circuit's sensing latency as well as its power dissipation. As a result, the developed circuit executes operations similarly to those of parallel circuits, reducing the sense latency and circuit power consumption. The performance of one of the recommended sense amplifiers may then be verified by simulation utilizing Tanner EDA and CTSA and 180nm technology, leading to a sense decoder employing advanced technology in the technique.

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Adhikari, Manoj Singh, Shaik Sahil, Palatla Babasri Tarun Naidu, Aseervadam Thushar Roy, Mandapati Devendra, and Uppala Goutham. "Power Efficient Technique for CMOS- Logic Circuits." Journal of Physics: Conference Series 2327, no. 1 (2022): 012015. http://dx.doi.org/10.1088/1742-6596/2327/1/012015.

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Abstract Power outages on normal CMOS circuit is very high it can be reduced by using the adiabatic technique. Adiabatic technique is used in the pull up part of CMOS logic. Power loss of CMOS Logic is in terms of heat. Adiabatic is an efficient technique where some of the energy stored in the load and it is used for next inputs without dissipating as heat. The adiabatic technique depends largely on the parameter variation. With the help of DSCH, MICROWIND, TANNER EDA (S-edit, TWV, TSP) Software’s power consumed by ECRL (Efficient Charge Recovery Logic) is compared to the power consumed by common CMOS for NAND and NOR inverter circuits. In this study it is find out that the adiabatic technique is the good choice rather than conventional technique in terms of power consumption.

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L, Saranya, Abinaya Inbamani, Nivedita A, and Arulanantham D. "Power Reduction in 4T DRAM Cell Using Low Power Topologies." ECS Transactions 107, no. 1 (2022): 5569–75. http://dx.doi.org/10.1149/10701.5569ecst.

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In today’s world there is a high demand in the development of VLSI circuits. The designers are paying attention to designing a good performance with zero hunger circuits in terms of power. At present, to design a high speed and a low cost device is becoming a major challenge for designers. In order to enlarge the demand of VLSI, CMOS technology plays a fundamental role. Dynamic Random Access Memory is the volatile memory, which is used in wide ranges of electronic based gadget applications. In this paper, the low power techniques like sleep transistor logic and Self Voltage Controllable Logic (SCVL) are implemented. A 4T DRAM cell using these low power logics has been designed and implemented. The power has been analyzed at 90nm technology. The simulation is done using the Tanner 13.1.EDA tool.

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Rahul Pal. "Novel low PDP CMOS Double-Base Multiplier." Journal of Electrical Systems 20, no. 3 (2024): 6207–15. https://doi.org/10.52783/jes.6683.

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Multipliers play a vital role on digital low power communication system. This present study introduced a new novel strategy of multiplication that can improve speed-power efficiency with a double-based number system multiplier. Designing with a Double base number system multiplier is a suitable alternation due to its two important properties redundancy & sharpness. Extensive simulations has been done to examine the competency of proposed designs under three different test conditions to test . It then compares some of the critical parameters with excising single base number system (i.e. Binary number system) & Multi-value number system (i.e. Ternary Number system). All the design optimization & evaluations performed are based on the BSIM4 device parameter of TSMC 0.18µm CMOS technology with 0.9V supply at 27oC temperature using S. Edit of Tanner EDA..

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G., Naveen Balaji, Karthikeyan S., and Merlin Asha M. "0.18µm CMOS Comparator for High Speed Applications." International Journal of Trend in Scientific Research and Development 1, no. 5 (2017): 671–74. https://doi.org/10.31142/ijtsrd2356.

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In the electronics industry the Low Power Comparator using High Speed in Analog to Digital Converters. In electronic device Comparator are mostly used in Analog to Digital converter ADC . In ADC are used for the delay produced and power consumed by an ADC. I design a 0.18µm CMOS Comparator for High Speed Application. The advantage of programmable hysteresis to the comparators are also discussed. Tanner EDA is used for the design and simulation for the comparator circuits The difference between the proposed comparator to the existing double tail comparator result are produced. G. Naveen Balaji | S. Karthikeyan | M. Merlin Asha "0.18µm CMOS Comparator for High-Speed Applications" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-1 | Issue-5 , August 2017, URL: https://www.ijtsrd.com/papers/ijtsrd2356.pdf

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Diksha Siddhamshittiwar. "An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique." International Journal of New Practices in Management and Engineering 6, no. 02 (2017): 07–12. http://dx.doi.org/10.17762/ijnpme.v6i02.57.

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Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

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N, Indu, Damodhar Rao M, and Prasad V. V. K. D. V. "High Speed Power Efficient Dynamic Comparator with Low Power Dissipation and Low Offset." Metallurgical and Materials Engineering 31, no. 3 (2025): 112–18. https://doi.org/10.63278/1332.

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When designing digital circuits with high speeds, dynamic comparators are necessary. In particular, central processing units (CPUs) in a wide variety of electronic devices rely on low-power, high-speed dynamic comparators. Numerous comparators, which are comparison circuits, make up these central processing units. This research article introduces a low-voltage, low-power Double Tail Dynamic Comparator (DTDC) that uses less power than previous designs. This journal article compares and contrasts the suggested design with several kinds of dynamic comparators. The suggested architecture is contrasted with dynamic comparators that rely on techniques such as regenerative latch, floating inverter amplifier, and Double Tail. The Tanner EDA simulation program is used to model this design using 18nm technology. This suggested design use the self-biasing approach to execute the pre-amplification process. This suggested design operates with less kick back noise thanks to the self-biasing mechanism.

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Hari Kishore, K., K. DurgaKoteswara Rao, G. Manvith, K. Biswanth, and P. Alekhya. "Area, power and delay efficient 2-bit magnitude comparator using modified gdi technique in tanner 180nm technology." International Journal of Engineering & Technology 7, no. 2.8 (2018): 222. http://dx.doi.org/10.14419/ijet.v7i2.8.10413.

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Of late, low power configuration took shape into the mostimportant concentrations in designing the latest VLSI circuits. By considering the same at the maximum priority, another outline of two-bit GDI based Magnitude or Digital Comparator are recommended and actualized with the assistance of Modified GDI transistors. Comparators are building blocks in advanced VLSI configuration circuits. In the current patterns the necessity for occupying less area in chip and low power compact devices. In this paper we introduced another Magnitude Comparator which willutilize low power, and gives a quick results and occupying less chip area in Modified GDI technology. The modified GDI procedure dependent extent comparator has favorable position of less control utilization as for different outline parameters; few on-chip zones secured as small number of transistors are utilized in circuit configuration when related with traditional CMOS size comparator. Either of the circuits is outlined and executed utilizing Tanner EDA Tool version 16.0 at 180nm processing technologies.

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Bolaños-Pérez, Ricardo, José Miguel Rocha-Pérez, Alejandro Díaz-Sánchez, Jaime Ramirez-Angulo, and Esteban Tlelo-Cuautle. "CMOS Analog AGC for Biomedical Applications." Electronics 9, no. 5 (2020): 878. http://dx.doi.org/10.3390/electronics9050878.

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In this paper, we present the design of an analog Automatic Gain Control with a small silicon area and reduced power consumption using a 0.5 μ m process. The design uses a classical approach implementing the AGC system with simple blocks, such as: peak detector, difference amplifier, four-quadrant multiplier, and inversor amplifier. Those blocks were realized by using a modified Miller type OPAMP, which allows indirect compensation, while the peak detector uses a MOS diode. The AGC design is simulated using the Tanner-Eda environment and Berkeley models BSIM49 of the On-Semiconductor C5 process, and it was fabricated through the MOSIS prototyping service. The AGC system has an operation frequency of around 1 kHz, covering the range of biomedical applications, power consumption of 200 μ W, and the design occupies a silicon area of approximately 508.8 μ m × 317.7 μ m. According to the characteristics obtained at the experimental level (attack and release time), this AGC can be applied to hearing aid systems.

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Gupta, Akhlesh, and Ashwani K. Rana. "Comparative Analysis of Single-Phase-Clocked Low Power Flip-Flops with Transmission-Gate Flip-Flop." Journal of Physics: Conference Series 2325, no. 1 (2022): 012015. http://dx.doi.org/10.1088/1742-6596/2325/1/012015.

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Abstract Flip-flops are fundamental building block in designing the digital circuits. They contribute significant amount of power consumption in the digital systems. In the modern era of VLSI design, power consumption has become crucial factor. As the technology is scaled down below 65nm, leakage power contributes significantly to overall power consumption of digital circuits. Since, Flip-flop is a fundamental building block in designing digital systems, reducing the power consumption of Flip-flop is required to achieve low power consumption of digital systems. Recently single-phase clocking technique has been employed in designing FFs to achieve low power consumption. This technique reduces excess loading on the clock signal. In this article performance of recent single-phase clocked FFs is compared with the conventional transmission-gate Flip-flop. Also, drawbacks of these FFs are discussed. For the comparison of performance of single-phase-clocked FFs with conventional transmission-gate FF, all the simulations are performed at 45-nm predictive technology on Tanner EDA tool.

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Gautam, Anil Kumar. "Bulk Cum QFG-Driven FVF Double Recycling Current Mirror Subthreshold OTA Based CCII+ Cell and Applications." International Journal of Electrical and Electronic Engineering & Telecommunications 13, no. 6 (2024): 467–77. http://dx.doi.org/10.18178/ijeetc.13.6.467-477.

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This paper presents a low-voltage low-power second generation CCII+ cell using bulk-driven FVF class AB mode operated double recycling current mirror OTA. The OTA is used in the input core of CCII+ cell utilizes bulkcum Quasi Floating Gate (QFG)-based voltage to current converter and Partial Positive Feedback (PPF) to enhance the performance of the circuit. The circuit permits closely railto- rail input common mode range, high output current drive capability with low dual power supply of ± 0.25 V. This circuit produces low input referred noise of 1.65 μV/sqrt Hz, dissipates ultra-low power of 342 nW and is suitable for lowfrequency applications, such as bio-signal processing. Further, to validate this design, a MISO type voltage mode biquadratic filter and voltage mode two phase quadrature oscillator are currently being implemented using this CCII+ cells. The circuit is simulated in tanner EDA tools using 180 nm n-tub CMOS process technology with low bias current of 18 nA.

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Prasad, S. Bhanu Venkata, and Dr G. Sujatha. "Low-Power Retentive True Single Phase Clocked(TSPC) D-Flip-Flop with Redundant Precharge Free Operation." International Journal for Research in Applied Science and Engineering Technology 12, no. 12 (2024): 1534–39. https://doi.org/10.22214/ijraset.2024.66075.

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Abstract: In this paper, optimizing power consumption of flip-flops (FFs) can significantly reduce the power of digital systems. In this article, an energy-efficient retentive true single- phase-clocked (TSPC) FF is proposed. With the employment of inputaware precharge scheme, the proposed TSPC FF precharges only when necessary. In addition, floating node analysis and transistor level optimization are employed to further ensure the high energy efficiency of the FF without significantly increasing the area. As The proposed Low power Retentive TSPC FF consumes less power which can be used in application like PLL (phased Lock loop) The main objective of a PLL is to generate a signal in which the phase is the same as the phase of a reference signal. The main Block For this is To design Phase frequency Circuit, Which is designed by using Low power Retentive TSPC FF To Give the better Results compare to conventional Circuit with a power Supply of 1.2 V by using Tanner EDA Tool

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Jhansi, Levaku. "Low-Power Retentive True Single Phase Clocked (TSPC) D-Flip-Flop with Redundant Precharge Free Operation." International Journal for Research in Applied Science and Engineering Technology 12, no. 9 (2024): 133–38. http://dx.doi.org/10.22214/ijraset.2024.64149.

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In this paper, optimizing power consumption of flip-flops (FFs) can significantly reduce the power of digital systems. In this article, an energy-efficient retentive true single- phase-clocked (TSPC) FF is proposed. With the employment of inputaware precharge scheme, the proposed TSPC FF precharges only when necessary. In addition, floating node analysis and transistor level optimization are employed to further ensure the high energy efficiency of the FF without significantly increasing the area. As The proposed Low power Retentive TSPC FF consumes less power which can be used in application like PLL (phased Lock loop )The main objective of a PLL is to generate a signal in which the phase is the same as the phase of a reference signal. The main Block For this is To design Phase frequency Circuit, Which is designed by using Low power Retentive TSPC FF To Give the better Results compare to conventional Circuit with a power Supply of 1.2 V by using Tanner EDA Tool

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Navya, Galla, K. Jamal, Hima Bindu Valiveti, Jitendra Kumar Gupta, and B. Vandana. "Implementation of three stage comparator using a modified latch with sustainable resources." E3S Web of Conferences 430 (2023): 01012. http://dx.doi.org/10.1051/e3sconf/202343001012.

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In this paper, the current study uses a lector technique to modify the latch. The Lector approach is one of the top low-power methods for IC technologies. The locking mechanism is the third stage in our proposed design for a three-stage comparator. The lector approach is used for the three-stage comparator circuit in this case and its modified version. Pre-amplifier stages are the first two levels. The improved performance of this comparator circuit uses two sets of complementary biased two-stage preamplifiers. The traditional three-stage amplifier decreased the latency, while the modified version of the modified three-stage amplifier focused on the kickback noise. The proposed design of this three-stage comparator, which employs a lector approach, concentrates mainly on lower consumption. Tanner EDA was used to build and simulate this complete schematic. Materials having a lesser environmental effect are chosen, such as those that use fewer resources or are simpler to recycle after a product’s lifespan and sustainability.

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Vidhyia, M. "Reordering of Test Vectors Using Weighting Factor Based on Average Power for Test Power Minimization." Asian Journal of Electrical Sciences 4, no. 2 (2015): 10–15. http://dx.doi.org/10.51983/ajes-2015.4.2.1950.

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Power consumption is one of the biggest challenges in high performance VLSI design and testing. Low power VLSI circuits dissipate more power during testing when compared with that of normal operation. Dynamic power has been the dominant part of power dissipation in CMOS circuits; however, in future technologies the static portion of power dissipation will outreach the dynamic portion. The proposed approach is based on a reordering of test vectors in the test sequence to minimize the switching activity of the circuit using test application. In this paper weighted switching activity is derived based on the average power consumed in the logic gates during all possible event conditions. Since this weighted switching activity is based on the power, which gives more accurate results. The proposed algorithm is implemented and verified using ISCAS85 benchmark circuits. Power is estimated for the circuits using Tanner EDA tool. The results show that power is reduced significantly over the existing methods

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G., Hemanth Kumar, Gopi K., Gowtham P., and Naveen Balaji G. "Area Efficient Full Subtractor Based on Static 125nm CMOS Technology." International Journal of Trend in Scientific Research and Development 2, no. 6 (2018): 1371–74. https://doi.org/10.31142/ijtsrd18860.

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A combinational logic circuit is said to be independent of time since it gives the results based on present input not past input. This research is concerned about the comparison between currently existing full subtractor IC and the subtractor which is built efficiently in the 125nm and observing the distortion and changes caused in the result of both full subtractor. The behaviour of the efficient full subtractor is designed using tanner eda tools which was useful and the currently existing full subtractor is designed using xilnx software and lastly the layout for this research is designed with the help of multisim. With help of this research many newly created circuits can designed much more smaller. G. Hemanth Kumar | K. Gopi | P. Gowtham | G. Naveen Balaji "Area Efficient Full Subtractor Based on Static 125nm CMOS Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-6 , October 2018, URL: https://www.ijtsrd.com/papers/ijtsrd18860.pdf

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B.Paulchamy, K.Kalpana, and J.Jaya. "An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 2605–11. https://doi.org/10.35940/ijeat.C5311.029320.

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Multiplies is an important component in Digital Signal Processing (DSP) and communication systems. It is utilized in signal and image processing applications including convolution, Fast Fourier Transform (FFT) and correlation. Therefore, it is necessary to develop a multiplier with power efficient and speed to reduce the cost of the system. Vedic multiplier has been introduced to solve the problems of existing multiplier. It is based on 16 algorithms. These algorithms use algebra, arithmetic operations and geometry. Urdhva Tiryabhyam is widely employed formula which provides high speed and efficient. Vedic multiplies generates partial sums and products in single step. It has been designed using pass transistor logic which reduces the number of components utilized to build logic gates by removing unwanted transistors. This paper design a vedic multiplier with FinFET based pass transistor logic. The developed multiplies provides better performance and suitable for high speed applications. 2x2 and 4x4 vedic multipliers are developed and executed 180nm approach with Tanner EDA Tool 3.0.

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Zaidi, Muhaned. "Low-voltage Low-power Bulk-driven CMOS Op-Amp Using Negative Miller Compensation for ECG." Journal of Engineering and Technological Sciences 54, no. 5 (2022): 220510. http://dx.doi.org/10.5614/j.eng.technol.sci.2022.54.5.10.

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Two bulk-driven CMOS (Complementary Metal Oxide Semiconductor) operational amplifier (op-amp) designs for electrocardiogram (ECG) application are presented and compared in this paper. Both op-amps are based on two-stage amplification, where bulk-driven differential input is the first stage, while additional DC gain is the second stage. Different compensation techniques were integrated in each op-amp design. Standard Miller compensation was used for the first op-amp parallel with the second stage. The novelty of the second op-amp is that it utilizes negative Miller compensation between the bulk-driven input node and the output node of the first stag, while standard Miller compensation was used in the second stage. The purpose of this work was to compare DC gain, phase margin (PM) and unit gain frequency (UGF) obtained through different simulated compensation strategies and test results. The op-amps were simulated using 0.25 μm CMOS technology. The simulation results are presented using the standard model libraries from Tanner EDA tools, operating on a single rail +0.8V power supply.

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Saha, Aloke, Sushil Kumar, Debajit Das та Mrinmoy Chakraborty. "LP-HS Logic Evaluation on TSMC 0.18μm CMOS Technology". International Journal of High Speed Electronics and Systems 26, № 04 (2017): 1740024. http://dx.doi.org/10.1142/s0129156417400249.

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Present paper analyses different aspects of “Low Power-High Speed” (LP-HS) logic in favour of present day ULSI system focus. At first, the speed-power efficiency of LP-HS logic is investigated by designing some basic digital building blocks like Buffer, OR, AND, XOR etc. Next, the Voltage Transfer Characteristics (VTC), Noise Margin (NM) and the temperature effect on logic threshold with respect to LP-HS Buffer circuit are examined. The robustness and reliability of LP-HS Logic has been measured in terms of corner analysis with TT (Typical), FF (Fastest) and SS (Slowest) PVT (Process Voltage Temperature) variations on LP-HS XOR circuit. The worst case delay and PDP variation is recorded. Finally the 8:1 Multiplexer is designed, optimized and evaluated based on LP-HS Logic. The evaluated results are compared with some recent competitive designs to benchmark. To resolve reliability issue the corner analysis with PVT variation has been performed on designed 8:1 Multiplexor circuit. All the simulations are done on TSMC 0.18μm CMOS technology using Tanner EDA V.13 at 25°C temperature with 1.8V supply rail.

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Dhanalakshmi, B., A. Shireesha, A. Ramya, T. Bharath Simha Reddy, G. Krishna Kishore, and Dr V. Madhurima. "High Speed and Area Efficient Scalable n-Bit Digital Comparator." International Journal for Research in Applied Science and Engineering Technology 12, no. 1 (2024): 1327–35. http://dx.doi.org/10.22214/ijraset.2024.58147.

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Abstract: The digital comparator is a crucial design element in various applications, including scientific computations. It is optimized for general-purpose computer architecture, memory addressing logic, queue buffers, and test circuits. High-speed comparators are essential for arithmetic operations, data sorting, and decision-making processes in digital systems. Area efficiency is crucial in integrated circuit design, as it minimizes the physical space a comparator occupies on a chip, reducing manufacturing costs and optimizing performance. The term "scalable" means the comparator can be adapted to handle different word lengths (n-bit), making it versatile for various applications. This project proposes an area-efficient n-bit digital comparator with high operating speed and low-power dissipation. The comparator structure consists of two modules: the Comparison Evaluation Module (CEM) and the Final Module (FM). The CEM involves the regular structure of repeated logic cells used for parallel prefix tree structure, while the FM validates the final comparison based on results from the CEM. The design is implemented using Tanner EDA in 45nm technology

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Seema, Chouhan* R.B.Gayakwad. "NEW ACTIVE BODY BIASED DOIND-ABC2 FOR HIGH SPEED DOMINO LOGIC AT 70NM NODE TECHNOLOGY." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 4 (2017): 203–9. https://doi.org/10.5281/zenodo.557150.

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In the resent VLSI technology high speed devices are used in much application, such as dynamic logic circuits because it is give the best performances over the static device due to less delay, less noise immunity and low power dissipation. Increase Leakage current combine with noise immunity it degrade the performance of dynamic logic circuit. In this paper body biased DOIND-ABC2 (DOIND-2) logic is proposed to reduce the leakage current with less delay penalty. In this paper different Active body biased technique for DOIND logic approach namely DOIND-2(ABC-2) has been used to analyze different parameters Proposed DOIND-2 approach has maximum 70% improvement in leakage current among Domino, DOIND and DOIND-1 proposed technique as compare to domino logic circuit. Proposed DOIND-2 approach also has improvement in most of parameter as compare to all other approaches .In this paper effect of frequency variation in different circuits has been analyzed. All the parameter has been performed at 70 nm technology node using tanner EDA tool with supply voltage 0.9v.

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Yin, Wan-Jun, Tao Wen, and Wei Zhang. "Design of Dynamic Random Access Memory Based on One Transistor One Diode Memory Cell." Journal of Nanoelectronics and Optoelectronics 16, no. 1 (2021): 114–18. http://dx.doi.org/10.1166/jno.2021.2924.

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This paper presents the design analysis of Dynamic Random Access Memory (DRAM) with one transistor one diode (1T1D). The proposed structure consists of one transistor and one voltage controlled diode capacitor. The word and bit lines are connected with two voltage sources for the write operation. The source and drain of the NMOS is tied together to form the diode structure. The off-state leakage current is the main cause for the power dissipation of DRAM. Thus the improvement of power efficiency to the overall system is a critical task. The conventional DRAM cell contains one capacitor and one transistor. But the absence of capacitor in the proposed work is advantageous by means of compatibility, scalability, fabrication complexity, and cost. Tanner EDA working platform of 7 nm technology is used for the implementation of 1T1D DRAM cell in proposed work. This work achieve the power dissipation, read and write access time in the range of 2.647 mW, 0.04 μs and 0.021 μs respectively. Also, the parameter comparison is performed by changing the technologies from 10 nm to 20 nm for 1T1D DRAM cell design.

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Kassa, Sankit, Neeraj Misra, and Rajendra Nagaria. "Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing." Facta universitatis - series: Electronics and Energetics 34, no. 2 (2021): 259–80. http://dx.doi.org/10.2298/fuee2102259k.

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Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.

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Sandhya, Kalla. "Design and High Performance Evaluation of a Low Power Bit-Line SRAM PMOS Biased Sense Amplifier." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 06 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem36033.

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Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

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Faseehuddin, Mohammad, Jahariah Sampe, Sadia Shireen, and Sawal Hamid Md Ali. "Minimum Component All Pass Filters Using a New Versatile Active Element." Journal of Circuits, Systems and Computers 29, no. 05 (2019): 2050078. http://dx.doi.org/10.1142/s0218126620500784.

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In this paper, a new active element namely Dual-X current conveyor differential input transconductance amplifier (DXCCDITA) is proposed. The DXCCDITA is utilized in designing four minimum component fully cascadable all pass filter (APF) structures. The designed all pass filters require only single active element and one/two passive elements for realization thus making them a minimum component implementation. Two among the four presented all pass structures require only a single capacitor for implementation. A scheme for realizing nth order all pass filter is also suggested and a fourth order voltage mode (VM) filter is developed from the proposed scheme. The effect of non-idealities on the proposed all pass filters is also studied. A simple oscillator is also developed using one of the all pass filter structure. The oscillator required only one DXCCDITA, two capacitors and one resistor for implementation. The DXCCDITA is implemented in 0.35[Formula: see text][Formula: see text]m TSMC CMOS technology parameters and tested in Tanner EDA. Sufficient numbers of simulations are provided to establish the functionality of all pass structures. The experimental results using commercially available integrated circuits (ICs) are also provided.

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GLADWIN, RUBAN, and NEHRU KASTHURI. "ROBUST AND SECURE S-BOX DESIGN WITH GATED HYBRID ENERGY RECOVERY LOGIC (GHERL) FOR IOT APPLICATIONS." DYNA 97, no. 1 (2022): 79–84. http://dx.doi.org/10.6036/10108.

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The smart Internet of Things (IoT) network relies heavily on data transmission over wireless channels. Hence, it should be designed to be robust against the attacks from hackers and antagonists. The confidentiality in IoT devices is directly proportional to the complexity and power consumption. To mitigate these issues, this paper proposes a secure Substitution Box (S-Box) design that is exploited in the IoT for cyber security applications. The S-Box is based on Gated Hybrid Energy Recovery Logic (GHERL) that is an amalgamation of two different techniques as adiabatic logic and power gating. Adiabatic logic is preferred to attain high energy efficiency in practical applications such as portable and handheld devices. Power gating technique is preferred to reduce the leakage power and energy consumption. The proposed GHERL XOR gate and S-Box are implemented with 125nm technology in Tanner EDA tool. The consequences of the experiments exhibits that the novel S-Box design with GHERL XOR decreases the power consumption by 1.76%, 35.26%, 36.81%, 41.01% and reduces the leakage power by 58.54%, 20.27%, 27.38%, 13.63% when compared with the existing techniques such as S-Box with sleep transistor, dual sleep transistor, dual-stack and sleepy keeper approach. Keywords: Adiabatic logic, Power Gating, Internet of Things, S-Box

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R, Yashaswini, and Kumar N. Krishna Murthy. "Design and Simulation of 16 Bit ADC." International Journal for Research in Applied Science and Engineering Technology 11, no. 7 (2023): 1017–24. http://dx.doi.org/10.22214/ijraset.2023.54790.

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Abstract: In this study, it was looked into how a 16-bit architecture might be used to develop an Analog-to-Digital Converter (ADC) Successive Approximation Register (SAR). The SAR ADC architecture is widely adopted for high-resolution applications because to its ease of use and minimal power requirements. The design also includes a voltage reference, a comparator, a successive approximation register, a sample-and-hold circuit, an analog-to-digital converter (DAC), and other components. A range of design approaches and circuit topologies are employed to maximize performance and satisfy the required criteria. The comparator is intended to properly detect the analogue input voltage and operate at high speeds. A binary search technique is used by the successive approximation register to find the input voltage's digital representation. The design is implemented using 250nm Gate Diffusion Input [GDI] Technology. Simulation and verification are performed using Tanner EDA tool. The results indicate that the proposed 16-bit SAR ADC achieves the desired resolution and meets the specified performance requirements. The ADC exhibits low power consumption, and satisfactory performance. This architecture its applications span across multiple disciplines, encompassing communication systems, scientific instrumentation, and medical imaging, where there is a requirement for accurate ADC conversion.

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Venkata, Lakshmi T., and M. Kamaraju. "A novel 1T-1D single ended SRAM cell using FinFET technology for low power applications." i-manager’s Journal on Electronics Engineering 14, no. 3 (2024): 6. http://dx.doi.org/10.26634/jele.14.3.20286.

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The increasing demand for high-density Very Large-Scale Integrated (VLSI) circuits, driven by the scaling of CMOS technology, is primarily challenged by the need for uniformity in SRAM cells. Given that most programs frequently seek dependable data, the primary cache and memory caching (MC) component in SRAM tends to be relatively steady. Resolving power and delay imbalances is the main problem with SRAM cells. The issues with CMOS-based SRAM cells include high cost, wide parameter variation, and worse dependability. CMOS devices also experience a loss of channel control by the gate. It is therefore advised to use FinFET-based SRAM cells rather than CMOS. This paper presents a design study of a 1T-1D SRAM cell using FinFET and CMOS technology. Without changing the logic state of the SRAM cell, the objective of this paper is to lessen power leakage. The cell structure's ease of design also contributes to its remarkable affordability and accessibility. A 1T-1D cell with the bare minimum of transistors has a smaller overall area. The suggested 1T-1D SRAM cell is implemented using the Tanner EDA working platform, which uses 7nm FinFET technology. With this study, low power was reached up to 99%, and delay reduction was improved to 98%.

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Ankit, Kumar* Dr. A.K. Gautam. "IMPROVEMENT IN NOISE AND DELAY IN DOMINO CMOS LOGIC CIRCUIT." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 5 (2017): 191–97. https://doi.org/10.5281/zenodo.573529.

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New experiments are always welcomed in the field of chip designing in VLSI technology. VLSI is advanced innovation over solid state devices and is based on CMOS designing. CMOS is a combination of PMOS and NMOS. The CMOS technology is mostly used to reduce power dissipation in circuitry and to minimize the losses. Still a sufficient amount of noise is present, which can cause for distortion in transmitted signal and make the whole transmission spurious. There are some known techniques which are used to minimize noise in any circuit i.e. keeper technique, pre-charge internal nodes and NMOS pull up transistor. The improvement over these three techniques is required so that noise could be more minimized and performance of circuitry can be increased. In this paper, experiments are done to add an additional part in the circuit to minimize the noise. The new improved circuit is named as ‘HIGH SPEED MASTER OUTPUT KEEPER DOMINO TECHNIQUE’ which minimize the noise up to great extent. All the experiment and calculations are done for logic gate using Tanner Tool EDA. The lowest noise present in AND gate was 1.75407 NV/HZ in old technique while it is minimize to 1.40310 NV/HZ in new technique.

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Suguna, T., and M. Janaki Rani. "Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications." International Journal of Interactive Mobile Technologies (iJIM) 14, no. 05 (2020): 73. http://dx.doi.org/10.3991/ijim.v14i05.13343.

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In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL styles. Moreover in this paper, 32 bit adders such as Ripple Carry Adder (RCA), Carry Select Adder (CSLA), Carry Save Adder (CSA), Carry Skip Adder (CSKA) and Brent Kung Adder (BKA) are realised using proposed ECRL and 2PASCL adiabatic full adders. All the adders are implemented and simulated using TANNER EDA tool 22nm technology, parameters like power, area, delay and power delay product (PDP) of all the adders are observed at different operating frequencies, with supply voltage of 0.95 v and load capacitance of 0.5 pF. The observed parameters are compared with the existing adiabatic full adder designs and concluded that the proposed adiabatic full adders have the advantages of less power, delay and transistor count. In conclusion ECRL full adder is 31% faster, has equal PDP and less area than 2PASCL full adder. At 1000MHz ECRL 32 bit carry save adder is having less delay among all the 32 bit adder and 65% less PDP than 2PASCL adder and it is concluded that ECRL 32 bit carry save adder can be selected for implementation of circuits that can be used in portable mobile applications.

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Saha, Aloke, Rahul Pal, and Jayanta Ghosh. "Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication." Micro and Nanosystems 12, no. 3 (2020): 149–58. http://dx.doi.org/10.2174/1876402911666190916155445.

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Background: The present study explores a novel self-pipelining strategy that can enhance speed-power efficiency as well as the reliability of a binary multiplier as compared to state-of-art register and wavepipelining. Method: Proper synchronization with efficient clocking between the subsequent self-pipelining stages has been assured to design a self-pipelined multiplier. Each self-pipelining stage consists of self-latching leaf cells that are designed, optimized and evaluated by TSMC 0.18μm CMOS technology with 1.8V supply rail and at 25°C temperature. The T-Spice transient response and simulated results for the designed circuits are presented. The proposed idea has been applied to design 4-b×4-b self-pipelined Wallace- tree multiplier. The multiplier was validated for all possible test patterns and the transient response was evaluated. The circuit performance in terms of propagation delay, average power and Power-Delay- Product (PDP) is recorded. Next, the decomposition logic is applied to design a higher-order multiplier (i.e., 8-bit×8-bit and 16-bit×16-bit) based on the proposed strategy using 4-bit×4-bit self-pipelined multiplier. The designed multiplier was also validated through extensive TSpice simulation for all the required test patterns using W-Edit and the evaluated performance is presented. All the designs, optimizations and evaluations performed are based on BSIM3 device parameter of TSMC 0.18μm CMOS technology with 1.8V supply rail at 25°C temperature using S-Edit of Tanner EDA. Results: The reliability was investigated of the proposed 4-b×4-b multiplier in the temperature range - 40°C to 100°C for maximum PDP variation. Conclusion: A benchmarking analysis in terms of speed-power performance with recent competitive design reveals preeminence of the proposed technique.

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Lasarte López, Rosana. "Tercera edad en Tanger." Acciones e Investigaciones Sociales, no. 14 (March 29, 2011): 153. http://dx.doi.org/10.26754/ojs_ais/ais.200214217.

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Después de un período de enorme esplendor y de una importante presencia española en la ciudad de Tánger, todavía queda allí una pequeña colonia española de la que forman parte un reducido número de personas mayores de 65 años.En este trabajo se analiza el perfil sociológico de estos mayores, las necesidades sociales que padecen, los recursos que les ofrece el Estado Español y se presenta el proyecto de intervenciones que se deberían poner en marcha para mejorar las condiciones de vida de esta población mayor en la ciudad marroquí.

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Oliván-Gonzalvo, Gonzalo, Paula Liliana Sanchez-Quiroz, and Alejandro Carlos De la Parte-Serna. "Uso de las etapas de Tanner para estimar la edad cronológica en presuntos casos de pornografía infantil: revisión sistemática." Andes Pediatrica 92, no. 3 (2021): 470. http://dx.doi.org/10.32641/andespediatr.v92i3.3374.

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En las dos últimas décadas se ha producido un crecimiento exponencial de la distribución y disponibilidad de material pornográfico infantil en Internet y las redes sociales. La comunidad médica está involucrada con la asistencia a las autoridades investigadoras en relación con la estimación de la edad y la madurez sexual de las presuntas víctimas.Objetivo: Determinar la eficacia del uso de las etapas de Tanner como método para estimar la edad cronológica en presuntos casos de pornografía infantil basada en la evidencia publicada.Material y Método: Estudio de revisión sistemática en las bases de datos PubMed y Scopus siguiendo directrices PRISMA. Se identificaron los artículos que describen el resultado del uso de las etapas de Tanner para estimar la edad cronológica en presuntos casos de pornografía infantil. Para el cribado se consideraron los escritos en inglés o español publicados desde el 1 de enero de 2000 hasta el 30 de abril de 2020. De los artículos finalmente incluidos se extrajeron los siguientes datos: tipo de estudio; material y métodos utilizados; ítems de Tanner examinados; características de los evaluadores; resultados; edad cronológica estimada versus la edad real; variaciones dependientes del observador (sesgo); conclusiones.Resultados: Se incluyeron siete estudios. Tres eran revisiones de la literatura y cuatro estudios de casos con testimonio de expertos y sesgo de los observadores. Este método es ineficaz cuando la presunta víctima, para ambos sexos, muestra una maduración sexual en las etapas 3-5 de Tanner. En las etapas 1-2 puede ser útil para testificar que la víctima es menor de 18 años, pero no para determinar su edad cronológica.Conclusión: La evidencia científica desaconseja el uso de las etapas de Tanner para estimar la edad cronológica de la víctima a partir de imágenes en supuestos casos de pornografía infantil. Los pediatras, y otros profesionales de la medicina, deben evitar emitir un testimonio que no tenga una base científica.

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Rodríguez, Priscila, María Mercedes Pérez, Adelvi Nieto, Alfredo Caraballo, and Melissa Osuna. "Ecografía pélvica: correlación de la evolución de útero y ovarios con estadios de Tanner de mama y edad." Revista de Obstetricia y Ginecología de Venezuela 80, no. 04 (2020): 303–11. http://dx.doi.org/10.51288/00800407.

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Objective: To correlate the ultrasound evolution of the uterus and ovaries, according to Tanner’s stages of breast and chronological age in patients attending the children’s and juvenile gynecology clinic of the children’s hospital “Dr. José Manuel de los Ríos “between March and October 2016. Methods: 113 patients aged between 7.7 and 15.5 years were evaluated. From them were excluded those ones who had presented menarche, urogynecologic malformation, endocrinopathy or a history of uterine or ovarian surgery. They were classified according to Tanner stages of breast. Transabdominal pelvic ultrasound was performed, additionally uterus and ovaries were measured and described. We calculated the mean standard deviation and median according to the type of variable, we applied an ANOVA non-parametric test of Kruskal-Wallis and chi-square of Pearson, it can be considered a statistically significant value if p <0.05. Results: Uterine length ranged from 33 mm in patients with Tanner I up to 52 mm in those with Tanner IV. Body/cervix ratio was 0.9 in patients with stage I, 1.12 with stage II, 1.42 with stage III and 1.30 with stage IV. A statistically significant relationship was found between ovarian volumes with both age groups and Tanner stages. As for the ovarian pattern, the most frequent one was the microfollicular. Conclusions: The uterus and ovaries show continuous growth in relation to age and the Tanner stage of breast, those factors with which a statistically significant relationship was demonstrated. Keywords: Pelvic ultrasound, uterus, ovaries, Tanner stages of breast.

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Rodriguez-Trigo, Gema. "Global Aspects and Health Effects of Oil Tanker Accidents." Epidemiology 20 (November 2009): S254. http://dx.doi.org/10.1097/01.ede.0000362850.88019.54.

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Prakhar, Bhardwaj, Sharan Harsha, and Saxena. Amit. "CMOS LAYOUT DESIGN FOR OTA-C BIQUAD FILTER." April 6, 2018. https://doi.org/10.5281/zenodo.1248756.

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This paper presents concept of universal bi-quad filter using operational trans-conductance amplifier (OTA).This OTA is biased using current of 62μA with supply voltage ?2v. TANNER environment with UMC 0.18μm technology file is used for simulation and design of this filter. This paper presents layout of an electronically tunable voltage mode universal bi-quadratic filter with three input and single output using two single ended OTA and two capacitors. The proposed filter provides low-pass, High-pass and Band-pass response by appropriately connecting the input terminals. The result of the 2nd order active bi-quad filter schematic is then compared with the layout drawn on Tanner EDA tool.

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Bennet, M. Anto, T.Mari Selvi, S.Mohana Priya, S. Monica, and R. Kanimozhi. "EFFICIENT APPROACHES FOR DESIGNING THE LOGICAL REVERSIBILITY OF COMPUTATION." International Journal on Smart Sensing and Intelligent Systems 10, no. 4 (2017). https://doi.org/10.21307/ijssis-2017-235.

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The work demonstrates about the reversible logic synthesis for the 2 to 4 decoder, the circuits are designed using reversible fault tolerant toffoli gates. Thus the entire scheme inherently becomes fault tolerant. In addition, several lower bounds on the number of constant inputs, garbage outputs and quantum cost of the reversible fault tolerant decoder have been proposed. Transistor simulations of the proposed decoder power consumption have been reduced than the existing approach without decreasing the speed, which proved the functional correctness of the proposed Decoder. The comparative results show that the proposed design is much better in terms of quantum cost, delay, hardware complexity and has significantly better scalability. Tanner software is the advanced industrial tool that is growing up in trend. So the proposed decoder is designed in Tanner EDA after completion of the circuit in DSCH and Microwind. This shows the power dissipation and power consumption at each nook and corner to re-design with low power consumption possible.

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"Design 10-Transistor (10t) Sram using Finfet Technology." International Journal of Engineering and Advanced Technology 9, no. 1 (2019): 566–72. http://dx.doi.org/10.35940/ijeat.a9690.109119.

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This paper discuss designing of low power, high-speed 10-Transistor (10T) SRAM and analysis of SRAM cell in Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and FinFET technology. MOSFET is used widely in many areas, but below 40 nm technology control of channel region becomes extremely difficult. So there is a necessity for new innovative technology which allows designers to design below 40nm technology and can offer excellent control over gate thus reducing short channel effects. The designing of SRAM is analyzed using TANNER EDA tool and Microwind.

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