Relevant bibliographies by topics / Tcad-sentaurus

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Tcad-sentaurus'

Author: Grafiati
Published: 4 June 2021
Last updated: 7 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Tcad-sentaurus.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Tcad-sentaurus"

1

Nabil, Amira, Ahmed Shaker, Mohamed Abouelatta, Hani Ragai, and Christian Gontrand. "Tunneling FET Calibration Issues: Sentaurus vs. Silvaco TCAD." Journal of Physics: Conference Series 1710 (November 2020): 012003. http://dx.doi.org/10.1088/1742-6596/1710/1/012003.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Kuznetsov, Maksim, Sergey Kalinin, Alexey Cherkaev, and Dmitriy Ostertak. "Investigating physical model interface in the TCAD Sentaurus environment." Transaction of Scientific Papers of the Novosibirsk State Technical University, no. 3 (November 18, 2020): 39–48. http://dx.doi.org/10.17212/2307-6879-2020-3-39-48.

Full text
Abstract:
Currently, the application SDevice software package TCAD Sentaurus is a reliable tool for electrophysical simulation of silicon CMOS transistors operating in the temperature range of -60 °C – +125 °C. To adapt the modeling process to specific physical conditions of the devices, application SDevice has an extensive library of models of electrophysical parameters, in particular models of mobility or band gap energy. However, when the device operates under extreme cryogenic conditions, there is a need to rework these models using a special Physical Model Interface (PMI). The paper presents methodological features of work with PMI and results of implementation of custom parameter models for silicon devices.
APA, Harvard, Vancouver, ISO, and other styles
3

Jiang, Yi Fan, B. Jayant Baliga, and Alex Q. Huang. "Influence of Lateral Straggling of Implated Aluminum Ions on High Voltage 4H-SiC Device Edge Termination Design." Materials Science Forum 924 (June 2018): 361–64. http://dx.doi.org/10.4028/www.scientific.net/msf.924.361.

Full text
Abstract:
This paper presents the analysis of Aluminum profile implanted into 4H-SiC with low background doping concentration. A strong lateral straggling effect was discovered with secondary electron potential contrast (SEPC) method, and analyzed by Sentaurus Monto Carlo simulations. The effect of lateral straggling was included in the edge termination design using Sentaurus TCAD simulation tool, and the results are compared with design not including the lateral straggling effect. The effect of interface charge on the electric field distribution and breakdown voltage of different 10 kV device edge termination designs was compared and analyzed.
APA, Harvard, Vancouver, ISO, and other styles
4

Johannesson, Daniel, Muhammad Nawaz, and Hans Peter Nee. "TCAD Model Calibration of High Voltage 4H-SiC Bipolar Junction Transistors." Materials Science Forum 963 (July 2019): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.963.670.

Full text
Abstract:
In this project, a Technology CAD (TCAD) model has been calibrated and verified against experimental data of a 15 kV silicon carbide (SiC) bipolar junction transistor (BJT). The device structure of the high voltage BJT has been implemented in the Synopsys Sentaurus TCAD simulation platform and design of experiment simulations have been performed to extract and fine-tune device parameters and 4H-SiC material parameters to accurately reflect the 15 kV SiC BJT experimental results. The set of calibrated TCAD parameters may serve as a base for further investigations of various SiC device design and device operation in electrical circuits.
APA, Harvard, Vancouver, ISO, and other styles
5

Dargar, Shashi Kant, J. K. Srivastava, Santosh Bharti, and Abha Nyati. "Performance Evaluation of GaN based Thin Film Transistor using TCAD Simulation." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 1 (February 1, 2017): 144. http://dx.doi.org/10.11591/ijece.v7i1.pp144-151.

Full text
Abstract:
<p>As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10<sup>7 </sup>~8.3×10<sup>8</sup>, and a sub-threshold slope of 0.44V/dec. Sentaurus TCAD simulations is the tool which offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.</p>
APA, Harvard, Vancouver, ISO, and other styles
6

Folkestad, Å., K. Akiba, M. van Beuzekom, E. Buchanan, P. Collins, E. Dall’Occo, A. Di Canto, et al. "Development of a silicon bulk radiation damage model for Sentaurus TCAD." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 874 (December 2017): 94–102. http://dx.doi.org/10.1016/j.nima.2017.08.042.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Boufouss, E., J. Alvarado, and D. Flandre. "Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000077–82. http://dx.doi.org/10.4071/hitec-eboufouss-ta25.

Full text
Abstract:
A temperature dependence analysis of the single event transient current induced by heavy ions irradiation is performed in the range of 300K to 500K on a 1μm SOI CMOS MOSFET standard 6T-SRAM cell. The Sentaurus TCAD mixed-mode numerical simulation showed a significant impact of the temperature on the current induced by the radiation and as a result, an increase of the 6T-SRAM sensitivity upon radiation. A SOI MOSFET compact model introduced in SPICE as a Verilog-A module reproducing the single event effects was developed. This model shows a very good agreement with the TCAD simulations results but with a drastic reduction of the simulation time. Furthermore this model could be extended to other circuits simulations. This result is of importance to allow for extensive circuit design studies which cannot be carried out with TCAD physical simulations.
APA, Harvard, Vancouver, ISO, and other styles
8

Rodríguez, Raúl, Benito González, Javier García, Gaetan Toulon, Frédéric Morancho, and Antonio Núñez. "DC Gate Leakage Current Model Accounting for Trapping Effects in AlGaN/GaN HEMTs." Electronics 7, no. 10 (September 21, 2018): 210. http://dx.doi.org/10.3390/electronics7100210.

Full text
Abstract:
A DC leakage current model accounting for trapping effects under the gate of AlGaN/GaN HEMTs on silicon has been developed. Based on TCAD numerical simulations (with Sentaurus Device), non-local tunneling under the Schottky gate is necessary to reproduce the measured transfer characteristics in a subthreshold regime. Once the trap concentration and distribution are determined in the device, the resulting gate leakage current is modeled making use of Verilog-A, for typical operation regimes.
APA, Harvard, Vancouver, ISO, and other styles
9

Phetchakul, Toempong, Wittaya Luanatikomkul, Chana Leepattarapongpan, E. Chaowicharat, Putapon Pengpad, and Amporn Poyai. "The Study of p-n and Schottky Junction for Magnetodiode." Advanced Materials Research 378-379 (October 2011): 663–67. http://dx.doi.org/10.4028/www.scientific.net/amr.378-379.663.

Full text
Abstract:
This paper presents the simulation model of Dual Magnetodiode and Dual Schottky Magnetodiode using Sentaurus TCAD to simulate the virtual structure of magneto device and apply Hall Effect to measure magnetic field response of the device. Firstly, we use the program to simulate the magnetodiode with p-type semiconductor and aluminum anode and measure electrical properties and magnetic field sensitivity. Simulation results show that sensitivity of Dual Schottky magnetodiode is higher than that of Dual magnetodiode.
APA, Harvard, Vancouver, ISO, and other styles
10

Salemi, Arash, Benedetto Buono, Anders Hallén, Jawad ul Hassan, Peder Bergman, Carl Mikael Zetterling, and Mikael Östling. "Fabrication and Design of 10 kV PiN Diodes Using On-Axis 4H-SiC." Materials Science Forum 778-780 (February 2014): 836–40. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.836.

Full text
Abstract:
10 kV PiN diodes using on-axis 4H-SiC were designed, fabricated, and measured. A lifetime enhancement procedure was done by carbon implantation followed by high temperature annealing to increase lifetime to above 2 μs. The device simulation software Sentaurus TCAD has been used in order to optimize the diode. All fabricated diodes are fully functional and have a VFof 3.3 V at 100 A/cm2at 25°C, which was decreased to 3.0 V at 300°C.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Tcad-sentaurus"

1

Mazzoli, Andrea. "TCAD analysis of hot-carrier-stress degradation in p-channel LDMOS power devices." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021.

Find full text
Abstract:
Nowadays, there is an increasing need to develop, reliable and low-cost power devices able to withstand high voltage drops and currents during the off-state and on-state operation, respectively. A useful strategy is represented by the integration on-chip of power devices with CMOS logic and analog technologies. This kind of solution is named BCD (BIPOLAR-CMOS-DMOS) technology. One of the fundamental power device on which the BCD technology is based is the LDMOS (Laterally-Diffused Metal-Oxide Semiconductor) transistor. The study and understanding of the degradation mechanisms affecting their long-term reliability is of great interest because of the stringent requirements in terms of safety, robustness, etc., basing on the field of application of the circuit in which the devices are integrated. This work, in collaboration with STMicroelectronics, focuses on the optimization of the p-channel LDMOS transistors and aims at studying and understanding how the Hot Carrier Stress (HCS) degradation impacts their performance for long working times. The behavior of the device is simulated through the Sentaurus TCAD where a HCS degradation model is employed to understand which are the dominant effects of the hot particles within the semiconductor, applying stress conditions aimed at accelerating the degradation mechanisms causing the drift of key parameters. In this work the focus is on the on-resistance, since it results to be the main parameter affected by degradation. The goal is to understand exactly which is the main cause of such variation in order to be able to allow a technology improvement. The simulations have been calibrated against experimental data. The on-resistance curve are correctly calibrated under certain stress conditions. The goal of the thesis activity has been achieved with accurate results, bringing to a more detailed description of a p-channel LDMOS power device through the development of a first version of the predictive simulation tool.
APA, Harvard, Vancouver, ISO, and other styles
2

El, Boubkari Kamal. "Impact de la modélisation physique bidimensionnelle multicellulaire du composant semi-conducteur de puissance sur l'évaluation de la fiabilité des assemblages appliqués au véhicule propre." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2013. http://tel.archives-ouvertes.fr/tel-00856596.

Full text
Abstract:
A bord des véhicules électriques (VE) et Hybrides (VEH), les fonctions de tractions sont assurées par des convertisseurs électroniques de puissances. Ces derniers sont constitués de module de puissance (IGBTs ou MOSFETs). Au cours de leur fonctionnement, ces modules sont parfois soumis à de fortes contraintes électriques et thermiques qui amènent à une défaillance ou même à une destruction. Le premier objectif sera de réaliser un banc expérimentale permettant d'étudier le vieillissement des modules IGBTs en régîmes extrêmes de fonctionnement (mode de court-circuit). Ainsi, nous évaluerons les différents indicateurs de vieillissements permettant de prédire la défaillance du composant. Il sera question aussi de suivre le vieillissement ou une dégradation initié sur les composants IGBTs par thermographie infrarouge. Le second objectif sera de modéliser et simuler par éléments finis différentes structures d'IGBTs, afin de valider les modèles en fonctionnement statique et dynamique. L'avantage de l'approche multicellulaire par rapport à l'approche unicellulaire sera mis en avant.
APA, Harvard, Vancouver, ISO, and other styles
3

Baccar, El Boubkari Fedia. "Évaluation des mécanismes de défaillance et de la fiabilité d’une nouvelle terminaison haute tension : approche expérimentale et modélisation associée." Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0266/document.

Full text
Abstract:
Ces travaux s’intègrent dans le projet de recherche SUPERSWITCH dans lequel des solutions alternatives à l’IGBT, utilisées dans les convertisseurs de puissance dans la gamme des tenues en tension 600-1200 V, sont envisagées. Les nouvelles structures du transistor MOS basées sur le principe de Super-Jonction tel que le transistor DT-SJMOSFET et sa terminaison originale, la « Deep Trench Termination » se propose comme alternative aux IGBT. Dans ce contexte, cette thèse se focalise sur la caractérisation de la robustesse de la terminaison DT2 adapté à une diode plane. Après avoir effectué un état de l’art sur les composants de puissances à semi-conducteur unidirectionnels en tension, les terminaisons des composants de puissance et la fiabilité des modules de puissance, un véhicule de test a été conçu en vue de réaliser les différents essais de vieillissement accéléré et suivi électrique. La fiabilité de la terminaison DT2 a été évaluée par des essais expérimentaux et des simulations numériques, dont une méthodologie innovante a été proposée. Au final de nouvelles structures ont été proposées pour limiter les problèmes de délaminage et de charges aux interfaces mis en avant dans notre étude
This work is a part of the research project SUPERSWITCH in which alternatives solutions to the IGBT, are investigated. This solution was used IGBT in power converters in the 600-1200 V breakdown voltage range. The new MOSFET structures based on the super-junction, such as the DT-SJMOSFET and its "Deep Trench Termination", is proposed as an alternative to IGBT. In this context, this thesis focuses on the robustness characterization of the DT2 termination adapted to a planar diode. After a state of the art on unidirectional voltage power components, the power components termination, and power modules reliability, a test vehicle has been designed in order to carry out different accelerated ageing tests and electrical monitoring. The reliability of DT2 termination was evaluated by experimental tests and numerical simulations. An innovative modeling methodology has been proposed. Finally, new structures have been proposed to limit the delamination failure mechanisms and interface charges problems highlighted in this thesis
APA, Harvard, Vancouver, ISO, and other styles
4

Legal, Julie. "Intégration des fonctions de protection avec les dispositifs IGBT." Phd thesis, Université Paul Sabatier - Toulouse III, 2010. http://tel.archives-ouvertes.fr/tel-00564270.

Full text
Abstract:
La fiabilité et la disponibilité des systèmes de gestion de l'énergie sont les conditions de base pour la généralisation de solutions électriques dans de nombreuses applications. Les dispositifs de puissance doivent être performants non seulement en régime normal, mais aussi en régimes extrêmes, par exemple lors des courts-circuits. Pour cela, les interrupteurs de puissance sont associés de façon discrète à des systèmes de détection et de protection. Une solution pour améliorer la fiabilité des dispositifs consiste à intégrer monolithiquement, au sein d'une même puce, l'interrupteur et les fonctions de détection et de protection. Ces dispositifs intégrés exploitent les interactions électriques qui apparaissent dans la puce pour détecter la défaillance et ainsi la stopper. L'interrupteur de puissance est ainsi protégé et se remet en conduction une fois la défaillance corrigée. Les composants de puissance seront ainsi capables de se protéger lors d'une défaillance. L'objectif de cette thèse est de proposer des solutions d'intégration de fonctions de protection et de diagnostic rapprochées avec les dispositifs IGBT afin d'augmenter la fiabilité et la disponibilité des systèmes de puissance. Les fonctions de protection sur lesquelles nous nous sommes focalisés sont le miroir de courant ("Sense") et le capteur d'anode ("Capteur de Tension d'Anode") pour détecter les courts-circuits. Ces deux capteurs ont été étudiés à l'aide de simulation 2D puis réalisés technologiquement. Un circuit de détection et de protection des IGBT contre les courts-circuits, comprenant le capteur de tension d'anode intégré monolithiquement, est proposé et simulé. Les tests électriques des capteurs en mode statique permettent de mieux comprendre leur comportement. Enfin, l'interrupteur IGBT associé à ses fonctions de détection et de protection est testé de manière discrète dans un circuit de commutation en condition de court-circuit afin de valider le fonctionnement.
APA, Harvard, Vancouver, ISO, and other styles
5

Bui, Thi Thanh Huyen. "Terminaisons verticales de jonction remplies avec des couches diélectriques isolantes pour des application haute tension utilisant des composants grand-gap de forte puissance." Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI061/document.

Full text
Abstract:
Le développement de l’énergie renouvelable loin des zones urbaines demande le transport d'une grande quantité d’énergie sur de longues distances. Le transport d’électricité en courant continu haute tension (HVDC) présente beaucoup d’avantages par rapport à celui en courant alternatif. Dans ce contexte il est nécessaire de développer des convertisseurs de puissance constitués par des composants électroniques très haute tension, 10 à 30 kV. Si les composants en silicium ne peuvent pas atteindre ces objectifs, le carbure de silicium (SiC) se positionne comme un matériau semiconducteur alternatif prometteur. Pour supporter des tensions élevées, une région de "drift", relativement large et peu dopée constitue le cœur du composant de puissance. En pratique l’obtention d’une tension de blocage effective dépend de plusieurs facteurs et surtout de la conception d'une terminaison de jonction adaptée. Cette thèse présente une méthode pour améliorer la tenue en tension des composants en SiC basée sur l’utilisation des terminaisons de jonctions : Deep Trench Termination. Cette méthode utilise une tranchée gravée profonde en périphérie du composant, remplie avec un matériau diélectrique pour supporter l'étalement des lignes équipotentielles. La conception de la diode avec cette terminaison a été faite par simulation TCAD, avec deux niveaux de tension 3 et 20 kV. Les travaux ont pris en compte les caractéristiques du matériau, les charges à l’interface de la tranchée et les limites technologiques pour la fabrication. Ce travail a abouti sur la fabrication de démonstrateurs et leur caractérisation pour valider notre conception. Lors de la réalisation de ces structures, la gravure plasma du SiC a été optimisée dans un bâti ICP de manière à obtenir une vitesse de gravure élevée et en conservant une qualité électronique de l'état des surfaces gravées. Cette qualité est confirmée par les résultats de caractérisation obtenus avec des tenues en tension proches de celle idéale
The development of renewable energy away from urban areas requires the transmission of a large amount of energy over long distances. High Voltage Direct Current (HVDC) power transmission has many advantages over AC power transmission. In this context, it is necessary to develop power converters based on high voltage power electronic components, 10 to 30 kV. If silicon components cannot achieve these objectives, silicon carbide (SiC) is positioned as a promising alternative semiconductor material. To support high voltages, a drift region, relatively wide and lightly doped is the heart of the power component. In practice obtaining an effective blocking voltage depends on several factors and especially the design of a suitable junction termination. This thesis presents a method to improve the voltage withstand of SiC components based on the use of junction terminations: Deep Trench Termination. This method uses a trench deep etching around the periphery of the component, filled with a dielectric material to support the spreading of the equipotential lines. The design of the diode with this termination was done by TCAD simulation, with two voltage levels 3 and 20 kV. The work took into account the characteristics of the material, the interface charge of the trench and the technological limits for the fabrication. This work resulted in the fabrication of demonstrators and their characterization to validate the design. During the production of these structures, plasma etching of SiC has been optimized in an ICP reactor so as to obtain a high etching rate and maintaining an electronic quality of the state of etched surfaces. This quality is confirmed by the results of characterization obtained with blocking voltage close to the ideal one
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Tcad-sentaurus"

1

Wu, Yung-Chun, and Yi-Ruei Jhan. "Introduction of Synopsys Sentaurus TCAD Simulation." In 3D TCAD Simulation for CMOS Nanoeletronic Devices, 1–17. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-3066-6_1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

"Simulation of JLFETS Using Sentaurus TCAD." In Junctionless Field-Effect Transistors, 385–438. Wiley, 2019. http://dx.doi.org/10.1002/9781119523543.ch9.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Tcad-sentaurus"

1

Kamaev, Gennadiy, Margarita Ashikhmina, and Alexey Cherkaev. "THE CONDUCTIVITY OF SILICON MESARESISTORS IN JOULE HEATING CONDITIONS." In International Forum “Microelectronics – 2020”. Joung Scientists Scholarship “Microelectronics – 2020”. XIII International conference «Silicon – 2020». XII young scientists scholarship for silicon nanostructures and devices physics, material science, process and analysis. LLC MAKS Press, 2020. http://dx.doi.org/10.29003/m1602.silicon-2020/208-211.

Full text
Abstract:
The article presents the results on the influence of geometric factors and surface states at the interfaces on the processes of electronic transport in thin silicon films on dielectric. TCAD Sentaurus calculations of the mesaresistors relative change resistance (ΔR\R) on the applied power, have shown the decisive role of traps with "shallow" states in the film conductivity. Their presence leads to a nonmonotonic dependence ΔR\R.
APA, Harvard, Vancouver, ISO, and other styles
2

Kuznetsov, Dmitry O. "Silicon thermal oxidation models comparison used in TCAD Sentaurus process and fact." In 2008 9th International Workshop and Tutorials on Electron Devices and Materials. IEEE, 2008. http://dx.doi.org/10.1109/sibedm.2008.4585855.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Wozny, Janusz, Jacek Podgorski, Ewa Raj, and Zbigniew Lisik. "Good Practices of Electrothermal Simulation of p-n Structures Using Sentaurus TCAD." In 2019 IEEE 15th International Conference on the Experience of Designing and Application of CAD Systems (CADSM). IEEE, 2019. http://dx.doi.org/10.1109/cadsm.2019.8779329.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

binti Morsin, Marlia, and Mohd Khairul Amriey. "Designing and characterization of 60nm p-well MOSFET using Sentaurus TCAD Software." In 2010 2nd International Conference on Electronic Computer Technology. IEEE, 2010. http://dx.doi.org/10.1109/icectech.2010.5479966.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Saburova, Vladislava I., Gennady N. Kamaev, Aleksey S. Cherkaev, and Victor A. Gridchin. "Modeling of the Temperature Dependence of Polycrystalline-Si Conductivity in TCAD Sentaurus Environment." In 2018 XIV International Scientific-Technical Conference on Actual Problems of Electronics Instrument Engineering (APEIE). IEEE, 2018. http://dx.doi.org/10.1109/apeie.2018.8545585.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Trinh, Cham Thi, Amran Al-Ashouri, Lars Korte, Daniel Amkreutz, Steve Albrecht, Bernd Stannowski, and Rutger Schlatmann. "Electrical and optical simulation of perovskite/silicon tandem solar cells using Tcad-Sentaurus." In 2021 IEEE 48th Photovoltaic Specialists Conference (PVSC). IEEE, 2021. http://dx.doi.org/10.1109/pvsc43889.2021.9519104.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Kashirskaya, Oxana N. "Sentaurus TCAD for modeling of the elements of the matrix photodetectors on organic compounds." In 2015 16th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM). IEEE, 2015. http://dx.doi.org/10.1109/edm.2015.7184482.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Li, Yonghong, Chaohui He, and Chunmei Xia. "Simulation of Heavy Ion Source-Drain Penetration Effect in SOI MOS and Bulk MOS." In 18th International Conference on Nuclear Engineering. ASMEDC, 2010. http://dx.doi.org/10.1115/icone18-29782.

Full text
Abstract:
The Single Event Effects (SEE) of Silicon On Insulator (SOI) and bulk-silicon NMOS are simulated using the SENTAURUS-TCAD device simulator. The Source-Drain Penetration Effect, which is caused by a heavy ion, was shown. It is proved that when the feature size of device become less than a certain scale, both Direct Channel Effect and Indirect Channel Effect occur. By comparing the distributions of equipotential lines in the MOSFETs’ channels of the different feature size devices during the ion strikes indirectly, the Source-Drain-Penetration Effect occurs more evidently when the device feature size is getting smaller.
APA, Harvard, Vancouver, ISO, and other styles
9

Krasukov, Anton Y., and Anton N. Mansurov. "Modeling of tot al dose radiation effect of RF PD SOI-MOSFET using Sentaurus TCAD." In 2009 International Conference and Seminar on Micro/Nanotechnologies and Electron Devices (EDM). IEEE, 2009. http://dx.doi.org/10.1109/edm.2009.5173951.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Ануфриев, Владимир, Vladimir Anufriev, Антон Козлов, and Anton Kozlov. "INVESTIGATION OF THE INTEGRAL MAGNETO SENSITIVITY HALL SENSOR WITH PN JUNCTIONS BY THE SENTAURUS TCAD NUMERICAL MODELING." In CAD/EDA/Simulation in Modern Electronics. Bryansk State Technical University, 2018. http://dx.doi.org/10.30987/conferencearticle_5c19e5de650781.53271413.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Tcad-sentaurus' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography