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Journal articles on the topic 'Tcad-sentaurus'

Author: Grafiati

Published: 4 June 2021

Last updated: 7 February 2022

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1

Nabil, Amira, Ahmed Shaker, Mohamed Abouelatta, Hani Ragai, and Christian Gontrand. "Tunneling FET Calibration Issues: Sentaurus vs. Silvaco TCAD." Journal of Physics: Conference Series 1710 (November 2020): 012003. http://dx.doi.org/10.1088/1742-6596/1710/1/012003.

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2

Kuznetsov, Maksim, Sergey Kalinin, Alexey Cherkaev, and Dmitriy Ostertak. "Investigating physical model interface in the TCAD Sentaurus environment." Transaction of Scientific Papers of the Novosibirsk State Technical University, no. 3 (November 18, 2020): 39–48. http://dx.doi.org/10.17212/2307-6879-2020-3-39-48.

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Currently, the application SDevice software package TCAD Sentaurus is a reliable tool for electrophysical simulation of silicon CMOS transistors operating in the temperature range of -60 °C – +125 °C. To adapt the modeling process to specific physical conditions of the devices, application SDevice has an extensive library of models of electrophysical parameters, in particular models of mobility or band gap energy. However, when the device operates under extreme cryogenic conditions, there is a need to rework these models using a special Physical Model Interface (PMI). The paper presents method

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3

Jiang, Yi Fan, B. Jayant Baliga, and Alex Q. Huang. "Influence of Lateral Straggling of Implated Aluminum Ions on High Voltage 4H-SiC Device Edge Termination Design." Materials Science Forum 924 (June 2018): 361–64. http://dx.doi.org/10.4028/www.scientific.net/msf.924.361.

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This paper presents the analysis of Aluminum profile implanted into 4H-SiC with low background doping concentration. A strong lateral straggling effect was discovered with secondary electron potential contrast (SEPC) method, and analyzed by Sentaurus Monto Carlo simulations. The effect of lateral straggling was included in the edge termination design using Sentaurus TCAD simulation tool, and the results are compared with design not including the lateral straggling effect. The effect of interface charge on the electric field distribution and breakdown voltage of different 10 kV device edge term

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4

Johannesson, Daniel, Muhammad Nawaz, and Hans Peter Nee. "TCAD Model Calibration of High Voltage 4H-SiC Bipolar Junction Transistors." Materials Science Forum 963 (July 2019): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.963.670.

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In this project, a Technology CAD (TCAD) model has been calibrated and verified against experimental data of a 15 kV silicon carbide (SiC) bipolar junction transistor (BJT). The device structure of the high voltage BJT has been implemented in the Synopsys Sentaurus TCAD simulation platform and design of experiment simulations have been performed to extract and fine-tune device parameters and 4H-SiC material parameters to accurately reflect the 15 kV SiC BJT experimental results. The set of calibrated TCAD parameters may serve as a base for further investigations of various SiC device design an

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Dargar, Shashi Kant, J. K. Srivastava, Santosh Bharti, and Abha Nyati. "Performance Evaluation of GaN based Thin Film Transistor using TCAD Simulation." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 1 (2017): 144. http://dx.doi.org/10.11591/ijece.v7i1.pp144-151.

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<p>As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10<sup>7 &l

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6

Folkestad, Å., K. Akiba, M. van Beuzekom, et al. "Development of a silicon bulk radiation damage model for Sentaurus TCAD." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 874 (December 2017): 94–102. http://dx.doi.org/10.1016/j.nima.2017.08.042.

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Boufouss, E., J. Alvarado, and D. Flandre. "Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (2010): 000077–82. http://dx.doi.org/10.4071/hitec-eboufouss-ta25.

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A temperature dependence analysis of the single event transient current induced by heavy ions irradiation is performed in the range of 300K to 500K on a 1μm SOI CMOS MOSFET standard 6T-SRAM cell. The Sentaurus TCAD mixed-mode numerical simulation showed a significant impact of the temperature on the current induced by the radiation and as a result, an increase of the 6T-SRAM sensitivity upon radiation. A SOI MOSFET compact model introduced in SPICE as a Verilog-A module reproducing the single event effects was developed. This model shows a very good agreement with the TCAD simulations results

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8

Rodríguez, Raúl, Benito González, Javier García, Gaetan Toulon, Frédéric Morancho, and Antonio Núñez. "DC Gate Leakage Current Model Accounting for Trapping Effects in AlGaN/GaN HEMTs." Electronics 7, no. 10 (2018): 210. http://dx.doi.org/10.3390/electronics7100210.

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A DC leakage current model accounting for trapping effects under the gate of AlGaN/GaN HEMTs on silicon has been developed. Based on TCAD numerical simulations (with Sentaurus Device), non-local tunneling under the Schottky gate is necessary to reproduce the measured transfer characteristics in a subthreshold regime. Once the trap concentration and distribution are determined in the device, the resulting gate leakage current is modeled making use of Verilog-A, for typical operation regimes.

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Phetchakul, Toempong, Wittaya Luanatikomkul, Chana Leepattarapongpan, E. Chaowicharat, Putapon Pengpad, and Amporn Poyai. "The Study of p-n and Schottky Junction for Magnetodiode." Advanced Materials Research 378-379 (October 2011): 663–67. http://dx.doi.org/10.4028/www.scientific.net/amr.378-379.663.

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This paper presents the simulation model of Dual Magnetodiode and Dual Schottky Magnetodiode using Sentaurus TCAD to simulate the virtual structure of magneto device and apply Hall Effect to measure magnetic field response of the device. Firstly, we use the program to simulate the magnetodiode with p-type semiconductor and aluminum anode and measure electrical properties and magnetic field sensitivity. Simulation results show that sensitivity of Dual Schottky magnetodiode is higher than that of Dual magnetodiode.

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10

Salemi, Arash, Benedetto Buono, Anders Hallén, et al. "Fabrication and Design of 10 kV PiN Diodes Using On-Axis 4H-SiC." Materials Science Forum 778-780 (February 2014): 836–40. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.836.

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10 kV PiN diodes using on-axis 4H-SiC were designed, fabricated, and measured. A lifetime enhancement procedure was done by carbon implantation followed by high temperature annealing to increase lifetime to above 2 μs. The device simulation software Sentaurus TCAD has been used in order to optimize the diode. All fabricated diodes are fully functional and have a VFof 3.3 V at 100 A/cm2at 25°C, which was decreased to 3.0 V at 300°C.

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Gulomov, Jasurbek, Rayimjon Aliev, Murad Nasirov, and Jakhongir Ziyoitdinov. "MODELING METAL NANOPARTICLES INFLUENCE TO PROPERTIES OF SILICON SOLAR CELLS." International Journal of Advanced Research 8, no. 11 (2020): 336–45. http://dx.doi.org/10.21474/ijar01/12015.

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Nanotechnologies are entering every field. Nanoparticles have been widely used in medicine and technology. We decided to study the behavior of nanoparticles under the influence of light and its effects on solar cells, based on a number of properties. How gold and silver nanoparticles are introduced into the optical layer of the solar cell has been studied enough to affect the properties of the solar cell. However, the effect of silicon-based solar cell metal nanoparticles in the n domain on the solar cell has not been sufficiently studied. In addition, in this study, the properties of solar ce

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12

Liu, Xue Qing, Sauvik Chowdhury, Collin W. Hitchcock, and T. Paul Chow. "Impact of Cell Geometry on Zero-Energy Turn-Off of SiC Power MOSFETs." Materials Science Forum 924 (June 2018): 756–60. http://dx.doi.org/10.4028/www.scientific.net/msf.924.756.

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1200V SiC power MOSFETs of various cell geometries are modeled in Synopsis Inc. Sentaurus TCAD. The impact of cell geometry on switching loss is studied by comparing the turn-on and turn-off losses using refined calculation methods. Under optimum circuit conditions, two different novel unit cell designs each achieve lower switching losses than conventional designs. For all the designs, lossless turn-on is impossible but lossless turn-off is achievable under circuit and biasing conditions that produce sufficiently rapid gate slew.

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Daliento, Santolo, Pierluigi Guerriero, Luisa Addonizio, and Alessandro Antonaia. "Numerical analysis of ZnO thin layers having rough surface." Facta universitatis - series: Electronics and Energetics 28, no. 2 (2015): 275–86. http://dx.doi.org/10.2298/fuee1502275d.

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In this paper an automated procedure for the analysis of Transparent Conductive Oxides (TCO) layers exhibiting rough surfaces is proposed. The method is based on the interaction between MATLand the Sentaurus TCAD and is aimed to the reduction of computational efforts needed for full three dimensional analyses. Experiments performed on CVD deposited ZnO layer, showing the reliability of the method for describing their optical properties, are reported. A semi-empirical technique for the extraction of the TCO refractive index is shown as well.

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14

Palomo, F. R., P. Fernández-Martínez, J. M. Mogollón, et al. "Simulation of femtosecond pulsed laser effects on MOS electronics using TCAD Sentaurus customized models." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 23, no. 4-5 (2010): 379–99. http://dx.doi.org/10.1002/jnm.736.

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15

Jaikumar, M. G., and Shreepad Karmalkar. "Calibration of Mobility and Interface Trap Parameters for High Temperature TCAD Simulation of 4H-SiC VDMOSFETs." Materials Science Forum 717-720 (May 2012): 1101–4. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1101.

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4H-Silicon Carbide VDMOSFET is simulated using the Sentaurus TCAD package of Synopsys. The simulator is calibrated against measured data for a wide range of bias conditions and temperature. Material parameters of 4H-SiC are taken from literature and used in the available silicon models of the simulator. The empirical parameters are adjusted to get a good fit between the simulated curves and measured data. The simulation incorporates the bias and temperature dependence of important physical mechanisms like interface trap density, coulombic interface trap scattering, surface roughness scattering

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16

Khalid, Muhammad, Waseem Raza, Saira Riaz, and Shahzad Naseem. "Simulation and Analysis of Static and Dynamic Performance of Normally-off TIVJFET Using Sentaurus TCAD." Materials Today: Proceedings 2, no. 10 (2015): 5720–25. http://dx.doi.org/10.1016/j.matpr.2015.11.117.

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17

Леган, Д. М., О. П. Пчеляков та В. В. Преображенский. "Оптимизация толщины слоя In-=SUB=-0.3-=/SUB=-Ga-=SUB=-0.7-=/SUB=-As в трехкаскадном In-=SUB=-0.3-=/SUB=-Ga-=SUB=-0.7-=/SUB=-As/GaAs/In-=SUB=-0.5-=/SUB=-Ga-=SUB=-0.5-=/SUB=-P солнечном элементе". Физика и техника полупроводников 54, № 1 (2020): 65. http://dx.doi.org/10.21883/ftp.2020.01.48776.9240.

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The search of the optimal absorbing layer thickness in the bottom In0.3Ga0.7As subcell of the triple-junction In0.3Ga0.7As/GaAs/In0.5Ga0.5P solar cell was carried out assisted by the Sentaurus TCAD software package, depending on the minority charge carrier lifetime in this layer. The lifetime value was set manually and it was in the range from 17 ps to 53 ns. The calculation results showed that the optimal thickness varies from 0.9 to 7.5 μm. The estimation of the efficiency contribution of the bottom In0.3Ga0.7As subcell to the given triple-junction solar cell, at various lifetime values, was

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18

Yang, Shao-Ming, Gene Sheu, Tzu Chieh Lee, Ting Yao Chien, Chieh Chih Wu, and Yun Jung Lin. "Design of a Low on Resistance High Voltage (120V) Novel 3D NLDMOS with Side Isolation Based on 0.35um BCD Process Technology." MATEC Web of Conferences 201 (2018): 02004. http://dx.doi.org/10.1051/matecconf/201820102004.

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High performance power device is necessary for BCD power device. In this paper, we used 3D Synopsis TCAD simulation tool Sentaurus to develop 120V device and successfully simulated. We implemented in a conventional 0.35um BCDMOS process to present of a novel high side 120V LDMOS have reduced surface field (RESURF) and Liner p-top structure with side isolation technology. The device has been research to achieve a benchmark specific on-resistance of 189 mΩ-mm2 while maintaining horizontal breakdown voltage and vertical isolation voltage both to target breakdown voltage of 120V. In ESOA, we also

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19

Passeri, D., F. Moscatelli, A. Morozzi, and G. M. Bilei. "Modeling of radiation damage effects in silicon detectors at high fluences HL-LHC with Sentaurus TCAD." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 824 (July 2016): 443–45. http://dx.doi.org/10.1016/j.nima.2015.08.039.

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20

Zhu, Shunwei, Hujun Jia, Tao Li, et al. "Novel High-Energy-Efficiency AlGaN/GaN HEMT with High Gate and Multi-Recessed Buffer." Micromachines 10, no. 7 (2019): 444. http://dx.doi.org/10.3390/mi10070444.

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A novel AlGaN/GaN high-electron-mobility transistor (HEMT) with a high gate and a multi-recessed buffer (HGMRB) for high-energy-efficiency applications is proposed, and the mechanism of the device is investigated using technology computer aided design (TCAD) Sentaurus and advanced design system (ADS) simulations. The gate of the new structure is 5 nm higher than the barrier layer, and the buffer layer has two recessed regions in the buffer layer. The TCAD simulation results show that the maximum drain saturation current and transconductance of the HGMRB HEMT decreases slightly, but the breakdo

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21

Nipoti, Roberta, Giovanna Sozzi, Maurizio Puzzanghera, and Roberto Menozzi. "Al+ implanted vertical 4H-SiC p-i-n diodes: experimental and simulated forward current-voltage characteristics." MRS Advances 1, no. 54 (2016): 3637–42. http://dx.doi.org/10.1557/adv.2016.315.

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ABSTRACT The temperature dependence of the forward and reverse current voltage characteristics of circular Al+ implanted 4H-SiC p-i-n vertical diodes of various diameters, post implantation annealed at 1950 °C/5 min, have been used to obtain the thermal activation energies of the defects responsible of the generation and the recombination currents, as well as the area and the periphery current component of the current voltage characteristics. The former have values compatible with those of the traps associated to the carbon vacancy defect in 4H-SiC. The hypothesis that only these traps may jus

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Koptev, N. S., and A. A. Pugachev. "TCAD-ASSISTED TECHNIQUE FOR DETERMINING THE PARAMETERS OF MICROLENSES USED IN PHOTOSENSITIVE CCD VLSI." Electronic engineering Series 2 Semiconductor devices 257, no. 2 (2020): 28–36. http://dx.doi.org/10.36845/2073-8250-2020-257-2-28-36.

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In this paper we introduce the simulation technique for photosensitive cell with CCD VLSI microlens with interline transfer. A microlens enhances the photosensitivity of the cell and reduces image blur. The technique is based on the calculation and comparison of the volumetric photogeneration rate integrals of different areas of the photocell, where generated charge carriers are collected and transferred. This technique does not require simulation of the full frame accumulation cycle of the cell, significantly reducing the time of simulation and enabling the evaluation of many design options f

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Salemi, Arash, Hossein Elahipanah, Carl Mikael Zetterling, and Mikael Östling. "10+ kV Implantation-Free 4H-SiC PiN Diodes." Materials Science Forum 897 (May 2017): 423–26. http://dx.doi.org/10.4028/www.scientific.net/msf.897.423.

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Implantation-free mesa etched 10+ kV 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. An area-optimized junction termination extension (O-JTE) is implemented in order to achieve a high breakdown voltage. The diodes design allows a high breakdown voltage of about 19.3 kV according to simulations by Sentaurus TCAD. No breakdown voltage is recorded up to 10 kV with a very low leakage current of 0.1 μA. The current spreading within the thick drift layer is considered and a voltage drop (VF) of 8.3 V and 11.4 V are measured at 50 A/cm2 and 100 A/cm2, respectively. The d

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Moni, Jackuline, and T. Jaspar Vinitha Sundari. "Junctionless Tunneling Nanowire for Steep Subthreshold Slope." Advanced Science Letters 24, no. 8 (2018): 5695–99. http://dx.doi.org/10.1166/asl.2018.12179.

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Using standardized simulations, we report a meticulous learning of the Junctionless nanowire with tunneling mechanism and the dependence of Subthreshold slope on operational parameters by varying the channel diameter, Gate length and doping concentration using Synopsys Sentaurus TCAD simulations. For the first time, Junctionless Nanowire in the company of tunneling architecture is proposed and explored. Our simulation study shows that a decrease in channel diameter and doping concentration results in higher band to band generation and steeper slope. Junctionless tunneling nanowire of diameter

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Gan, Lu-Rong, Ya-Rong Wang, Lin Chen, Hao Zhu, and Qing-Qing Sun. "A Floating Gate Memory with U-Shape Recessed Channel for Neuromorphic Computing and MCU Applications." Micromachines 10, no. 9 (2019): 558. http://dx.doi.org/10.3390/mi10090558.

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We have simulated a U-shape recessed channel floating gate memory by Sentaurus TCAD tools. Since the floating gate (FG) is vertically placed between source (S) and drain (D), and control gate (CG) and HfO2 high-k dielectric extend above source and drain, the integrated density can be well improved, while the erasing and programming speed of the device are respectively decreased to 75 ns and 50 ns. In addition, comprehensive synaptic abilities including long-term potentiation (LTP) and long-term depression (LTD) are demonstrated in our U-shape recessed channel FG memory, highly resembling the b

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Othman, Nurul Aida Farhana, Sharidya Rahman, Sharifah Fatmadiana Wan Muhamad Hatta, Norhayati Soin, Brahim Benbakhti, and Steven Duffy. "Design optimization of the graded AlGaN/GaN HEMT device performance based on material and physical dimensions." Microelectronics International 36, no. 2 (2019): 73–82. http://dx.doi.org/10.1108/mi-09-2018-0057.

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Purpose To design and optimize the traditional aluminum gallium nitride/gallium nitride high electron mobility transistor (HEMT) device in achieving improved performance and current handling capability using the Synopsys’ Sentaurus TCAD tool. Design/methodology/approach Varying material and physical considerations, specifically investigating the effects of graded barriers, spacer interlayer, material selection for the channel, as well as study of the effects in the physical dimensions of the HEMT, have been extensively carried out. Findings Critical figure-of-merits, specifically the DC charac

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Patil, Kalawati, and B. K. Mishra. "Dielectric Dependent Absorption Characteristics in CNFET Infrared Phototransistor." International Journal of Engineering and Technologies 19 (December 2020): 11–21. http://dx.doi.org/10.18052/www.scipress.com/ijet.19.11.

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In future infrared photodetectors, single-walled carbon nanotubes (SWCNTs) are considered as potential candidates due to their band gap, high absorption coefficient (104 - 105 cm −1), high charge carrier mobility and ease of processability. The SWCNT based Field Effect Transistors (CNFETs) are being seriously considered for applications in optoelectronics. In the proposed work optically controlled back gated CNFET is modeled in Sentaurus TCAD to observe the impact of high dielectric oxides on its photoabsorption. The model is based on analytical approximations and parameters extracted from qua

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Sahoo, Sasmita, Sidhartha Dash, and Guru P. Mishra. "An Accurate Drain Current Model for Symmetric Dual Gate Tunnel FET Using Effective Tunneling Length." Nanoscience &Nanotechnology-Asia 9, no. 1 (2018): 85–91. http://dx.doi.org/10.2174/2210681207666170612081017.

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Introduction: Here we propose an accurate drain current model for a Symmetric Dual Gate Tunnel FET (SDG-TFET) using effective tunneling length and generation rate of carrier over tunneling junction area. Analytical Modeling: The surface potential of the model is obtained by solving 2-dimensional Poisson’s equation and further extends to determine the magnitude of initial tunneling length and final tunneling length. The different DC performance indicators like drain current (ID), threshold voltage (Vth), transconductance (gm) and Subthreshold Slope (SS) for the present model are extensively inv

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Wang, You, Yu Mao, Qizheng Ji, Ming Yang, Zhaonian Yang, and Hai Lin. "Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET." Electronics 10, no. 4 (2021): 454. http://dx.doi.org/10.3390/electronics10040454.

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Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure curre

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Li, Han, Chen Wang, Lin Chen, Hao Zhu, and Qingqing Sun. "A Semi-Floating Gate Memory Based on SOI Substrate by TCAD Simulation." Electronics 8, no. 10 (2019): 1198. http://dx.doi.org/10.3390/electronics8101198.

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Over the past decade, the dimensional scaling of semiconductor electronic devices has been facing fundamental and physical challenges, and there is currently an urgent need to increase the ability of dynamic random-access memory (DRAM). A semi-floating gate (SFG) transistor has been proposed as a capacitor-less memory with faster speed and higher density as compared with the conventional one-transistor one-capacitor (1T1C) DRAM technology. The integration of SFG-based memory on the silicon-on-insulator (SOI) substrate has been demonstrated in this work by using the Sentaurus Technology Compute

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Choi, Yejoo, Jinwoong Lee, Jaehyuk Lim, Seungjun Moon, and Changhwan Shin. "Impact of Process-Induced Variations on Negative Capacitance Junctionless Nanowire FET." Electronics 10, no. 16 (2021): 1899. http://dx.doi.org/10.3390/electronics10161899.

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In this study, the impact of the negative capacitance (NC) effect on process-induced variations, such as work function variation (WFV), random dopant fluctuation (RDF), and line edge roughness (LER), was investigated and compared to those of the baseline junctionless nanowire FET (JL-NWFET) in both linear (Vds = 0.05 V) and saturation (Vds = 0.5 V) modes. Sentaurus TCAD and MATLAB were used for the simulation of the baseline JL-NWFET and negative capacitance JL-NWFET (NC-JL-NWFET). Owing to the NC effect, the NC-JL-NWFET showed less variation in terms of device performance, such as σ[Vt], σ[SS

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Dehzangi, Arash, Farhad Larki, Sawal Hamid Md Ali, et al. "Study of the side gate junctionless transistor in accumulation region." Microelectronics International 33, no. 2 (2016): 61–67. http://dx.doi.org/10.1108/mi-03-2015-0027.

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Purpose The purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition. Design/methodology/approach The device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transf

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Adak, Sarosij, Sanjit Kumar Swain, Hemant Pardeshi, Hafizur Rahaman, and Chandan Kumar Sarkar. "Effect of Barrier Thickness on Linearity of Underlap AlInN/GaN DG-MOSHEMTs." Nano 12, no. 01 (2017): 1750009. http://dx.doi.org/10.1142/s1793292017500096.

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In this proposed work, an extensive study on the linearity performance of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) has been analyzed using 2D Sentaurus TCAD simulation. Specifically a brief comparison is made on the linearity and intermodulation distortion characteristics of the proposed device due to variation of barrier layer thickness from 2 nm to 6 nm. Various parameters such as transconductance ([Formula: see text], second-order transconductance ([Formula: see text]), third-order transconductance ([Formula: see text]), second-o

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Chakraborty, C. "Role of interfacial layer thickness on high-κ dielectric-based MOS devices". Journal of Advanced Dielectrics 04, № 03 (2014): 1450023. http://dx.doi.org/10.1142/s2010135x14500234.

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An attempt has been made to investigate the role of interfacial layer (IL) and its thickness on HfO 2-based high-κ metal-oxide-semiconductor (MOS) devices. The capacitance–voltage (C–V) and current–voltage (I–V) characteristics have been simulated using Sentaurus TCAD software for two different IL thicknesses and at different substrate temperatures and doping concentrations. The device performance is found to be improved for an IL thickness of 1 nm at higher temperature but deteriorates with further increase in IL thickness. The capacitance value decreases with the increase in IL thickness and

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Zhu, Shunwei, Hujun Jia, Xingyu Wang, et al. "Improved MRD 4H-SiC MESFET with High Power Added Efficiency." Micromachines 10, no. 7 (2019): 479. http://dx.doi.org/10.3390/mi10070479.

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An improved multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (IMRD 4H-SiC MESFET) with high power added efficiency is proposed and studied by co-simulation of advanced design system (ADS) and technology computer aided design (TCAD) Sentaurus software in this paper. Based on multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (MRD 4H-SiC MESFET), the recessed area of MRD MESFET on both sides of the gate is optimized, the direct current (DC), radio frequency (RF) parameters and efficiency of the device i

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Wang, Ying, Chan Shan, Wei Piao, et al. "3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance." Micromachines 9, no. 12 (2018): 659. http://dx.doi.org/10.3390/mi9120659.

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In this paper, for the first time, an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) layout with a Z gate and an improved total ionizing dose (TID) tolerance is proposed. The novel layout can be radiation-hardened with a fixed charge density at the shallow trench isolation (STI) of 3.5 × 1012 cm−2. Moreover, it has the advantages of a small footprint, no limitation in W/L design, and a small gate capacitance compared with the enclosed gate layout. Beside the Z gate layout, a non-radiation-hardened single gate layout and a radiation-hardened enclosed gate layout are simul

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Chen, Wei-Ren, Yao-Chuan Tsai, Po-Jen Shih, Cheng-Chih Hsu, and Ching-Liang Dai. "Magnetic Micro Sensors with Two Magnetic Field Effect Transistors Fabricated Using the Commercial Complementary Metal Oxide Semiconductor Process." Sensors 20, no. 17 (2020): 4731. http://dx.doi.org/10.3390/s20174731.

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The fabrication and characterization of a magnetic micro sensor (MMS) with two magnetic field effect transistors (MAGFETs) based on the commercial complementary metal oxide semiconductor (CMOS) process are investigated. The magnetic micro sensor is a three-axis sensing type. The structure of the magnetic microsensor is composed of an x/y-MAGFET and a z-MAGFET. The x/y-MAGFET is employed to sense the magnetic field (MF) in the x- and y-axis, and the z-MAGFET is used to detect the MF in the z-axis. To increase the sensitivity of the magnetic microsensor, gates are introduced into the two MAGFETs

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Adak, Sarosij, and Sanjit Kumar Swain. "Impact of High-K Dielectric Materials on Performance Analysis of Underlap In0.17Al0.83N/GaN DG-MOSHEMTs." Nano 14, no. 05 (2019): 1950060. http://dx.doi.org/10.1142/s1793292019500607.

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This work systematically investigated the effect of high-[Formula: see text] oxide materials on the performance of InAlN/GaN heterostructure underlap double gate (DG) MOS-HEMTs by considering 2D Sentaurus TCAD simulation. During the course of simulation, hydrodynamic mobility model was implemented and the obtained results were used for validating the model with the previously published experimental results. Different device performance parameters are thoroughly studied for different high-[Formula: see text] oxide materials by performing extensive simulations. It is verified that short channel

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Chakraborty, Chaitali, and Chayanika Bose. "Effect of size and position of gold nanocrystals embedded in gate oxide of SiO2/Si MOS structures." Journal of Advanced Dielectrics 06, no. 01 (2016): 1650001. http://dx.doi.org/10.1142/s2010135x16500016.

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The influence of single and double layered gold (Au) nanocrystals (NC), embedded in SiO2 matrix, on the electrical characteristics of metal–oxide–semiconductor (MOS) structures is reported in this communication. The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools. In a single NC-layered MOS structure, the role of NCs is more prominent when they are placed closer to SiO2/Si[Formula: see text]substrate interface than to SiO2/Al–gate interface. In MOS structures with larger NC dots and double layered NCs, the charge storage capacity is increased due

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Suh Song, Young, Hyunwoo Kim, Junsu Yu, and Jongho Lee. "Improvement in Self-Heating Characteristic by Utilizing Sapphire Substrate in Omega-Gate-Shaped Nanowire Field Effect Transistor for Wearable, Military, and Aerospace Application." Journal of Nanoscience and Nanotechnology 21, no. 5 (2021): 3092–98. http://dx.doi.org/10.1166/jnn.2021.19149.

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In this study, we propose an omega-shaped-gate nanowire field effect transistor (ONWFET) with a silicon-on-sapphire (SOS) substrate. In order to investigate improvements in the self-heating characteristic with the use of a SOS substrate, the lattice temperature is examined using a Synopsys Sentaurus 3D Technology computer-aided design (TCAD) simulator with the results compared to those with a silicon-on-insulator (SOI) substrate. To validate the proposed structure with the SOS substrate, the locations of hot spots and heat dissipation paths (heat sinks) depending on the substrate materials are

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Palacios A., César, Noemi Guerra, Marco Guevara, and María José López. "TCAD 2D numerical simulations for increasing efficiency of AlGaAs – GaAs Solar Cells." I+D Tecnológico 14, no. 2 (2018): 96–107. http://dx.doi.org/10.33412/idt.v14.2.2078.

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The performance of solar cells has improved quickly in recent years, the latest research focuses on thin cells, multijunction cells, solar cells of the group III-V compounds, Tandem cells, etc. In the present work, numerical simulations are developed, using SENTAURUS TCAD as a tool, in order to obtain a solar cell model based on Galium Arsenide (GaAs). This solar cell corresponds to the so-called "Thin Films" due to the fact that can make layers thinner than we would have if we work with conventional semiconductors, such as; Silicon or Germanium; thus opening the possibility of placing the cel

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Jasurbek Gulomov, Rayimjon Aliev, Murodjon Abduvoxidov, Avazbek Mirzaalimov, and Navruzbek Mirzaalimov. "Exploring optical properties of solar cells by programming and modeling." Global Journal of Engineering and Technology Advances 5, no. 1 (2020): 032–38. http://dx.doi.org/10.30574/gjeta.2020.5.1.0080.

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One of the main factors influencing the efficiency of solar cells is their optical properties. So, most light is reflecting back and transmit through solar cell. This leads to a decrease in the efficiency. We know that the refractive index of silicon is 3-4 depending on the wavelength of light, and the refractive index of air is about 1. This causes to reflect 34 percentages of the incident light. To reduce the amount of reflected light, the surface of the solar cell should be covered with an anti-reflection layer. It is important to determine the conditions of the types and thicknesses of the

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Nguyen, Thi Thanh Huyen, Mihai Lazar, Jean Louis Augé, Hervé Morel, Luong Viet Phung, and Dominique Planson. "Vertical Termination Filled with Adequate Dielectric for SiC Devices in HVDC Applications." Materials Science Forum 858 (May 2016): 982–85. http://dx.doi.org/10.4028/www.scientific.net/msf.858.982.

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Recently, thanks to the advancement in SiC process technology, the deep trench termination (DT2) technique becomes an appropriate choice for future high voltage SiC power device. This technique termination is based on the use of a wide and deep trench, which is filled by a dielectric and associated with a field plate. DT2 technique increases the breakdown voltage (VBR) to a value near to the ideal one that can be obtained in a plan case; and at the same time, reduces drastically the chip area comparing to the previous conventional techniques. In this work, the DT2 used for a 3 kV 4H-SiC bipola

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Mishra, Sikha, Urmila Bhanja, and Guru Prasad Mishra. "An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET." Nanoscience & Nanotechnology-Asia 9, no. 4 (2019): 504–11. http://dx.doi.org/10.2174/2210681208666180820151121.

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Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal w

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Danilenko, Alexander A., Anton V. Strygin, Nikolay I. Mikhailov, et al. "PROGRAMMING 2-BIT PIN DIODE IN SYNOPSYS TCAD." Journal of the Russian Universities. Radioelectronics, no. 5 (December 6, 2018): 51–59. http://dx.doi.org/10.32603/1993-8985-2018-21-5-51-59.

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The article is devoted to the modeling of a two-bit pin-diode. The possibility of programming opening time of the device based on the pin-diode is shown. The design consisting of a pin diode and two floating gates on the surface of i-region is considered. The addition of electrodes to the surface of the i-region makes it possible to regulate the concentration of electrons and holes within the larger limits in compare with the single-gate structure creating enriched and depleted are-as in the structure. Programming is carried out by applying the appropriate voltage to the control electrodes of

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Han, Ke, Shanglin Long, Zhongliang Deng, Yannan Zhang, and Jiawei Li. "A Novel Germanium-Around-Source Gate-All-Around Tunnelling Field-Effect Transistor for Low-Power Applications." Micromachines 11, no. 2 (2020): 164. http://dx.doi.org/10.3390/mi11020164.

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This paper presents a germanium-around-source gate-all-around tunnelling field-effect transistor (GAS GAA TFET). The electrical characteristics of the device were studied and compared with those of silicon gate-all-around and germanium-based-source gate-all-around tunnel field-effect transistors. Furthermore, the electrical characteristics were optimised using Synopsys Sentaurus technology computer-aided design (TCAD). The GAS GAA TFET contains a combination of around-source germanium and silicon, which have different bandgaps. With an increase in the gate-source voltage, band-to-band tunnelli

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Danilenko, A. A., A. D. Ivanov, V. L. Ivanov, V. V. Marochkin, M. N. Ivanovich, and P. V. Vsevolodovich. "The Characteristics of the pin-Structure with a Discrete Metallic Surface i-Region." Journal of the Russian Universities. Radioelectronics 23, no. 1 (2020): 41–51. http://dx.doi.org/10.32603/1993-8985-2020-23-1-41-51.

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Introduction. Currently, an interest in improving pin-structures continues to be the focus of attention of developers of electronic devices. Devices that use controlled pin-structures include: non-volatile memory, static voltage protection device, pin-diodes with adjustable characteristics, etc. However, insufficient attention is paid to the issue of controlling the characteristics of pin-structures by using discrete metallization on the surface of i-region.Aim. Investigation of the influence of discrete metallization of the surface of i-region on static and dynamic characteristics of pin-stru

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Ke, Haotao, Yifan Jiang, Adam J. Morgan, and Douglas C. Hopkins. "Investigation of Package Effects on the Edge Termination E-Field for HV WBG Power Semiconductors." International Symposium on Microelectronics 2017, no. 1 (2017): 000224–30. http://dx.doi.org/10.4071/isom-2017-wa32_092.

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Abstract The edge termination of a power semiconductor is defined as the spatial junction terminations around the edges of the power devices. Guard rings are used to contour the internal depletion regions and E-fields as they terminate at the edge termination, i.e. the intersection of the depletion regions and the wafer saw line where the crystal damage is located. Since there is no specific package for WBG power devices, wire bonds are still widely used to interconnect to the topside metal pads of the power devices. From previous research it is shown that wire bonding will not affect the E-fi

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Prócel, Luis Miguel, and Lionel Trojman. "Simulación TCAD para un MOSFET de silicio en aislante, ultra fino con óxido enterrado y completamente agotado: una comparación entre COMSOL y Sentaurus." ACI Avances en Ciencias e Ingenierías 6, no. 1 (2014). http://dx.doi.org/10.18272/aci.v6i1.163.

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En el presente trabajo, se desarrolla un modelo para simular un dispositivo MOSFET de silicio en aislante, ultra delgados con oxido enterrado (20m) y agotados completamente con SiO2 (5nm) como compuerta. El software que se usa es TCAD-Sentaurus. Se desarrollaron simulaciones DC para estudiar el comportamiento del voltaje de encendido y la transconductancia. Además, se desarrollaron simulaciones AC para estudiar la capacitancia y carga de inversión. Los resultados fueron comparados con un trabajo previo en el que se usó como simulador al programa COMSOL-Multiphysics. Los resultados obtenidos so

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"Model of HfO2/Al2O3 Dielectric ALNINNAlganmos HEMT for Power Application." International Journal of Innovative Technology and Exploring Engineering 9, no. 1 (2019): 3999–4002. http://dx.doi.org/10.35940/ijitee.a5185.119119.

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The work involves to devise dielectric HfO2 /Al2O3MOS-HEMT stack to validate for the device structure through the refinement of mesh analysis. The structure of the AlN\InN\AlGaN HEMT MOS-HEMTs are designed and meshed using the script file in the Sentaurus structure editor. TheAlN\InN\AlGaN MOS-HEMTs output characteristic are examined for physics of MOS-HEMT in Hydrodynamic model TCAD. The amalgamation formation ofthe Al0.30GaN0.70 barrierinterface with the channelofhigh 2DEG density result in anincreaseddrain current density and high trans conductance. Additional the device performance of DC t

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