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Journal articles on the topic 'TCAD Transconductance'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

Morankar, Niraj, Raj Patil, Yash Mahajan, Pranjal Patil, and Santosh Wagaj. "Simulation of Junctionless Transistor for Low Power Mix Circuit." International Journal for Research in Applied Science and Engineering Technology 10, no. 5 (2022): 3874–79. http://dx.doi.org/10.22214/ijraset.2022.43253.

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Abstract: In this work simulation of Double Gate Junction less transistor has been carried out. Comparitive study of the various parameters namely; transconductance(gm), output conductance(gd), DIBL, Subthreshold slope, Ion/Ioff, electric field and Potential. Simulation is carried out in Cogenda Visual TCAD simulator. Comparative study shows using double gate junctionless transistor reduces short channel effect such as DIBL, Subthreshold Slope, Ion/Ioff. Double Gate Junctionless transistor has higher transconductance(gm) and lower output transconductance(gd) compared to conventional junction t

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2

Morankar, Niraj, Raj Patil, Yash Mahajan, Pranjal Patil, and Santosh Wagaj. "Simulation of Junctionless Transistor for Low Power Mix Circuit." International Journal for Research in Applied Science and Engineering Technology 10, no. 5 (2022): 3874–79. http://dx.doi.org/10.22214/ijraset.2022.43253.

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Abstract: In this work simulation of Double Gate Junction less transistor has been carried out. Comparitive study of the various parameters namely; transconductance(gm), output conductance(gd), DIBL, Subthreshold slope, Ion/Ioff, electric field and Potential. Simulation is carried out in Cogenda Visual TCAD simulator. Comparative study shows using double gate junctionless transistor reduces short channel effect such as DIBL, Subthreshold Slope, Ion/Ioff. Double Gate Junctionless transistor has higher transconductance(gm) and lower output transconductance(gd) compared to conventional junction t

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3

K.Ullah, S.Riaz M.Habib F.Abbas S.Naseem I.Shah A.Bukhtiar. "Effect of Channel Doping Concentration on the Impact ionization of nChannel Fully Depleted SOI MOSFET." International Journal of Engineering Works 2, no. 2 (2015): 18–22. https://doi.org/10.5281/zenodo.15756.

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Impact ionization in fully depleted (FD) Silicon On Insulator (SOI) n-Channel MOSFET is investigated as a function of the doping concentration. We have found that impact ionization increases with the decrease in the doping concentration and vice versa. Simulation results obtained from Sentaurus TCAD with the higher doping concentration can control the threshold voltage (Vth). Furthermore we have examined the effect of doping concentration on the transconductance (gm) and have observed that transconductance is inversely proportional of the doping concentration.

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K., Ullah S. Riaz M.Habib F. Abbas S. Naseem G. Abbas. "Effect of High Temperature on the Impact Ionization of N-Channel Fully Depleted SOI MOSFET." International Journal of Engineering Works 1, no. 3 (2014): 48–51. https://doi.org/10.5281/zenodo.15750.

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High temperature effects on the impact ionization of the n-channel fully depleted (FD) SOI MOSFET are investigated over a wide range of temperature from 300 to the 600 K by using TCAD. In particular, we have studied the current voltage characteristics (Id-Vd and Id-Vg ) , threshold voltage (Vth)and transconductance (gm). By the simulation results, we have analyzed that impact ionization decreases with increasing the temperature and vice versa. Furthermore, we have observed that threshold voltage and transconductance are both inversely proportional to the temperature. 

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5

Arafat, I. Sheik, N. B. Balamurugan, and C. Priya. "Effects of Roughness Scattering in Carrier Transport of Near Ballistic Silicon NanoWire MOSFET." Applied Mechanics and Materials 573 (June 2014): 201–8. http://dx.doi.org/10.4028/www.scientific.net/amm.573.201.

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– In this paper, we have investigated the Scattering effects in Carrier Transport of Near-ballistic SiNW MOSFET, which incorporates elastic scattering, optical phonon emission and its combination with Roughness Scattering. Current–voltage (I–V) characteristics of Proposed model is compared with Natori’s Ballistic and Quasi-Ballistic Transport model. We study the impact of Surface Roughness in the device leads on the current variability of a Gate-All-Around (GAA) SiNW MOSFET, which shows a remarkable decrease in electric current, mobility variation and transconductance because of scattered mobi

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Adak, Sarosij, Sanjit Kumar Swain, Hemant Pardeshi, Hafizur Rahaman, and Chandan Kumar Sarkar. "Effect of Barrier Thickness on Linearity of Underlap AlInN/GaN DG-MOSHEMTs." Nano 12, no. 01 (2017): 1750009. http://dx.doi.org/10.1142/s1793292017500096.

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In this proposed work, an extensive study on the linearity performance of underlap AlInN/GaN double gate metal oxide semiconductor high electron mobility transistors (MOS-HEMT) has been analyzed using 2D Sentaurus TCAD simulation. Specifically a brief comparison is made on the linearity and intermodulation distortion characteristics of the proposed device due to variation of barrier layer thickness from 2 nm to 6 nm. Various parameters such as transconductance ([Formula: see text], second-order transconductance ([Formula: see text]), third-order transconductance ([Formula: see text]), second-o

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7

DWIVEDI, A. D. D., and POOJA KUMARI. "TCAD SIMULATION AND PERFORMANCE ANALYSIS OF SINGLE AND DUAL GATE OTFTs." Surface Review and Letters 27, no. 05 (2019): 1950145. http://dx.doi.org/10.1142/s0218625x19501452.

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This paper presents finite element-based numerical simulation and performance analysis of dual and single gate pentacene-based organic thin film transistors (OTFTs) using technology computer-aided design (TCAD) tools. Electrical characteristics of the devices have been simulated using 2D numerical device simulation software ATLAS™ from Silvaco International. Also, device parameters like threshold voltage, mobility, transconductance, subthreshold swing and current on/off ratio of the single and dual gate OTFTs have been extracted and compared.

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Mo, Haifeng, Yaohui Zhang, and Helun Song. "Improving Linearity and Robustness of RF LDMOS by Mitigating Quasi-Saturation Effect." Active and Passive Electronic Components 2019 (July 14, 2019): 1–7. http://dx.doi.org/10.1155/2019/8425198.

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This paper discusses linearity and robustness together for the first time, disclosing a way to improve them. It reveals that the nonlinear transconductance with device working at quasi-saturation region is significant factor of device linearity. The peak electric field is the root cause of electron velocity saturation. The high electric field at the drift region near the drain will cause more electron-hole pairs generated to trigger the parasitic NPN transistor turn-on, which may cause failure of device. Devices with different drift region doping are simulated with TCAD and measured. With LDD4

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9

Osykin, Andrey, Aleksandr Potupchik, and Kirill Panyshev. "Verilog-A model of the impurity freeze-out in LDD regions at cryogenic temperatures." Modeling of systems and processes 16, no. 2 (2023): 93–100. http://dx.doi.org/10.12737/2219-0767-2023-16-2-93-100.

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The article shows the practical implementation of the impurity freeze-out effect in the lightly-doped areas of the drain and source (LDD) in the Verilog-A model of the resistor. This model is based on a theoretical understanding of the freeze-out effect at cryogenic temperatures and data from the TCAD simulation of a MOSFET. The TCAD simulation data were represented by transconductance characteristics of n- and p-channel transistors Id(Vg) in linear mode (Vd=0.1 V) at temperature range from -200 °C to 27 °C for transistors with dimensions 10 um × 10 um. The model is applicable to the use as pa

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10

Bouguenna, Abdellah, Abdelhadi Feddag, Driss Bouguenna, and Ibrahim Farouk Bouguenna. "Comparative Study and Analytical Modeling of AlGaN/GaN HEMT and MOSHEMT Based Biosensors for Biomolecules Detection." East European Journal of Physics, no. 1 (March 3, 2025): 284–89. https://doi.org/10.26565/2312-4334-2025-1-33.

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In this study, a model has been developed to analyze AlGaN/GaN high-electron-transistor (HEMT) and metal-oxide semiconductor high-electron-transistor (MOSHEMT) based biosensors. The model focuses on detecting biomolecules such as ChOx, protein, streptavidin and uricase by modulating the dielectric constant. The sensitivity parameters used for biomolecule detection include drain current, transconductance, and drain off sensitivity. The dielectric constant is adjusted based on the specific biomolecule being sensed by the biosensor. The variation in dielectric leads to changes in drain current, w

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11

Sharma, Sanjeev Kumar, Jeetendra Singh, Balwinder Raj, and Mamta Khosla. "Analysis of Barrier Layer Thickness on Performance of In1–xGaxAs Based Gate Stack Cylindrical Gate Nanowire MOSFET." Journal of Nanoelectronics and Optoelectronics 13, no. 10 (2018): 1473–77. http://dx.doi.org/10.1166/jno.2018.2374.

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In this paper, InGaAs/InP heterostructure based Cylindrical Gate Nanowire MOSFETs (CGNWMOSFET) is designed and its performance has been analyzed using silvaco ATLAS TCAD tool. The influence of the barrier thickness is investigated for perusal performance of an InGaAs/InP heterostructure CGNWMOSFET. The performance compared for various parameters on current, off current, Cut off Frequency (fT), Transconductance (gm), Gate to Source capacitance (Cgs), and Gate to Drain capacitance (Cgd). Results show significant variation in the performance of InGaAs/InP heterostructure CGNWMOSFET by varying the

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Ahn, Tae Jun, and Yun Seop Yu. "Electrical Coupling of Monolithic 3D Inverters (M3INVs): MOSFET and Junctionless FET." Applied Sciences 11, no. 1 (2020): 277. http://dx.doi.org/10.3390/app11010277.

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In this paper, we investigated the electrical coupling between the top and bottom transistors in a monolithic 3-dimensional (3D) inverter (M3INV) stacked vertically with junctionless field-effect transistor (JLFET), which is one of candidates to replace metal-oxide-semiconductor field-effect transistors (MOSFET). Currents, transconductances, and gate capacitances of the top N-type transistor at the different gate voltages of the bottom P-type transistor as a function of thickness of inter-layer dielectric (TILD) and gate channel length (Lg) are simulated using technology computer-aided-design

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Bora, N., N. Deka, and R. Subadar. "Quantum Mechanical Analysis on Modeling of Surface Potential and Drain Current for Nanowire JLFET." Journal of Nano Research 64 (November 2020): 123–34. http://dx.doi.org/10.4028/www.scientific.net/jnanor.64.123.

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This paper presents an analytical model for ultra scaled symmetric double gate (SDG) nanowire junctionless field effect transistor (JLFET), which includes charge quantization in all the regions of operation. This model is based on a first-order correction for the confined energies obtained by solving the Schrodinger’s equation. The model is able to predict the quantum mechanical effects (QME) on the surface potential, drain current and transconductance for a highly doped and extremely thin silicon layer of thickness down to 4nm. The results obtained are validated by comparing with GENIUS 3D TC

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14

Das, Sanat, Bibek Chettri, Prasanna Karki, Bhakta Kunwar, Pronita Chettri, and Bikash Sharma. "Impact of high-k metal oxide as gate dielectric on the certain electrical properties of silicon nanowire field-effect transistors: A simulation study." Facta universitatis - series: Electronics and Energetics 36, no. 4 (2023): 553–65. http://dx.doi.org/10.2298/fuee2304553d.

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Standard Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are gaining prominence in low-power nanoscale applications. This is largely attributed to their proximity to physical and thermal limits, rendering them a compelling option for energy-efficient electronic devices. In this study, we hypothesized that the high-? HfO2 in a quasi-ballistic SiNW MOSFET acts as the gate dielectric. In this case, the data from the TCAD simulation and the model demonstrated exceptional agreement. The proposed model for a SiNW MOSFET with high-? HfO2 exhibits a consistently increasing drain current,

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15

Vimala, Palanichamy, and T. S. Arun Samuel. "A Simulation Study on the Impact of InP Barrier on InGaAs/InP Hetero Junction Gate all around MOSFET." Journal of Nano Research 60 (November 2019): 113–23. http://dx.doi.org/10.4028/www.scientific.net/jnanor.60.113.

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In this work, we have analyzed the digital and analog performance for InGaAs/InP heterojunction Gate all around MOS structure. A detailed study on the impact of Barrier thickness on different analog and digital performance for an InGaAs/InP hetero structure GAA MOSFET is carried out by using TCAD device simulation. The electrical parameters such as surface potential, electric field, transfer characteristics, output characteristics, transconductance and output conductance is carried out and analyzed by varying the barrier thickness from 1 nm to 4 nm. Based on the simulation results it is invest

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16

Bora, N., N. Deka, and R. Subadar. "A Drain Current and Transconductance Analytical Model for Symmetric Double Gate Junctionless FENT." Journal of Nano Research 65 (December 2020): 39–50. http://dx.doi.org/10.4028/www.scientific.net/jnanor.65.39.

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This paper presents an analytical model of various electrical parameters for an ultra thin symmetric double gate (SDG) junctionless field effect nanowire transistor (JLFENT). The model works for all the regions of operation of the nanowire transistor without using any fitting parameter. The surface potential is derived based on the solutions of Poisson’s and current continuity equations by using appropriate boundary conditions. The Pao–Sah double integral was used to obtain the drain current, transconductance and drain conductance. The results obtained from analytical model are validated by co

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17

Zhu, Shunwei, Hujun Jia, Tao Li, et al. "Novel High-Energy-Efficiency AlGaN/GaN HEMT with High Gate and Multi-Recessed Buffer." Micromachines 10, no. 7 (2019): 444. http://dx.doi.org/10.3390/mi10070444.

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A novel AlGaN/GaN high-electron-mobility transistor (HEMT) with a high gate and a multi-recessed buffer (HGMRB) for high-energy-efficiency applications is proposed, and the mechanism of the device is investigated using technology computer aided design (TCAD) Sentaurus and advanced design system (ADS) simulations. The gate of the new structure is 5 nm higher than the barrier layer, and the buffer layer has two recessed regions in the buffer layer. The TCAD simulation results show that the maximum drain saturation current and transconductance of the HGMRB HEMT decreases slightly, but the breakdo

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18

Baral, Biswajit, Sudhansu Mohan Biswal, Debashis De, and Angsuman Sarkar. "Radio frequency/analog and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor." SIMULATION 93, no. 11 (2017): 985–93. http://dx.doi.org/10.1177/0037549717704308.

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The analog/radio frequency (RF) and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor (JL DGMOS) is investigated using the numerical TCAD device simulator. JL DGMOSs have shown great promise for high-performance digital applications due to their superior short channel effect performance and ease of fabrication. In analog and RF circuit applications, linearity testing and RF performance is a major issue that is encountered due to non-linear behavior of the devices. Therefore, in this paper, different RF/analog and linearity performance figures

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19

Sun, Zhonghao, Huolin Huang, Nan Sun, Pengcheng Tao, Cezhou Zhao, and Yung C. Liang. "A Novel GaN Metal-Insulator-Semiconductor High Electron Mobility Transistor Featuring Vertical Gate Structure." Micromachines 10, no. 12 (2019): 848. http://dx.doi.org/10.3390/mi10120848.

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A novel structure scheme by transposing the gate channel orientation from a long horizontal one to a short vertical one is proposed and verified by technology computer-aided design (TCAD) simulations to achieve GaN-based normally-off high electron mobility transistors (HEMTs) with reduced on-resistance and improved threshold voltage. The proposed devices exhibit high threshold voltage of 3.1 V, high peak transconductance of 213 mS, and much lower on-resistance of 0.53 mΩ·cm2 while displaying better off-state characteristics owing to more uniform electric field distribution around the recessed

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20

Boursali, Amin, Ahlam Guen-Bouazza, and Choukria Sayah. "DC and RF characteristics of 20 nm gate length InAlAs/InGaAs/InP HEMTs for high frequency application." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1248. http://dx.doi.org/10.11591/ijece.v10i2.pp1248-1254.

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lnAlAs/lnGaAs/InP high electron mobility transistor (HEMT) offers excellent high frequency operation.In this work,the DC and RF performance of a 20 nm gate length enhancement mode InAlAs/InGaAs/InP high electron mobility transistor (HEMT) on InP substrate are presented.The SILVACO-TCAD simulations performed at room temperature using the appropriate model sshowed that the studied device exhibit excellent pinch-off characteristics, with a maximum transconductance of 1100ms/mm, a threshold voltage of 0,62V, and an Ion/Ioff ratio of 2.106. The cut-off frequency and maximum frequency of oscillation

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Amin, Boursali, Guen-Bouazza Ahlam., and Sayah Choukria. "DC and RF characteristics of 20 nm gate length InAlAs/InGaAs/InP HEMTs for high frequency application." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (2020): 1248–54. https://doi.org/10.11591/ijece.v10i2.pp1248-1254.

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lnAlAs/lnGaAs/InP high electron mobility transistor (HEMT) offers excellent high frequency operation.In this work, the DC and RF performance of a 20 nm gate length enhancement mode InAlAs/InGaAs/InP high electron mobility transistor (HEMT) on InP substrate are presented. The SILVACO-TCAD simulations performed at room temperature using the appropriate model sshowed that the studied device exhibit excellent pinch-off characteristics, with a maximum transconductance of 1100ms/mm, a threshold voltage of 0,62V, and an Ion/Ioff ratio of 2.106. The cut-off frequency and maximum frequency of oscillati

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22

Hind, Jaafar, Aouaj Abdellah, Bouziane Ahmed, and Iñiguez Benjamin. "A compact model of transconductance and drain conductance for DMG-GC-DOT cylindrical gate MOSFET." International Journal of Reconfigurable and Embedded Systems 9, no. 1 (2020): 34–41. https://doi.org/10.11591/ijres.v9.i1.pp34-41.

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A compact model for dual-material gate graded-channel and dual-oxide thickness with two dielectric constant different cylindrical gate (DMG-GCDOTTDCD) MOSFET was investigated in terms of transconductance, drain conductance and capacitance. Short channel effects are modeled with simple expressions, and incorporated into the core of the model (at the drain current). The design effectiveness of DMG-GC-DOTTDCD was monitored in comparing with the DMG-GC-DOT transistor, the effect of variations of technology parameters, was presented in terms of gate polarization and drain polarization. The results

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23

Firas, Natheer Abdul-kadir, khaleel Mohammad Khalid, and Hashim Yasir. "Investigation and design of ion-implanted MOSFET based on (18 nm) channel length." TELKOMNIKA Telecommunication, Computing, Electronics and Control 18, no. 5 (2020): 2635~2641. https://doi.org/10.12928/TELKOMNIKA.v18i5.15958.

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The aim of this study is to invistgate the characteristics of Si-MOSFET with 18 nm length of ion implemented channel. Technology computer aided design (TCAD) tool from Silvaco was used to simulate the MOSFET’s designed structure in this research. The results indicate that the MOSFET with 18 nm channel length has cut-off frequency of 548 GHz and transconductance of 967 μS, which are the most important factors in calculating the efficiency and improving the performance of the device. Also, it has threshold voltage of (-0.17 V) in addition obtaining a relatively small DIBL (55.11 mV/V).

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Mohapatra, Sushanta, Kumar Pradhan, and Prasanna Sahu. "ZTC bias point of advanced fin based device: The importance and exploration." Facta universitatis - series: Electronics and Energetics 28, no. 3 (2015): 393–405. http://dx.doi.org/10.2298/fuee1503393m.

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The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25?C to 225?C is reviewed to extend the benchmark of device scalability. The impact of fin height (HFin), fin width (WFin), and temperature (T) on immense performance metrics including on-off ratio (Ion/Ioff), transconductance (gm), gain (AV), cut-off frequency (fT), static po

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25

Sh. HUSSEIN, A., Z. HASSAN, H. ABU HASSAN, and S. M. THAHAB. "ELECTRICAL PROPERTIES OF AlGaN/GaN HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS (HFETs) WITH AND WITHOUT Mg-DOPED CARRIER CONFINEMENT LAYER." International Journal of Nanoscience 09, no. 04 (2010): 263–67. http://dx.doi.org/10.1142/s0219581x10006776.

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AlGaN/GaN -based heterostructure field-effect transistors (HFETs) with and without Mg -doped semi-insulating carrier confinement layer were simulated by using ISE TCAD software, respectively. The detailed study on the electrical properties of these samples was performed. The effect of inserting Mg -doped GaN layer on the source–drain (S–D) leakage current was investigated. Higher values of drain current and extrinsic transconductance were achieved with conventional HFETs (without Mg -doped). The source-to-drain (S–D) leakage current of conventional HFETs was also higher. However, the S–D leaka

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Yadav, Rahis Kumar, Pankaj Pathak, and R. M. Mehra. "TCAD Simulations and Small Signal Modeling of DMG AlGaN/GaN HFET." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1839. http://dx.doi.org/10.11591/ijece.v7i4.pp1839-1849.

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This article presents extraction of small signal model parameters and TCAD simulation of novel asymmetric field plated dual material gate AlGaN/GaN HFET first time. Small signal model is essential for design of LNA and microwave electronic circuit by using the proposed superior performance HFET structure. Superior performances of device are due to its dual material gate structure and field plate that can provide better electric field uniformity, suppression of short channel effects and improvement in carrier transport efficiency. In this article we used direct parameter extraction methodology

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27

Rahis, Kumar Yadav, Pathak Pankaj, and M. Mehra R. "TCAD Simulations and Small Signal Modeling of DMG AlGaN/GaN HFET." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1839–49. https://doi.org/10.11591/ijece.v7i4.pp1839-1849.

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This article presents extraction of small signal model parameters and TCAD simulation of novel asymmetric field plated dual material gate AlGaN/GaN HFET first time. Small signal model is essential for design of LNA and microwave electronic circuit by using the proposed superior performance HFET structure. Superior performances of device are due to its dual material gate structure and field plate that can provide better electric field uniformity, suppression of short channel effects and improvement in carrier transport efficiency. In this article we used direct parameter extraction methodology

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Sahoo, Sasmita, Sidhartha Dash, and Guru P. Mishra. "An Accurate Drain Current Model for Symmetric Dual Gate Tunnel FET Using Effective Tunneling Length." Nanoscience &Nanotechnology-Asia 9, no. 1 (2018): 85–91. http://dx.doi.org/10.2174/2210681207666170612081017.

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Introduction: Here we propose an accurate drain current model for a Symmetric Dual Gate Tunnel FET (SDG-TFET) using effective tunneling length and generation rate of carrier over tunneling junction area. Analytical Modeling: The surface potential of the model is obtained by solving 2-dimensional Poisson’s equation and further extends to determine the magnitude of initial tunneling length and final tunneling length. The different DC performance indicators like drain current (ID), threshold voltage (Vth), transconductance (gm) and Subthreshold Slope (SS) for the present model are extensively inv

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Jayachandran, Remya, Dhanaraj Jagalchandran, and Perinkolam Chidambaram Subramaniam. "Planar CMOS and multigate transistors based wide-band OTA buffer amplifiers for heavy resistance load." Facta universitatis - series: Electronics and Energetics 35, no. 1 (2022): 13–28. http://dx.doi.org/10.2298/fuee2201013j.

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Analog buffer amplifier configurations capable of driving heavy resistive load using different operational transconductance amplifier (OTA) are presented in this paper. The OTA CMOS buffer configurations are designed using 0.18 ?m SCL technology library in Cadence Virtuoso tool and multigate transistor OTA buffer in TCAD Sentaurus tool. CMOS OTA buffer configuration using simple OTA outperform the OTA buffer circuits using other OTAs in terms of power dissipation and stability. Measured results show that the OTA buffer circuit works well for resistive load below 100 ?. The gain tuning of up to

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Oliveira, Alberto Vinícius, Guilherme Vieira Gonçalves, Paula Ghedini Der Agopian, et al. "Ground Plane Impact on Performance of Relaxed Ge FinFETs." Journal of Integrated Circuits and Systems 14, no. 1 (2019): 1–6. http://dx.doi.org/10.29292/jics.v14i1.55.

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The implementation of a barrier potential layer underneath the channel region, well known as Ground Plane (GP) implantation, and its influence on the performance of relaxed germanium pFinFET devices is investigated in this manuscript. This study aims to explain the fin width dependence of the threshold voltage from experimental data and evaluates the ground plane doping concentration and its depth influence on relaxed p-type channel germanium FinFET parameters, as threshold voltage, transconductance and subthreshold swing, through Technology Computer-Aided Design (TCAD) numerical simulations.

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Jia, Hujun, Yuan Liang, Tao Li, et al. "Improved DRUS 4H-SiC MESFET with High Power Added Efficiency." Micromachines 11, no. 1 (2019): 35. http://dx.doi.org/10.3390/mi11010035.

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A 4H-SiC metal semiconductor field effect transistor (MESFET) with layered doping and undoped space regions (LDUS-MESFET) is proposed and simulated by ADS and ISE-TCAD software in this paper. The structure (LDUS-MESFET) introduced layered doping under the lower gate of the channel, while optimizing the thickness of the undoped region. Compared with the double-recessed 4H-SiC MESFET with partly undoped space region (DRUS-MESFET), the power added efficiency of the LDUS-MESFET is increased by 85.8%, and the saturation current is increased by 27.4%. Although the breakdown voltage of the device has

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32

Suresh Babu, T., and U. Saravanakumar. "AlGaN/GaN High Electron Mobility Transistor (HEMT)-Based Dual-Metal Gate Architecture for Biosensing Applications." Journal of Nanoelectronics and Optoelectronics 19, no. 11 (2024): 1201–8. https://doi.org/10.1166/jno.2024.3683.

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The electrical characteristics and sensitivity of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistor (MOSHEMTs) with dual metal single gate (DMSG) architecture are investigated and compared via Sentaurus technology computer aided design (TCAD) simulations with conventional single metal single gate (SMSG) devices. This technique reduces gate leakage and current collapse by using aluminium oxide as a high-k dielectric. Simulation results clearly reveal that DMSG devices exhibit superior performance with high drain current, high transconductance, and improved sensitivity compar

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33

Jaafar, Hind, Abdellah Aouaj, and Benjamin Iñiguez. "A compact model of transconductance and drain conductance for DMG-GC-DOT cylindrical gate MOSFET." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 1 (2020): 34. http://dx.doi.org/10.11591/ijres.v9.i1.pp34-41.

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A compact model for dual-material gate graded-channel and dual-oxide<br />thickness with two dielectric constant different cylindrical gate (DMG-GC-<br />DOTTDCD) MOSFET was investigated in terms of transconductance, drain<br />conductance and capacitance. Short channel effects are modeled with simple<br />expressions, and incorporated into the core of the model (at the drain<br />current). The design effectiveness of DMG-GC-DOTTDCD was monitored<br />in comparing with the DMG-GC-DOT transistor, the effect of variations of<br />technology parameters, w

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Nawaz, Muhammad, and Filippo Chimento. "On the TCAD Based Design Diagnostic Study of 4H-SiC Based IGBTs." Materials Science Forum 778-780 (February 2014): 1034–37. http://dx.doi.org/10.4028/www.scientific.net/msf.778-780.1034.

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This paper addresses the design diagnostic study of 4H-SiC based IGBTs using two dimensional numerical computer simulations. Using identical set of physical device parameters (doping, thicknesses), simulated structure was first calibrated with the experimental data. A minority carrier life time in the drift layer of 1.0 1.6 μs and contact resistivity of 0.5 - 1.0 x 10-4 Ω-cm2 produces a close match with the experimental device. A decay in the device transconductance and threshold voltage is observed with increasing temperature. The on-resistance first decays with temperature (i.e., increased i

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Lazzaz, Abdelaziz, Khaled Bousbahi, and Mustapha Ghamnia. "Performance analysis and optimization of 10 nm TG N- and P-channel SOI FinFETs for circuit applications." Facta universitatis - series: Electronics and Energetics 35, no. 4 (2022): 619–34. http://dx.doi.org/10.2298/fuee2204619l.

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This paper analyses the electrical characteristics of 10 nm tri-gate (TG) N- and P-channel silicon-on-insulator (SOI) FinFETs with hafnium oxide gate dielectric. The analysis has been performed through simulations by using Silvaco ATLAS TCAD with the Bohm quantum potential (BQP) algorithm. The influence of the geometrical parameters on the threshold voltage VTH, the subthreshold swing (SS), the transconductance and the on/off current ratio, ION/IOFF, is investigated. The two structures have been optimized for CMOS inverter implementation. The simulation results show that the N-FinFET and the P

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Oh, Jong Hyeok, and Yun Seop Yu. "Electrical Coupling for Monolithic 3-D Integrated Circuit Consisting of Feedback Field-Effect Transistors." Journal of Nanoscience and Nanotechnology 21, no. 8 (2021): 4293–97. http://dx.doi.org/10.1166/jnn.2021.19387.

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In this study, for two cases of monolithic 3-dimensional integrated circuit (M3DIC) consisting of vertically stacked feedback field-effect transistors (FBFETs), the variation of electrical characteristics of the FBFET was presented in terms of electrical coupling by using technology computer aided design (TCAD) simulation. In the Case 1, the M3DIC was composed with an N-type FBFET in an upper tier (tier2) and a P-type FBFET in a lower tier (tier1), and in the Case 2, it was composed with the FBFETs of opposite type of the Case 1 on each tier. To utilize the FBFET as a logic device, the study o

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Lv, Beibei, Lixing Zhang, and Jiongjiong Mo. "Asymmetric GaN High Electron Mobility Transistors Design with InAlN Barrier at Source Side and AlGaN Barrier at Drain Side." Electronics 13, no. 3 (2024): 653. http://dx.doi.org/10.3390/electronics13030653.

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The InAlN/GaN HEMT has been identified as a promising alternative to conventional AlGaN/GaN HEMT due to its enhanced polarization effect contributing to higher 2DEG in the GaN channel. However, the InAlN barrier usually suffers from high leakage and therefore low breakdown voltage. In this paper, we propose an asymmetrical GaN HEMT structure which is composed of an InAlN barrier at the source side and an AlGaN barrier at the drain side. This novel device combines the advantages of high 2DEG density at the source side and low electrical-field crowding at the drain side. According to the TCAD si

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Fatma M. Mahmoud. "GaN-HEMT Performance Enhancement." Journal of Electrical Systems 20, no. 2 (2024): 1426–35. http://dx.doi.org/10.52783/jes.1442.

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In this work, a simulation analysis and calibration are carried out to improve the performance of AlGaN/GaN- MOSHEMTs (Metal-Oxide Semiconductor High Electron Mobility Transistors). The effect of the AlGaN layer thickness, gate length, Al mole fraction, and the interface traps on the electrical performance of the device has been presented. Device simulations have been done using Sentaurus technology computer-aided design (TCAD). The simulations and analysis show better drain current, transconductance, and cut-off frequency performance. The maximum cut-off frequency shown by the proposed HEMT d

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Hamida, Djelti. "Numerical investigation of the performance of AlGaN/GaN/BGaN double-gate double-channel high electron mobility transistor." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 3 (2022): 2655–62. https://doi.org/10.11591/ijece.v12i3.pp2655-2662.

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In this work, we examine the direct-current (DC) behavior and the radio frequency (RF) performance of both single-gate simple-channel (SGSC), single-gate double-channel (SGDC) and double-gate double-channel (DGDC) AlGaN/GaN/BGaN high electron mobility transistor (HEMT) with BGaN back-barriers consist of 250 nm gate length. Using technology computer aided design (TCAD) Silvaco, our isothermal simulation results reveal that the proposed structure of double-gate double-channel HEMT with BGaN back-barriers (DGDCBB HEMT) increases electron concentration and consequently the saturation drain current

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Chowdhury, Md. Iqbal Bahar. "Silvaco TCAD based Analysis of Cylindrical Gate -All-Around FET Having Indium Arsenide as channel and Aluminium Oxide as Gate Dielectrics." Journal of Nanotechnology and its Applications in Engineering 1, no. 1 (2025): 1–12. https://doi.org/10.5281/zenodo.15318861.

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In this work, a cylindrical gate-all-around (CGAA) FET (field-effect transistor) structure with Indium Arsenide (InAs) nanowire is used as channel instead of silicon nanowire, and aluminium oxide is used as the gate dielectrics instead of silicon dioxide. The performance of this setup was demonstrated using ATLAS simulator of Silvaco TCAD software. Indium Arsenide is chosen due to its high electron velocity, high saturation velocity and low contact resistance, whereas, aluminium oxide is chosen because of its higher permittivity. Simulation results indicate that the proposed combination is sup

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Hadjem, Dalila, Zakarya Kourdi, and Salim Kerai. "The optimization of a GaN-based current aperture vertical electron transistor." International Journal of Power Electronics and Drive Systems (IJPEDS) 15, no. 2 (2024): 651–58. https://doi.org/10.11591/ijpeds.v15.i2.pp651-658.

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The main objective of this paper is to simulate and optimize a current aperture vertical electron transistor (CAVET) based on gallium nitride (GaN), which combines both a two-dimensional electron gas (2DEG) and a vertical structure using the SILVACO-TCAD simulator. The dimensions of the structure were reduced by 45% to minimize the size and improve the performances of the proposed device; also, a part of aluminum nitride (AlN)was added to the current blocking layer (CBL) to modulate the conduction band profile. The results obtained from the simulation of our structure demonstrated a maximum dr

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Abdul-kadir, Firas Natheer, and Faris Hassan Taha. "Characterization of silicon tunnel field effect transistor based on charge plasma." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 1 (2022): 138–43. https://doi.org/10.11591/ijeecs.v25.i1.pp138-143.

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The aim of the proposed paper is an analytical model and realization of the characteristics for tunnel field-effect transistor (TFET) based on charge plasma (CP). One of the most applications of the TFET device which operates based on CP technique is the biosensor. CP-TFET is to be used as an effective device to detect the uncharged molecules of the bio-sample solution. Charge plasma is one of some techniques that recently invited to induce charge carriers inside the devices. In this proposed paper we use a high work function in the source (ϕ=5.93 eV) to induce hole charges and we use a lower

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Djelti, Hamida. "Numerical investigation of the performance of AlGaN/GaN/BGaN double-gate double-channel high electron mobility transistor." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 3 (2022): 2655. http://dx.doi.org/10.11591/ijece.v12i3.pp2655-2662.

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<p><span>In this work, we examine the direct-current (DC) behavior and the radio-frequency (RF) performance of both single-gate simple-channel (SGSC), single-gate double-channel (SGDC) and double-gate double-channel (DGDC) AlGaN/GaN/BGaN high electron mobility transistor (HEMT) with BGaN back-barriers consist of 250 nm gate length. Using Technologie Computer Aided Design (TCAD) Silvaco, our isothermal simulation results reveal that the proposed structure of double-gate double-channel HEMT with BGaN back-barriers (DGDCBB HEMT) increases electron concentration and consequently the sa

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44

Seo, Jae Hwa, Young Jun Yoon, Seongjae Cho, Heung-Sik Tae, Jung-Hee Lee, and In Man Kang. "Analyses on RF Performances of Silicon-Compatible InGaAs-Based Planar-Type and Fin-Type Junctionless Field-Effect Transistors." Journal of Nanoscience and Nanotechnology 15, no. 10 (2015): 7615–19. http://dx.doi.org/10.1166/jnn.2015.11141.

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The In0.53Ga0.47As-based planar-type junctionless fieled-effect transistor (JLFET) and fin-type FET (FinFET) have been designed and characterized by technology computer-aided design (TCAD) simulations. Because of their attractive material characteristics, the combination of In0.53Ga0.47As and InP has been adopted in some of the most recent semiconductor devices. In particular, the In0.53Ga0.47As-based transistor using an InP buffer is highly attractive due to its superior electrostatic performance which results from the by particular characteristics of the In0.53Ga0.47As material. In this pape

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45

Hadjem, Dalila, Zakarya Kourdi, and Salim Kerai. "The optimization of a GaN-based current aperture vertical electron transistor." International Journal of Power Electronics and Drive Systems (IJPEDS) 15, no. 2 (2024): 651. http://dx.doi.org/10.11591/ijpeds.v15.i2.pp651-658.

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The main objective of this paper is to simulate and optimize a current aperture vertical electron transistor (CAVET) based on gallium nitride (GaN), which combines both a two-dimensional electron gas (2DEG) and a vertical structure using the SILVACO-TCAD simulator. The dimensions of the structure were reduced by 45% to minimize the size and improve the performances of the proposed device; also, a part of aluminum nitride (AlN)was added to the current blocking layer (CBL) to modulate the conduction band profile. The results obtained from the simulation of our structure demonstrated a maximum dr

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46

Hamady, Saleem, Bilal Beydoun, and Frédéric Morancho. "TCAD-Based Analysis on the Impact of AlN Interlayer in Normally-off AlGaN/GaN MISHEMTs with Buried p-Region." Electronics 14, no. 2 (2025): 313. https://doi.org/10.3390/electronics14020313.

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With the growing demand for more efficient power conversion and silicon reaching its theoretical limit, wide bandgap semiconductor devices are emerging as a potential solution. For instance, Gallium Nitride (GaN)-based high-electron-mobility transistors (HEMTs) are getting more attention, and several structures for the normally off operation have been proposed. Adding an AlN interlayer in conventional AlGaN/GaN normally on HEMT structures is known to enhance the current density. In this work, the effect of an AlN interlayer in the normally off AlGaN/GaN MISHEMT with a buried p-region was inves

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deva, shalini, and Prashanth Kumar. "High-Frequency Performance Characteristics of the Double-Gate Schottky Barrier Tunnel Field Effect Transistor in Analog and Radio-Frequency Applications." ECS Journal of Solid State Science and Technology, August 15, 2023. http://dx.doi.org/10.1149/2162-8777/acf071.

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Abstract A novel structure of double gate Schottky barrier tunnel field effect transistor (DG-SBTFET) has been designed and simulated. The DG-SBTFET has two sources (NiSi) and two gate metals with an HfO2. Silvaco-TCAD simulator has been used for investigating the analog and radio frequency performance of the DG-SBTFET. The proposed device is compared with the conventional devices in terms of electrical parameters including ION current, ION/IOFF ratio, RF performance including transconductances, cut-off frequency, transit time, gain bandwidth product, transconductance generation factor, and tr

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Jaisawal, Rajeewa Kumar, Sunil Rathore, Navneet Gandhi, Pravin N. Kondekar, and Navjeet Bagga. "Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET." Semiconductor Science and Technology, September 15, 2022. http://dx.doi.org/10.1088/1361-6641/ac9250.

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Abstract Temperature plays a decisive role in semiconductor device performance and reliability analysis. The effect is more severe in a Negative Capacitance (NC) transistor, as the temperature modulates the ferroelectric polarization, implicitly included by the Landau coefficients (α, β, γ) in TCAD. In this paper, through TCAD simulations, the role of varying ambient temperature is investigated in the linearity and analog/RF merits of NC-FinFET. The varying temperature modulates the carrier mobility, the semiconductor bandgap, and the Landau parameter (α). We analyzed the analog/RF and lineari

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Shalini, V., and Prashanth Kumar. "Temperature‐Induced Changes in Multifin‐Schottky Barrier FinFETs: An Analog/RF Linearity Investigation." Advanced Theory and Simulations, October 10, 2024. http://dx.doi.org/10.1002/adts.202400531.

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AbstractIn this script, a Gallium Nitride (GaN)‐based FinFET structure is proposed with a multi‐channel device that is designed and simulated. Here, the 3D‐Sentaures TCAD simulator is used to investigate the analog/radio frequency performance and linearity of the MultiFin‐Schottky Barrier FinFET with different temperatures of 100–400 K. The proposed device underwent a temperature analysis, where critical parameters include drain current, ION/IOFF ratio, Transconductance (gm), higher‐order terms (gm2 and gm3), Gain Bandwidth Product (GBP), Cut‐off Frequency (fT), Transit Time (τ), Transconducta

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Singh, Abhay Pratap, Vibhuti Chauhan, R. K. Baghel, and Sukeshni Tirkey. "Enhancing VLSI Design Efficiency With ML‐Based C‐ANN: Performance Optimization of Gate‐Stacked Ferroelectric FE‐MOSFETs for High‐Speed and RF Applications." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 38, no. 3 (2025). https://doi.org/10.1002/jnm.70064.

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ABSTRACTThis study presents an innovative approach leveraging TCAD simulations and a Convolutional Artificial Neural Network (C‐ANN) to address challenges in VLSI design. A statistical sample of 4000 distinct values was simulated to predict drain current (Ids), achieving a dramatic reduction in runtime from 46 to 48 days (conventional TCAD) to just 100–120 s using the proposed ML‐based C‐ANN. The proposed gate‐stacking SiO2 + HfO2 FE‐MOSFET device demonstrates significant advancements, including reductions in short‐channel effects (SCEs), subthreshold swing (SS) by 3.12%–4.04%, and drain‐induc

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