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Journal articles on the topic 'Technologie FDSOI - Fully Depleted Silicon On Insulator'

Author: Grafiati

Published: 4 June 2021

Last updated: 10 February 2022

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1

Klewer, Christian, Frank Kuechenmeister, Jens Paul, et al. "Package Qualification Envelope for 22FDX® Technology." International Symposium on Microelectronics 2019, no. 1 (2019): 000169–75. http://dx.doi.org/10.4071/2380-4505-2019.1.000169.

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Abstract This article describes the methodology used to derive the 22FDX® Fully-Depleted Silicon-On-Insulator (FDSOI) Chip Package Interaction (CPI) qualification envelope. In the first part it is discussed how the individual market segments influence the technology features and offerings, including BEOL stacks and package types. In the following, the criteria used for the selection of BEOL stacks, die and package sizes and the interconnect type for the qualification envelope are summarized and explained. The three CPI qualification stages and related characterization methods are presented. CP

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2

Kambham, Ajay Kumar, Dan Flatoff, and Bianzhu Fu. "Application of Atom Probe on Fully Depleted Silicon-On-Insulator (FDSOI) Structures." Microscopy and Microanalysis 22, S3 (2016): 696–97. http://dx.doi.org/10.1017/s1431927616004335.

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3

Lin, Jyi-Tsong, Yi-Chuen Eng, and Po-Hsieh Lin. "A Novel Nanoscale FDSOI MOSFET with Block-Oxide." Active and Passive Electronic Components 2013 (2013): 1–9. http://dx.doi.org/10.1155/2013/627873.

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We demonstrate improved device performance by applying oxide sidewall spacer technology to a block-oxide-enclosed Si body to create a fully depleted silicon-on-insulator (FDSOI) nMOSFET, which overcomes the need for a uniform ultrathin silicon film. The presence of block-oxide along the sidewalls of the Si body significantly reduces the influence of drain bias over the channel. The proposed FDSOI structure therefore outperforms conventional FDSOI with regard to its drain-induced barrier lowering (DIBL), on/off current ratio, subthreshold swing, and threshold voltage rolloff. The new FDSOI stru

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4

Wang, Hanbin, Jinshun Bi, Mengxin Liu, and Tingting Han. "Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure." Electronics 10, no. 13 (2021): 1585. http://dx.doi.org/10.3390/electronics10131585.

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This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/p

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5

Olejarz, Piotr, Kyoungchul Park, Samuel MacNaughton, Mehmet R. Dokmeci, and Sameer Sonkusale. "0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process." Journal of Low Power Electronics and Applications 2, no. 2 (2012): 155–67. http://dx.doi.org/10.3390/jlpea2020155.

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6

Almeida, Luciano M., Katia R. A. Sasaki, M. Aoulaiche, Eddy Simoen, Cor Clayes, and João Antonio Martino. "One Transistor Floating Body RAM Performances on UTBOX Devices Using the BJT Effect." Journal of Integrated Circuits and Systems 7, no. 2 (2012): 113–20. http://dx.doi.org/10.29292/jics.v7i2.363.

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This work aims to analyze through 2D numerical simulations the minimum drain bias for the onset of the parasitic bipolar transistor (BJT) effect (VLatch) of a Ultra-Thin-Buried-Oxide (UTBOX) Fully-Depleted-Silicon-on-Insulator (FDSOI) transistor used as a Single-Transistor-Dynamic-Random-Access-Memory (1TDRAM) cell at high temperatures. The buried oxide thickness (tBOX) and silicon film thickness (tSi) variation were also taken into account and initial studies of the retention time (RT) and the data degradation have been performed. It was verified that the latch voltage, the sense margin curre

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7

Litty, Antoine, Sylvie Ortolland, Dominique Golanski, Christian Dutto, Alexandres Dartigues, and Sorin Cristoloveanu. "Towards High-Voltage MOSFETs in Ultrathin FDSOI." International Journal of High Speed Electronics and Systems 25, no. 01n02 (2016): 1640005. http://dx.doi.org/10.1142/s012915641640005x.

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High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides

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8

Xu, Jingyan, Yang Guo, Ruiqiang Song, Bin Liang, and Yaqing Chi. "Supply Voltage and Temperature Dependence of Single-Event Transient in 28-nm FDSOI MOSFETs." Symmetry 11, no. 6 (2019): 793. http://dx.doi.org/10.3390/sym11060793.

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Based on three-dimensional (3D) technology computer aided design (TCAD) simulations, the supply voltage and temperature dependence of single-event transient (SET) pulse width in 28-nm fully-depleted silicon-on-insulator (FDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated. FDSOI MOSFETs are symmetry devices with a superior control of the short channel effects (SCEs) and single-event effects (SEEs). Previous studies have suggested that the SET width is invariant when the temperature changes in FDSOI devices. Simulation results show that the SET pulse width increa

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9

Yan, Gangping, Jinshun Bi, Gaobo Xu, et al. "Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor." IEEE Access 8 (2020): 154898–905. http://dx.doi.org/10.1109/access.2020.3018714.

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10

Jacquemod, Gilles, Alexandre Fonseca, Emeric de Foucauld, Yves Leduc, and Philippe Lorenzini. "2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology." Frontiers of Materials Science 9, no. 2 (2015): 156–62. http://dx.doi.org/10.1007/s11706-015-0288-6.

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11

Wei, Zhaopeng, Gilles Jacquemod, Yves Leduc, Emeric de Foucauld, Jerome Prouvee, and Benjamin Blampey. "Reducing the Short Channel Effect of Transistors and Reducing the Size of Analog Circuits." Active and Passive Electronic Components 2019 (July 4, 2019): 1–9. http://dx.doi.org/10.1155/2019/4578501.

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Analog integrated circuits never follow the Moore’s Law. This is particularly right for passive component. Due to the Short Channel Effect, we have to implement longer transistor, especially for analog cell. In this paper, we propose a new topology using some advantages of the FDSOI (Fully Depleted Silicon on Insulator) technology in order to reduce the size of analog cells. First, a current mirror was chosen to illustrate and validate a new design. Measured currents, with 35nm transistor length, have validated our new cross-coupled back-gate topology. Then, a VCRO (Voltage Controlled Ring Osc

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12

Lederer, Maximilian, Thomas Kämpfe, Norman Vogel, et al. "Structural and Electrical Comparison of Si and Zr Doped Hafnium Oxide Thin Films and Integrated FeFETs Utilizing Transmission Kikuchi Diffraction." Nanomaterials 10, no. 2 (2020): 384. http://dx.doi.org/10.3390/nano10020384.

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The microstructure of ferroelectric hafnium oxide plays a vital role for its application, e.g., non-volatile memories. In this study, transmission Kikuchi diffraction and scanning transmission electron microscopy STEM techniques are used to compare the crystallographic phase and orientation of Si and Zr doped HfO2 thin films as well as integrated in a 22 nm fully-depleted silicon-on-insulator (FDSOI) ferroelectric field effect transistor (FeFET). Both HfO2 films showed a predominately orthorhombic phase in accordance with electrical measurements and X-ray diffraction XRD data. Furthermore, a s

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13

Zhang, Lujie, Jingyan Xu, Yaqing Chi, and Yang Guo. "The Effect of Energy Loss Straggling on SEUs Induced by Low-Energy Protons in 28 nm FDSOI SRAMs." Applied Sciences 9, no. 17 (2019): 3475. http://dx.doi.org/10.3390/app9173475.

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Sensitive volume thickness for silicon on insulator (SOI) devices has scaled to the point that energy loss straggling cannot be ignored within the development of the manufacturing process. In this study, irradiation experiments and Geant4 simulation were carried out to explore the influence of energy loss straggling on single event upsets (SEUs) caused by sub-8 MeV proton direct ionization. We took a 28 nm fully-depleted SOI static random-access memory (SRAM) as the research target. According to our results, the depositing energy spectrum formed by monoenergetic low-energy protons that penetra

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14

Han, Sangwoo, Sojin Jeong, Jaemin Shin, and Changhwan Shin. "Steep-Switching Fully Depleted Silicon-on-Insulator (FDSOI) Phase-Transition Field-Effect Transistor With Optimized HfO₂/Al₂O₃-Multilayer-Based Threshold Switching Device." IEEE Transactions on Electron Devices 68, no. 3 (2021): 1358–63. http://dx.doi.org/10.1109/ted.2021.3053237.

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15

Boutchacha, T., and G. Ghibaudo. "Semianalytical Modelling and 2D Numerical Simulation of Low-Frequency Noise in Advanced N-Channel FDSOI MOSFETs." Active and Passive Electronic Components 2020 (December 2, 2020): 1–10. http://dx.doi.org/10.1155/2020/7989238.

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Thorough investigations of the low-frequency noise (LFN) in a fully depleted silicon-on-insulator technology node have been accomplished, pointing out on the contribution of the buried oxide (BOX) and the Si-BOX interface to the total drain current noise level. A new analytical multilayer gate stack flat-band voltage fluctuation-based model has been established, and 2D numerical simulations have been carried out to identify the main noise sources and related parameters on which the LFN depends. The increase of the noise at strong inversion could be explained by the access resistance contributi

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16

Christmann, Jean-Frédéric, Florent Berthier, David Coriat, et al. "A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm." Journal of Low Power Electronics and Applications 9, no. 1 (2019): 8. http://dx.doi.org/10.3390/jlpea9010008.

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Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wa

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17

Dghais, Wael, Malek Souilem, Fakhreddine Zayer, and Abdelkader Chaari. "Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation." Mathematical Problems in Engineering 2018 (August 8, 2018): 1–9. http://dx.doi.org/10.1155/2018/1356538.

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This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power sup

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18

Kumar, K. Senthil, Saptarsi Ghosh, Anup Sarkar, S. Bhattacharya, and Subir Kumar Sarkar. "Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance." Applied Mechanics and Materials 110-116 (October 2011): 5150–54. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.5150.

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With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of

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19

Zhao, Chao, and Jinjuan Xiang. "Atomic Layer Deposition (ALD) of Metal Gates for CMOS." Applied Sciences 9, no. 11 (2019): 2388. http://dx.doi.org/10.3390/app9112388.

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The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and

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20

Nocua, Alejandro, Arnaud Virazel, Alberto Bosio, Patrick Girard, and Cyril Chevalier. "HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization." Journal of Circuits, Systems and Computers 26, no. 08 (2017): 1740004. http://dx.doi.org/10.1142/s0218126617400047.

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High power consumption is a key factor hindering system-on-chip (SoC) performance. Accurate and efficient power models have to be introduced early in the design flow when most of the optimization potential is possible. However, early accuracy cannot be ensured because of the lack of precise knowledge of the final circuit structure. Current SoC design paradigm relies on intellectual property (IP) core reuse since low-level information about circuit components and structure is available. Thus, power estimation accuracy at the system level can be improved by using this information and developing

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21

"Analytical Modeling and Simulation of Nanoscale Fully Depleted Dual Metal Gate SOI MOSFET." VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE 8, no. 10 (2019): 2946–50. http://dx.doi.org/10.35940/ijitee.j1113.0881019.

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The demand and development of scaled semiconductors devices for upcoming challenges in VLSI technology is unending. CMOS technology plays a very important role in fulfilling this criterion. The conventional MOSFET exhibits short channel effects (SCE) and performance degradation when scaled down in the nanometer regime. In order to meet the required enhanced performance and to further increase the device density new materials and new device structures have been developed. This paper analyses the performance characteristics of one of such improved device structure i.e Fully Depleted Silicon over

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22

Yoon, Chankeun, Seungjun Moon, and Changhwan Shin. "Study of a hysteresis window of FinFET and fully-depleted silicon-on-insulator (FDSOI) MOSFET with ferroelectric capacitor." Nano Convergence 7, no. 1 (2020). http://dx.doi.org/10.1186/s40580-020-00230-x.

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23

Ameziane, Hatim, Kamal Zared, and Hassan Qjidaa. "A New CMOS OP-AMP Design with an Improved Adaptive Biasing Circuitry." WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 19 (January 4, 2021). http://dx.doi.org/10.37394/23201.2020.19.27.

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This paper sets out a new technique for designing an operational amplifier (OP-AMP) using tanner EDA 1um FDSOI CMOS Technology. Fully Depleted Silicon on Insulator used for building integrated circuits to support the temperature changes, the proposed OP-AMP operates at 3.75V power supply and 70uA bias current using the proposed Adaptive Biasing Circuitry (ABC), which its devices operate at the weak inversion to allow low power dissipation of 0.62mW. The 0.064us settling time and 37.016V/μs slew rate parameters improved by the ABC technique, reducing the power dissipation by operating the ABC d

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