Academic literature on the topic 'Technology / Electronics / Microelectronics'

Reconfigurable electronics technology represents a challenging implementation paradigm of actual stage microelectronics. This paper presents the advantages of using hardware reconfigurable microelectronics technology in intelligent spaces development and implementation. An original approach is unfolded which emphasize the versatility of reconfigurable electronic circuit’s topology based configurations in a wide range of intelligent environment applications. The introduced theoretical approaches have been validated then by a real-time intelligent space implementation example. There have been exploited the huge re-routing abilities of reconfigurable electronics associated with its fine-grained operating behaviours. The final result of the theoretical and experimental research efforts is a well-fitted and practical solution for a wide range of intelligent space applications development and implementation.

The map of science for the Omsk State Technical University in the field of microelectronics and information technology is presented in the work. The map was built on the basis of data from the SciVal scientometric system based on university publications in Scopus. Also, the results of registration of intellectual activity, registered in the Unified State Information System of Accounting. research, development and technological work for civil purposes are used.

Crystalline silicon forms the basis of just about all computing technologies on the planet, in the form of microelectronics. An enormous amount of research infrastructure and knowledge has been developed over the past half-century to construct complex functional microelectronic structures in silicon. As a result, it is highly probable that silicon will remain central to computing and related technologies as a platform for integration of, for instance, molecular electronics, sensing elements and micro- and nanoelectromechanical systems. Porous nanocrystalline silicon is a fascinating variant of the same single crystal silicon wafers used to make computer chips. Its synthesis, a straightforward electrochemical, chemical or photochemical etch, is compatible with existing silicon-based fabrication techniques. Porous silicon literally adds an entirely new dimension to the realm of silicon-based technologies as it has a complex, three-dimensional architecture made up of silicon nanoparticles, nanowires, and channel structures. The intrinsic material is photoluminescent at room temperature in the visible region due to quantum confinement effects, and thus provides an optical element to electronic applications. Our group has been developing new organic surface reactions on porous and nanocrystalline silicon to tailor it for a myriad of applications, including molecular electronics and sensing. Integration of organic and biological molecules with porous silicon is critical to harness the properties of this material. The construction and use of complex, hierarchical molecular synthetic strategies on porous silicon will be described.

As semiconductor technology advances and computers become smaller with higher functionality, the technology has extended into a variety of areas, such as IT-enabled household electronics, ICT devices, electronic automobiles and ITS transport networks, to enrich people's lives. Packaging technology serves as a vital bridge between semiconductor chips and computer systems. Its considerable value is recognized in the constant contributions it makes in bringing about a prosperous life. This paper addresses the two mainstream areas of high-end computers and consumer products, with a special focus on the ceramic materials and process technology of the packaging technologies field at the primary packaging level. Drawing on the past and present developments in these areas as well as future prospects, the paper elucidates the significance of ceramics in packaging.

Mechanical and electrical integration, also known as mechanical, electronics is an interdisciplinary comprehensive high technology, is made up of microelectronics technology, computer technology, information technology, automatic control technology, mechanical technology, hydraulic technology and other technology cross mutual fusion and become an independent discipline. This article mainly discusses the mechanical and electrical integration in the application of all kinds of excavator.

This paper presents the results of hydrogen electron-cyclotron resonance (ECR) plasma in micro-electronics technology. Its effect on the radiation resistance of the IC and on the quality of the ohmic contact during the formation of UBM metallization is demonstrated. The devices obtained with the use of plasma ECR and without it are analyzed.

AbstractDevelopments originally targeted toward economical manufacturing of telecommunications products have planted the seeds for new opportunities such as low-cost, large-area electronics based on printing technologies. Organic-based materials systems for printed wiring board (PWB) construction have opened up unique opportunities for materials research in the fabrication of modular electronic systems.The realization of successful consumer products has been driven by materials developments that expand PWB functionality through embedded passive components, novel MEMS structures (e.g., meso-MEMS, in which the PWB-based structures are at the milliscale instead of the microscale), and microfluidics within the PWB. Furthermore, materials research is opening up a new world of printed electronics technology, where active devices are being realized through the convergence of printing technologies and microelectronics.

In the 1980's the US based electronics manufacturing and ecosystem witnessed a significant shift from manual operations to automated assembly to enable high volume, lower cost products. The maturation of surface mount technology and the introduction of organic semiconductor packaging were key drivers and enablers during this era. The 1990's brought about the shift from the OEM microelectronics innovation & assembly ecosystem to the outsourced model as OEM's tried to stay ahead of the cost reduction curve during this dotcom era. The end result was a short lived US based model for outsourced volume microelectronics assembly that crashed with many of the other startups in the early 2000's. The severity of the downturn not only affected the volume assembly service model but, more importantly the innovation and development opportunities for microelectronics as well. With the recent renewed emphasis on innovation, security, reshoring and manufacturing job creation the opportunity to create a new model for microelectronics assembly in the US has successfully emerged.

Abstract The second Electronics Resurgence Initiative (ERI 2.0), sponsored by the U.S. Defense Advanced Research Project Agency (DARPA) Microsystems Technology Office (MTO), is focused on driving next generation dual use microelectronics for national security and domestic needs. The initiative focuses on creating U.S. capability for three-dimensional heterogeneous integration (3DHI) manufacturing and pursuing focused research for the manufacture of complex 3D microsystems. This guest editorial describes the outcomes from a three-day summit (Seattle, Washington, August 2023) where the initiative was launched.

Extreme environments pose major obstacles for electronics in the form of extremely wide temperature ranges and hazardous radiation. The most common mitigation procedures involve extensive shielding and temperature control or complete displacement from the environment with high costs in weight, power, volume, and performance. There has been a shift away from these solutions and towards distributed, in-environment electronic systems. However, for this methodology to be viable, the requirements of heavy radiation shielding and temperature control have to be lessened or eliminated. This work gained new understanding of the best practices in analog circuit design for extreme environments. Major accomplishments included the over-temperature -180 C to +120 C and radiation validation of the SiGe Remote Electronics Unit, a first of its kind, 16 channel, sensor interface for unshielded operation in the Lunar environment, the design of two wide-temperature (-180 C to +120 C), total-ionizing-dose hardened, wireline transceivers for the Lunar environment, the low-frequency-noise characterization of a second-generation BiCMOS process from 300 K down to 90 K, the explanation of the physical mechanisms behind the single-event transient response of cascode structures in a 45 nm, SOI, radio-frequency, CMOS technology, the analysis of the single-event transient response of differential structures in a 32 nm, SOI, RF, CMOS technology, and the prediction of scaling trends of single-event effects in SOI CMOS technologies.

Les objectifs de la thèse concernent l’optimisation du rendement énergétique, la minimisation de l’empreinte et du coût de l’alimentation en tension d’amplificateurs audio pour l’application casque des plateformes mobiles. Après une présentation du contexte des plateformes mobiles et des caractéristiques principales des amplificateurs audio dédiés, l’introduction conclut sur la nécessité d’une alimentation en tensions bipolaires, symétriques et donne les spécifications principales d’une telle alimentation en énergie électrique. Le chapitre d’état de l’art présente dans un premier temps les architeture les plus compétitves permettant de générer deux tensions symétriques. Une figure de mérite englobe le rendement énergétique, l’empreinte sur la plateforme et le coût en composants passifs externes de chacune des solutions présentées. Une architecture de convertisseur utilisant une seule inductance pour obtenir des tensions régulées symétriques se révelle etre un candidat interessant pour l’alimentation des amplificateurs dédiés aux casques audio. Cette architecture à été démontrée mais cependant loin des spécifications de l’application casque audio. Basée sur cette architecture, le chapitre troisième présente un étage de puissance et ses modes de conduction correspondant aux spécifications de l’application casque audio. Des détails concernent en particulier la conception des interrupteurs ainsi que la stratégie d’asservissement et de régulation. Des premières estimations de rendement sont évaluées dans les pires cas de fonctionnement. Très tôt dans le déroulement de la thèse, il y a eu une opportunité de tester l’étage de puissance en technologie CMOS 130nm. Le chapitre 4 présente l’implémentation du convertisseur sur un circuit de test. Le convertisseur est embarqué notamment à côté d’un amplificateur audio dédié, autorisant des tests plus proches de la réalité d’usage. Les campagnes de mesures ont concerné les aspects fonctionnels et les valeurs de rendement. Les résultats sont encourageants mais confirment les éléments non optimaux du dispositif. Dans l’idée d’un second silicium, le chapitre cinquième décrit plus théoriquement l’approche d’asservissement et de régulation et met en évidence des cas critiques, peu probables mais concrets, liés à l’évaluation sur des profils de charge réelle du convertisseur. Des simulations permettent de transformer un flux audio en courbe de courant absorbé par l’amplificateur audio, c’est-à-dire la charge réelle vue par le convertisseur de tensions symétriques. Le chapitre sixième décrit des améliorations à propos des modes de conduction, à savoir l’introduction des modes discontinu ou d’élimination d’impulsion (pulse skipping). Malheureusement une crise économique a barré l’accès à un silicium de validation finale. Le manuscrit est conclu par un rappel des résultats principaux et des perspectives. Les travaux ont fait l’objet de publications à des conférences internationales
The objectives of this thesis were the optimization of the power efficiency and the minimization of the footprint area and cost of the integrated power supply of headset audio amplifiers on mobile platforms (fig. 1). The thesis took place in the Analog System Design group at ST Ericsson in strong collaboration with Ampere laboratory at INSA de Lyon. The french agency ANRT provided part of the project funding. The first chapter presents the current mobile platform context as well as the main characteristics of audio amplifiers driving headphones. This chapter concludes giving the need of a symmetrical power supply for the headset audio amplifiers and giving a set of electrical specifications for this power supply. The second chapter presents the state-of-the-art in terms of symmetrical power supply architectures able to fit the previously given characteristics and specifications. A set of key parameters based on the power efficiency, the relative silicon area, the relative external bill of material, the number of Input/Output pins and the external passive components area, is employed to benchmark all existing architectures to supply such audio amplifiers. This benchmark reveals the novel Single Inductor Bipolar Output (SIBO) converter as very promising. The similar existing circuits are also detailed and pros and cons of each one of them are discussed to define the most suited architecture. The third chapter proposes a dedicated power stage architecture and related conduction schemes. The design of the power stage is described as well as its dedicated control strategy. Some ideal efficiency estimations are given. The fourth chapter presents the realization of a first prototype, designed in a 130 nm ST Microelectronics CMOS process to be an early demonstrator of the architecture in chapter 3. Measurements on efficiency, control and transient performances are presented and discussed. This circuit embedded on the same die as an audio amplifier proves its effectiveness in supplying such a circuit. The fifth chapter presents a theoretical analysis of the feedback control of this SIBO converter. Mathematical linear model of the converter is derived to obtain its transfer function matrix, then the feedback structure design is defined thanks to dedicated mathematical tools. A set of classical PID controllers is proposed and validated with piecewise linear model while playing different audio popular songs. The sixth chapter describes the design of improvements of the first test chip as well as simulation results about these improvements. The main improvements presented in this chapter are a Discontinuous Conduction Mode (DCM) as well as a Pulse Skipping Mode (PSM). No silicon result can be presented here due to a budget restriction that impacted the course of the thesis. The final chapter is a discussion about the proposed solutions and some perspectives to the present work

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007.
Includes bibliographical references.

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.
Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009.
Includes bibliographical references.

ALICE (A Large Ion Collider Experiment) is the heavy-ion experiment at the Large Hadron Collider (LHC) at CERN. As an important part of its upgrade plans, the ALICE experiment will schedule the installation of a new Inner Tracking System (ITS) during the Long Shutdown 2 (LS2) of the LHC. The new ITS layout will consist of seven concentric layers, ¿ 12.5 Gigapixel camera covering about 10m2 with Monolithic Active Pixel Sensors (MAPS). This choice of technology has been guided by the tight requirements on the material budget of 0.3% X/X0 per layer for the three innermost layers and backed by the significant progress in the field of MAPS in recent years. The technology initially chosen for the ITS upgrade is the TowerJazz 180 nm CMOS Technology. It offers a standard epitaxial layer of 15 - 18 µm with a resistivity between 1 and 5 k¿ cm¿1 and a gate oxide thickness below 4 nm, thus being more robust to Total Ionizing Dose (TID). The main subject of this thesis is to implement a novel digital pixel readout architecture for MAPS. This thesis aims to study this novel readout architecture as an alternative to the rolling-shutter readout. However, this must be investigated through the study of several chip readout architectures during the R&D phase. Another objective of this thesis is the study and characterization of TowerJazz, if it meets the Non-Ionizing Energy Loss (NIEL) and Single Event Effects (SEE) of the ALICE ITS upgrade program. Other goals of this thesis are: ¿ Implementation of the top-down flow for this CMOS process and the design of multiple readouts for different prototypes up to the assembly of a full-scale prototype. xvii Abstract ¿ Characterization of the radiation hardness and SEE of the chips submitted to fabrication. ¿ Characterization of full custom designs using analog simulations and the generation of digital models for the simulation chain needed for the verification process. ¿ Implementation and study of different digital readouts to meet the ITS upgrade program in integration time, pixel size and power consumption, from the conceptual idea, production and fabrication phase. Chapter 1 is a brief overview of CERN, the LHC and the detectors complex. The ALICE ITS will be explained, focusing on the ITS upgrade in terms of detector needs and design constraints. Chapter 2 explains the properties of silicon detectors and the detector material and the principles of operation for MAPS. Chapters 3 and 4 describe the ALPIDE prototypes and their readout based on MAPS; this forms the central part of this work, including the multiple families of pixel detectors fabricated in order to reach the final design for the ITS. The ALPIDE3/pALPIDE3B chip, the latest MAPS chip designed, will be explained in detail, as well focusing in the matrix digital readout. In chapter 5 the noise measurements and its characterization are presented including a brief summary of detector response to irradiation with soft X-rays, sources and particle beams.
El sub detector ITS (Inner Tracking System) del detector ALICE (A Large Ion Collider Experiment) es un detector de vértice y es el detector mas cercano al punto de interacción. Se encuentra conformado por 3 tipos de subdetectores, dos capas de pixel de silicio (Silicon Pixel Detectors), 2 capas de acumulación de silicio (Silicon Drift Detectors) y 2 capas de banda de Silicio (Silicon Strip Detectors). La función primaria del ITS es identificar y rastrear las partículas de bajo momentum transversal. El detector ITS en sus dos capas más internas están equipadas con sensores de silicio basados en píxeles híbridos. Para reemplazar esta tecnología de Píxeles, el detector ITS actual será reemplazado por un nuevo detector de una sola tecnología, ampliando su resolución espacial y mejorando el rastreo de trazas. Este nuevo detector constará de siete capas de sensores de píxeles activos monolíticos (MAPS), las cuales deberán satisfacer los requerimientos de presupuesto de materiales y ser tolerantes a mayores niveles de radiación para los nuevos escenarios de incrementos de luminosidad y mayores tasas de colisiones. Los sensores MAPS que integran el sensor de imagen y los circuitos de lectura se encuentran en la misma oblea de silicio, tienen grandes ventajas en una buena resolución de posición y un bajo presupuesto material en términos de bajo coste de producción. TowerJazz ofrece la posibilidad de una cuádruple-WELL aislando los transistores pMOS que se encuentran en la misma nWELL evitando la competencia con el electrodo de recolección, permitiendo circuitos mas complejos y compactos para ser implementados dentro de la zona activa y además posee una capa epitaxial de alta resistividad. Esta tecnología proporciona una puerta de óxido muy delgado limitando el daño superficial por la radiación haciéndolo adecuado para su uso denxiii Resúmen tro del experimento ALICE. En los últimos cuatro años se ha llevado a cabo una intensiva I+D en MAPS en el marco de la actualización del ITS de ALICE. Varios prototipos a pequeña escala se han desarrollado y probado exitosamente con rayos X, fuentes radioactivas y haces de partículas. La tolerancia a la radiación de ALICE ITS es moderada con una tolerancia de irradiación TID de 700 krad y NIEL de 1 × 1013 1 MeV neqcm¿2 , MAPS es una opción viable para la actualización del ITS. La contribución original de esta tesis es la implementación de una nueva arquitectura digital de lectura de píxeles para MAPS. Esta tesis presenta un codificador asíncrono de direcciones (arquitectura basada en la supresión de ceros transmitiendo la dirección de los píxeles excitados denominada PADRE) para la arquitectura ALPIDE, el autor también hizo una contribución significativa en el ensamblaje y veri- ficación de circuitos. PADRE es la principal investigación del autor, basada en un codificador de prioridad jerárquica de cuatro entradas y es una alternativa a la arquitectura de lectura rolling-shutter. Además de los prototipos a pequeña escala, también se han desarrollado prototipos a escala completa a las necesidades del detector ITS (15 mm y 30 mm) empleando un nuevo circuito de lectura basado en la versión personalizada del circuito PADRE. El pALPIDEfs fue el primer prototipo a escala completa y se caracterizó obteniendo un tiempo de lectura de la matriz por debajo de 4 µs y un consumo de energía en el orden de 80 mWcm¿2 . En general, los resultados obtenidos representan un avance significativo de la tecnología MAPS en cuanto al consumo de energía, velocidad de lectura, tiempo de recolección de carga y tolerancia a la radiación. El sensor pALPIDE2 ha demostrado ser una opción muy atractiva para el nuevo detector ITS, satisfaciendo los requerimientos en términos de eficiencia de detección, fake-hit rate y resolución de posición, ya que su rendimiento no puede alcanzarse mediante prototipos basados en la arquitectura de lectura tradicionales como es
El subdetector ITS (Inner Tracking System) del detector ALICE (A Large Ion Collider Experiment) és un detector de vèrtex i és el detector mes proper al punt d'interacció. Es troba conformat per 3 tipus de subdetectors, dues capes de píxel de silici (Silicon Pixel Detectors), 2 capes d'acumulació de silici (Silicon Drift Detectors) i 2 capes de banda de Silici (Silicon Strip Detectors). La funció primària del ITS és identificar i rastrejar les partícules de baix moment transversal. El detector ITS en les seues dues capes més internes estan equipades amb sensors de silici basats en píxels híbrids. Per a reemplaçar aquesta tecnologia de Píxels, el detector ITS actual serà reemplaçat per un nou detector d'una sola tecnologia, ampliant la seua resolució espacial i millorant el rastreig de traces. Aquest nou detector constarà de set capes de sensors de píxels actius monolítics (MAPS), les quals hauran de satisfer els requeriments de pressupost de materials i ser tolerants a majors nivells de radiació per als nous escenaris d'increments de lluminositat i majors taxes de col·lisions. Els sensors MAPS que integren el sensor d'imatge i els circuits de lectura es troben en la mateixa hòstia de silici, tenen grans avantatges en una bona resolució de posició i un baix pressupost material en termes de baix cost de producció. TowerJazz ofereix la possibilitat d'una quàdruple-WELL aïllant els transistors pMOS que es troben en la mateixa nWELL evitant la competència amb l'elèctrode de recol·lecció, permetent circuits mes complexos i compactes per a ser implementats dins de la zona activa i a més posseeix una capa epitaxial d'alta resistivitat. Aquesta tecnologia proporciona una porta d'òxid molt prim limitant el dany superficial per la radiació fent-ho adequat per al seu ús dins de l'- experiment ALICE. En els últims quatre anys s'ha dut a terme una intensiva R+D en MAPS en el marc de l'actualització del ITS d'ALICE. Diversos prototips a petita escala s'han desenvolupat i provat ix Resum reeixidament amb rajos X, fonts radioactives i feixos de partícules. La tolerància a la radiació d'ALICE ITS és moderada amb una tolerància d'irradiació TID de 700 krad i NIEL d'1× 1013 1MeV neqcm¿2 , MAPS és una opció viable per a l'actualització del ITS. La contribució original d'aquesta tesi és la implementació d'una nova arquitectura digital de lectura de píxels per a MAPS. Aquesta tesi presenta un codificador asíncron d'adreces (arquitectura basada en la supressió de zeros transmetent l'adreça dels píxels excitats denominada PADRE) per a l'arquitectura ALPIDE, l'autor també va fer una contribució significativa en l'assemblatge i verificació de circuits. PADRE és la principal recerca de l'autor, basada en un codificador de prioritat jeràrquica de quatre entrades i és una alternativa a l'arquitectura de lectura rolling-shutter. A més dels prototips a petita escala, també s'han desenvolupat prototips a escala completa a les necessitats del detector ITS (15 mm i 30 mm) emprant un nou circuit de lectura basat en la versió personalitzada del circuit PADRE. El pALPIDEfs va ser el primer prototip a escala completa i es va caracteritzar obtenint un temps de lectura de la matriu per sota de 4 µs i un consum d'energia en l'ordre de 80 mWcm¿2 . En general, els resultats obtinguts representen un avanç significatiu de la tecnologia MAPS quant al consum d'energia, velocitat de lectura, temps de recol·lecció de càrrega i tolerància a la radiació. El sensor pALPIDE2 ha demostrat ser una opció molt atractiva per al nou detector ITS, satisfent els requeriments en termes d'eficiència de detecció, fake-hit rate i resolució de posició, ja que el seu rendiment no pot aconseguir-se mitjançant prototips basats en l'arquitectura de lectura tradicionals com és el rolling-shutter dissenyat en la mateixa tecnologia. Per aquesta raó, la R+D en els prototips ALPIDE ha continuat amb l'objectiu d'optimitza
Marín Tobón, CA. (2017). PADRE pixel read-out architecture for Monolithic Active Pixel Sensor for the new ALICE Inner Tracking System in TowerJazz 180 nm technolog [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/86154
TESIS

Laser Induced Forward Transfer (LIFT) techniques show promise as a disruptive technology which will enable the placement of components smaller than what conventional pick-and-place techniques are capable of today. Limitations of current die-attach techniques are presented and discussed and present the opportunity for a new placement method. This study introduces the Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) process and is an application of the unique blistering behavior of a dynamic releasing layer when irradiated by low energy focused UV laser pulses. The potential of tmSLADT as the next generation LIFT technique is demonstrated by the "touchless" transfer of 65 ?m thick silicon tiles between two substrates spaced 195 ?m apart. Additionally, the advantages of an enclosed blister-actuator mechanism over previously studied ablative and thermal releasing techniques are discussed. Finally, experimental results studying transfer precision indicate this non optimized die transfer process compares with, and may exceed, the placement precision of current assembly techniques.
Defense Microelectronics Activity (DMEA) under agreement number H94003-09-2-0905

As microelectronics becomes increasingly important in automotive systems, transport electronics developers are increasingly relying on FPGA programmable structures to create applications with better performance and flexible architectures. Keywords—electronic control units, transport applications, programmable logic blocks, automotive information technology, hardware, digital signal processing