Dissertations / Theses on the topic 'Technology / Electronics / Microelectronics'

Extreme environments pose major obstacles for electronics in the form of extremely wide temperature ranges and hazardous radiation. The most common mitigation procedures involve extensive shielding and temperature control or complete displacement from the environment with high costs in weight, power, volume, and performance. There has been a shift away from these solutions and towards distributed, in-environment electronic systems. However, for this methodology to be viable, the requirements of heavy radiation shielding and temperature control have to be lessened or eliminated. This work gained new understanding of the best practices in analog circuit design for extreme environments. Major accomplishments included the over-temperature -180 C to +120 C and radiation validation of the SiGe Remote Electronics Unit, a first of its kind, 16 channel, sensor interface for unshielded operation in the Lunar environment, the design of two wide-temperature (-180 C to +120 C), total-ionizing-dose hardened, wireline transceivers for the Lunar environment, the low-frequency-noise characterization of a second-generation BiCMOS process from 300 K down to 90 K, the explanation of the physical mechanisms behind the single-event transient response of cascode structures in a 45 nm, SOI, radio-frequency, CMOS technology, the analysis of the single-event transient response of differential structures in a 32 nm, SOI, RF, CMOS technology, and the prediction of scaling trends of single-event effects in SOI CMOS technologies.

Les objectifs de la thèse concernent l’optimisation du rendement énergétique, la minimisation de l’empreinte et du coût de l’alimentation en tension d’amplificateurs audio pour l’application casque des plateformes mobiles. Après une présentation du contexte des plateformes mobiles et des caractéristiques principales des amplificateurs audio dédiés, l’introduction conclut sur la nécessité d’une alimentation en tensions bipolaires, symétriques et donne les spécifications principales d’une telle alimentation en énergie électrique. Le chapitre d’état de l’art présente dans un premier temps les architeture les plus compétitves permettant de générer deux tensions symétriques. Une figure de mérite englobe le rendement énergétique, l’empreinte sur la plateforme et le coût en composants passifs externes de chacune des solutions présentées. Une architecture de convertisseur utilisant une seule inductance pour obtenir des tensions régulées symétriques se révelle etre un candidat interessant pour l’alimentation des amplificateurs dédiés aux casques audio. Cette architecture à été démontrée mais cependant loin des spécifications de l’application casque audio. Basée sur cette architecture, le chapitre troisième présente un étage de puissance et ses modes de conduction correspondant aux spécifications de l’application casque audio. Des détails concernent en particulier la conception des interrupteurs ainsi que la stratégie d’asservissement et de régulation. Des premières estimations de rendement sont évaluées dans les pires cas de fonctionnement. Très tôt dans le déroulement de la thèse, il y a eu une opportunité de tester l’étage de puissance en technologie CMOS 130nm. Le chapitre 4 présente l’implémentation du convertisseur sur un circuit de test. Le convertisseur est embarqué notamment à côté d’un amplificateur audio dédié, autorisant des tests plus proches de la réalité d’usage. Les campagnes de mesures ont concerné les aspects fonctionnels et les valeurs de rendement. Les résultats sont encourageants mais confirment les éléments non optimaux du dispositif. Dans l’idée d’un second silicium, le chapitre cinquième décrit plus théoriquement l’approche d’asservissement et de régulation et met en évidence des cas critiques, peu probables mais concrets, liés à l’évaluation sur des profils de charge réelle du convertisseur. Des simulations permettent de transformer un flux audio en courbe de courant absorbé par l’amplificateur audio, c’est-à-dire la charge réelle vue par le convertisseur de tensions symétriques. Le chapitre sixième décrit des améliorations à propos des modes de conduction, à savoir l’introduction des modes discontinu ou d’élimination d’impulsion (pulse skipping). Malheureusement une crise économique a barré l’accès à un silicium de validation finale. Le manuscrit est conclu par un rappel des résultats principaux et des perspectives. Les travaux ont fait l’objet de publications à des conférences internationales
The objectives of this thesis were the optimization of the power efficiency and the minimization of the footprint area and cost of the integrated power supply of headset audio amplifiers on mobile platforms (fig. 1). The thesis took place in the Analog System Design group at ST Ericsson in strong collaboration with Ampere laboratory at INSA de Lyon. The french agency ANRT provided part of the project funding. The first chapter presents the current mobile platform context as well as the main characteristics of audio amplifiers driving headphones. This chapter concludes giving the need of a symmetrical power supply for the headset audio amplifiers and giving a set of electrical specifications for this power supply. The second chapter presents the state-of-the-art in terms of symmetrical power supply architectures able to fit the previously given characteristics and specifications. A set of key parameters based on the power efficiency, the relative silicon area, the relative external bill of material, the number of Input/Output pins and the external passive components area, is employed to benchmark all existing architectures to supply such audio amplifiers. This benchmark reveals the novel Single Inductor Bipolar Output (SIBO) converter as very promising. The similar existing circuits are also detailed and pros and cons of each one of them are discussed to define the most suited architecture. The third chapter proposes a dedicated power stage architecture and related conduction schemes. The design of the power stage is described as well as its dedicated control strategy. Some ideal efficiency estimations are given. The fourth chapter presents the realization of a first prototype, designed in a 130 nm ST Microelectronics CMOS process to be an early demonstrator of the architecture in chapter 3. Measurements on efficiency, control and transient performances are presented and discussed. This circuit embedded on the same die as an audio amplifier proves its effectiveness in supplying such a circuit. The fifth chapter presents a theoretical analysis of the feedback control of this SIBO converter. Mathematical linear model of the converter is derived to obtain its transfer function matrix, then the feedback structure design is defined thanks to dedicated mathematical tools. A set of classical PID controllers is proposed and validated with piecewise linear model while playing different audio popular songs. The sixth chapter describes the design of improvements of the first test chip as well as simulation results about these improvements. The main improvements presented in this chapter are a Discontinuous Conduction Mode (DCM) as well as a Pulse Skipping Mode (PSM). No silicon result can be presented here due to a budget restriction that impacted the course of the thesis. The final chapter is a discussion about the proposed solutions and some perspectives to the present work

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007.
Includes bibliographical references.

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.
Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009.
Includes bibliographical references.

ALICE (A Large Ion Collider Experiment) is the heavy-ion experiment at the Large Hadron Collider (LHC) at CERN. As an important part of its upgrade plans, the ALICE experiment will schedule the installation of a new Inner Tracking System (ITS) during the Long Shutdown 2 (LS2) of the LHC. The new ITS layout will consist of seven concentric layers, ¿ 12.5 Gigapixel camera covering about 10m2 with Monolithic Active Pixel Sensors (MAPS). This choice of technology has been guided by the tight requirements on the material budget of 0.3% X/X0 per layer for the three innermost layers and backed by the significant progress in the field of MAPS in recent years. The technology initially chosen for the ITS upgrade is the TowerJazz 180 nm CMOS Technology. It offers a standard epitaxial layer of 15 - 18 µm with a resistivity between 1 and 5 k¿ cm¿1 and a gate oxide thickness below 4 nm, thus being more robust to Total Ionizing Dose (TID). The main subject of this thesis is to implement a novel digital pixel readout architecture for MAPS. This thesis aims to study this novel readout architecture as an alternative to the rolling-shutter readout. However, this must be investigated through the study of several chip readout architectures during the R&D phase. Another objective of this thesis is the study and characterization of TowerJazz, if it meets the Non-Ionizing Energy Loss (NIEL) and Single Event Effects (SEE) of the ALICE ITS upgrade program. Other goals of this thesis are: ¿ Implementation of the top-down flow for this CMOS process and the design of multiple readouts for different prototypes up to the assembly of a full-scale prototype. xvii Abstract ¿ Characterization of the radiation hardness and SEE of the chips submitted to fabrication. ¿ Characterization of full custom designs using analog simulations and the generation of digital models for the simulation chain needed for the verification process. ¿ Implementation and study of different digital readouts to meet the ITS upgrade program in integration time, pixel size and power consumption, from the conceptual idea, production and fabrication phase. Chapter 1 is a brief overview of CERN, the LHC and the detectors complex. The ALICE ITS will be explained, focusing on the ITS upgrade in terms of detector needs and design constraints. Chapter 2 explains the properties of silicon detectors and the detector material and the principles of operation for MAPS. Chapters 3 and 4 describe the ALPIDE prototypes and their readout based on MAPS; this forms the central part of this work, including the multiple families of pixel detectors fabricated in order to reach the final design for the ITS. The ALPIDE3/pALPIDE3B chip, the latest MAPS chip designed, will be explained in detail, as well focusing in the matrix digital readout. In chapter 5 the noise measurements and its characterization are presented including a brief summary of detector response to irradiation with soft X-rays, sources and particle beams.
El sub detector ITS (Inner Tracking System) del detector ALICE (A Large Ion Collider Experiment) es un detector de vértice y es el detector mas cercano al punto de interacción. Se encuentra conformado por 3 tipos de subdetectores, dos capas de pixel de silicio (Silicon Pixel Detectors), 2 capas de acumulación de silicio (Silicon Drift Detectors) y 2 capas de banda de Silicio (Silicon Strip Detectors). La función primaria del ITS es identificar y rastrear las partículas de bajo momentum transversal. El detector ITS en sus dos capas más internas están equipadas con sensores de silicio basados en píxeles híbridos. Para reemplazar esta tecnología de Píxeles, el detector ITS actual será reemplazado por un nuevo detector de una sola tecnología, ampliando su resolución espacial y mejorando el rastreo de trazas. Este nuevo detector constará de siete capas de sensores de píxeles activos monolíticos (MAPS), las cuales deberán satisfacer los requerimientos de presupuesto de materiales y ser tolerantes a mayores niveles de radiación para los nuevos escenarios de incrementos de luminosidad y mayores tasas de colisiones. Los sensores MAPS que integran el sensor de imagen y los circuitos de lectura se encuentran en la misma oblea de silicio, tienen grandes ventajas en una buena resolución de posición y un bajo presupuesto material en términos de bajo coste de producción. TowerJazz ofrece la posibilidad de una cuádruple-WELL aislando los transistores pMOS que se encuentran en la misma nWELL evitando la competencia con el electrodo de recolección, permitiendo circuitos mas complejos y compactos para ser implementados dentro de la zona activa y además posee una capa epitaxial de alta resistividad. Esta tecnología proporciona una puerta de óxido muy delgado limitando el daño superficial por la radiación haciéndolo adecuado para su uso denxiii Resúmen tro del experimento ALICE. En los últimos cuatro años se ha llevado a cabo una intensiva I+D en MAPS en el marco de la actualización del ITS de ALICE. Varios prototipos a pequeña escala se han desarrollado y probado exitosamente con rayos X, fuentes radioactivas y haces de partículas. La tolerancia a la radiación de ALICE ITS es moderada con una tolerancia de irradiación TID de 700 krad y NIEL de 1 × 1013 1 MeV neqcm¿2 , MAPS es una opción viable para la actualización del ITS. La contribución original de esta tesis es la implementación de una nueva arquitectura digital de lectura de píxeles para MAPS. Esta tesis presenta un codificador asíncrono de direcciones (arquitectura basada en la supresión de ceros transmitiendo la dirección de los píxeles excitados denominada PADRE) para la arquitectura ALPIDE, el autor también hizo una contribución significativa en el ensamblaje y veri- ficación de circuitos. PADRE es la principal investigación del autor, basada en un codificador de prioridad jerárquica de cuatro entradas y es una alternativa a la arquitectura de lectura rolling-shutter. Además de los prototipos a pequeña escala, también se han desarrollado prototipos a escala completa a las necesidades del detector ITS (15 mm y 30 mm) empleando un nuevo circuito de lectura basado en la versión personalizada del circuito PADRE. El pALPIDEfs fue el primer prototipo a escala completa y se caracterizó obteniendo un tiempo de lectura de la matriz por debajo de 4 µs y un consumo de energía en el orden de 80 mWcm¿2 . En general, los resultados obtenidos representan un avance significativo de la tecnología MAPS en cuanto al consumo de energía, velocidad de lectura, tiempo de recolección de carga y tolerancia a la radiación. El sensor pALPIDE2 ha demostrado ser una opción muy atractiva para el nuevo detector ITS, satisfaciendo los requerimientos en términos de eficiencia de detección, fake-hit rate y resolución de posición, ya que su rendimiento no puede alcanzarse mediante prototipos basados en la arquitectura de lectura tradicionales como es
El subdetector ITS (Inner Tracking System) del detector ALICE (A Large Ion Collider Experiment) és un detector de vèrtex i és el detector mes proper al punt d'interacció. Es troba conformat per 3 tipus de subdetectors, dues capes de píxel de silici (Silicon Pixel Detectors), 2 capes d'acumulació de silici (Silicon Drift Detectors) i 2 capes de banda de Silici (Silicon Strip Detectors). La funció primària del ITS és identificar i rastrejar les partícules de baix moment transversal. El detector ITS en les seues dues capes més internes estan equipades amb sensors de silici basats en píxels híbrids. Per a reemplaçar aquesta tecnologia de Píxels, el detector ITS actual serà reemplaçat per un nou detector d'una sola tecnologia, ampliant la seua resolució espacial i millorant el rastreig de traces. Aquest nou detector constarà de set capes de sensors de píxels actius monolítics (MAPS), les quals hauran de satisfer els requeriments de pressupost de materials i ser tolerants a majors nivells de radiació per als nous escenaris d'increments de lluminositat i majors taxes de col·lisions. Els sensors MAPS que integren el sensor d'imatge i els circuits de lectura es troben en la mateixa hòstia de silici, tenen grans avantatges en una bona resolució de posició i un baix pressupost material en termes de baix cost de producció. TowerJazz ofereix la possibilitat d'una quàdruple-WELL aïllant els transistors pMOS que es troben en la mateixa nWELL evitant la competència amb l'elèctrode de recol·lecció, permetent circuits mes complexos i compactes per a ser implementats dins de la zona activa i a més posseeix una capa epitaxial d'alta resistivitat. Aquesta tecnologia proporciona una porta d'òxid molt prim limitant el dany superficial per la radiació fent-ho adequat per al seu ús dins de l'- experiment ALICE. En els últims quatre anys s'ha dut a terme una intensiva R+D en MAPS en el marc de l'actualització del ITS d'ALICE. Diversos prototips a petita escala s'han desenvolupat i provat ix Resum reeixidament amb rajos X, fonts radioactives i feixos de partícules. La tolerància a la radiació d'ALICE ITS és moderada amb una tolerància d'irradiació TID de 700 krad i NIEL d'1× 1013 1MeV neqcm¿2 , MAPS és una opció viable per a l'actualització del ITS. La contribució original d'aquesta tesi és la implementació d'una nova arquitectura digital de lectura de píxels per a MAPS. Aquesta tesi presenta un codificador asíncron d'adreces (arquitectura basada en la supressió de zeros transmetent l'adreça dels píxels excitats denominada PADRE) per a l'arquitectura ALPIDE, l'autor també va fer una contribució significativa en l'assemblatge i verificació de circuits. PADRE és la principal recerca de l'autor, basada en un codificador de prioritat jeràrquica de quatre entrades i és una alternativa a l'arquitectura de lectura rolling-shutter. A més dels prototips a petita escala, també s'han desenvolupat prototips a escala completa a les necessitats del detector ITS (15 mm i 30 mm) emprant un nou circuit de lectura basat en la versió personalitzada del circuit PADRE. El pALPIDEfs va ser el primer prototip a escala completa i es va caracteritzar obtenint un temps de lectura de la matriu per sota de 4 µs i un consum d'energia en l'ordre de 80 mWcm¿2 . En general, els resultats obtinguts representen un avanç significatiu de la tecnologia MAPS quant al consum d'energia, velocitat de lectura, temps de recol·lecció de càrrega i tolerància a la radiació. El sensor pALPIDE2 ha demostrat ser una opció molt atractiva per al nou detector ITS, satisfent els requeriments en termes d'eficiència de detecció, fake-hit rate i resolució de posició, ja que el seu rendiment no pot aconseguir-se mitjançant prototips basats en l'arquitectura de lectura tradicionals com és el rolling-shutter dissenyat en la mateixa tecnologia. Per aquesta raó, la R+D en els prototips ALPIDE ha continuat amb l'objectiu d'optimitza
Marín Tobón, CA. (2017). PADRE pixel read-out architecture for Monolithic Active Pixel Sensor for the new ALICE Inner Tracking System in TowerJazz 180 nm technolog [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/86154
TESIS

Laser Induced Forward Transfer (LIFT) techniques show promise as a disruptive technology which will enable the placement of components smaller than what conventional pick-and-place techniques are capable of today. Limitations of current die-attach techniques are presented and discussed and present the opportunity for a new placement method. This study introduces the Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) process and is an application of the unique blistering behavior of a dynamic releasing layer when irradiated by low energy focused UV laser pulses. The potential of tmSLADT as the next generation LIFT technique is demonstrated by the "touchless" transfer of 65 ?m thick silicon tiles between two substrates spaced 195 ?m apart. Additionally, the advantages of an enclosed blister-actuator mechanism over previously studied ablative and thermal releasing techniques are discussed. Finally, experimental results studying transfer precision indicate this non optimized die transfer process compares with, and may exceed, the placement precision of current assembly techniques.
Defense Microelectronics Activity (DMEA) under agreement number H94003-09-2-0905

Thesis (M. S.)--Materials Science and Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Tummala, Rao; Committee Member: Iyer, Mahadevan; Committee Member: Saxena, Ashok; Committee Member: Swaminathan, Madhavan; Committee Member: Wong, Chingping.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department or Systems Science and Industrial Engineering, 2009.
Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2008.
Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engfineering and Applied Science, Department of Systems Science and Industrial Engineering, 2009.
Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2008.
Includes bibliographical references.

Thesis (Ph. D.)--Chemistry and Biochemistry, Georgia Institute of Technology, 2008.
Committee Chair: Dr. C. P. Wong; Committee Member: Dr. Boris Mizaikoff; Committee Member: Dr. Rigoberto Hernandez; Committee Member: Dr. Z. John Zhang; Committee Member: Dr. Z.L. Wang.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2010.
ENGLISH ABSTRACT: The main focus of this thesis is to document the formulation, extraction and validation of nonlinear models for the on-wafer gallium nitride (GaN) high-electron mobility (HEMT) devices manufactured at the Interuniversity Microelectronics Centre (IMEC) in Leuven, Belgium. GaN semiconductor technology is fast emerging and it is expected that these devices will play an important role in RF and microwave power amplifier applications. One of the main advantages of the new GaN semiconductor technology is that it combines a very wide band-gap with high electron mobility, which amounts to higher levels of gain at very high frequencies. HEMT devices based on GaN, is a fairly new technology and not many nonlinear models have been proposed in literature. This thesis details the design of hardware and software used in the development of the nonlinear models. An intermodulation distortion (IMD) measurement setup was developed to measure the second and higher-order derivative of the nonlinear drain current. The derivatives are extracted directly from measurements and are required to improve the nonlinear model IMD predictions. Nonlinear model extraction software was developed to automate the modelling process, which was fundamental in the nonlinear model investigation. The models are implemented in Agilent’s Advanced Design System (ADS) and it is shown that the models are capable of accurately predicting the measured S-parameters, large-signal singletone and two-tone behaviour of the GaN devices.
AFRIKAANSE OPSOMMING: Die hoofdoel van hierdie tesis is om die formulering, ontrekking en validasie van nie-lineêre modelle vir onverpakte gallium nitraat (GaN) hoë-elektronmobilisering transistors (HEMTs) te dokumenteer. Die transistors is vervaaardig by die Interuniversity Microelectronics Centre (IMEC) in Leuven, België. GaN-halfgeleier tegnologie is besig om vinnig veld te wen en daar word voorspel dat hierdie transistors ʼn belangrike rol gaan speel in RF en mikrogolf kragversterker toepassings. Een van die hoof voordele van die nuwe GaN-halfgeleier tegnologie is dat dit 'n baie wyd band-gaping het met hoë-elektronmobilisering, wat lei tot hoë aanwins by mikrogolf frekwensies. GaN HEMTs is 'n redelik nuwe tegnologie en nie baie nie-lineêre modelle is al voorgestel in literatuur nie. Hierdie tesis ondersoek die ontwerp van die hardeware en sagteware soos gebruik in die ontwikkeling van nie-lineêre modelle. 'n Intermodulasie distorsie-opstelling (IMD-opstelling) is ontwikkel vir die meting van die tweede en hoër orde afgeleides van die nie-lineêre stroom. Die afgeleides is direk uit die metings onttrek en moet die nie-lineêre IMD-voorspellings te verbeter. Nie-lineêre onttrekking sagteware is ontwikkel om die modellerings proses te outomatiseer. Die modelle word geïmplementeer in Agilent se Advanced Design System (ADS) en bewys dat die modelle in staat is om akkurate afgemete S-parameters, grootsein enkeltoon en tweetoon gedrag van die GaN-transistors te kan voorspel.

Thesis (M.S.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.
Includes bibliographical references.

As technology progresses towards smaller electronic packages, thermo-mechanical considerations pose a challenge to package designers. One area of difficulty is the ability to predict the fatigue life of the solder connections. To do this one must be able to accurately model the thermo-mechanical performance of the electronic package. As the solder ball size decreases, it becomes difficult to determine the performance of the package with traditional methods such as the use of strain gages. This is due to the fact that strain gages become limited in size and resolution and lack the ability to measure discreet strain fields as the solder ball size decreases. A solution to the limitations exhibited in strain gages is the use of Moiré interferometry. Moiré interferometry utilizes optical interferometry to measure small, in-plane relative displacements and strains with high sensitivity. Moiré interferometry is a full field technique over the application area, whereas a strain gage gives an average strain for the area encompassed by the gage. This ability to measure full field strains is useful in the analysis of electronic package interconnections; especially when used to measure strains in the solder ball corners, where failure is known to originate. While the improved resolution of the data yielded by the method of Moiré interferometry results in the ability to develop more accurate models, that is not to say the process is simple and without difficulties of it's own. Moiré interferometry is inherently susceptible to error due to experimental and environmental effects; therefore, it is vital to generate a reliable experimental procedure that provides repeatable results. This was achieved in this study by emulating and modifying established procedures to meet our specific application. The developed procedure includes the preparation of the specimen, the replication and transfer of the grids, the use of the PEMI, interpretation of results, and validation of data by finite element analysis using ANSYS software. The data obtained maintained uniformity to the extent required by the scope of this study, and potential sources of error have been identified and should be the subject of further research.

The objective of this dissertation is to develop electrical modeling and co-simulation methodologies for signal and power integrity of package and board applications. The dissertation includes 1) the application of the finite element method to the optimization for decoupling capacitor selection and placement on a power delivery network (PDN), 2) the development of a PDN modeling method effective for multidimensional and multilayer geometries, 3) the analysis and modeling of return path discontinuities (RPDs), and 4) the implementation of the absorbing boundary condition for PDN modeling. The optimization technique for selection and placement of decoupling capacitors uses a genetic algorithm (GA) and the multilayer finite element method (MFEM), a PDN modeling method using FEM. The GA is customized for the decoupling problem to enhance the convergence speed of the optimization. The mathematical modifications necessary for the incorporation of the capacitor model into MFEM is also presented. The main contribution of this dissertation is the development of a new modeling method, the multilayer triangular element method (MTEM), for power/ground planes of a PDN. MTEM creates a surface mesh on each plane-pair using dual graphs; a non-uniform triangular mesh (Delaunay triangulation) and its orthogonal counterpart (Voronoi diagram), to which electromagnetic and equivalent circuit concepts are applied. The non-uniform triangulation is especially efficient for discretizing multidimensional and irregular geometries which are common in package and board PDNs. Moreover, MTEM generates a sparse, banded, and symmetric system matrix, which enables efficient computations. For a given plane-pair, MTEM extracts an equivalent circuit that is consistent with the physics-based planar-circuit model of a plane-pair. Thus, the values of the lumped elements can be simply calculated from the physical parameters, such as material properties and mesh geometries of each unit-cell. Consequently, the modeling of MTEM is flexible and easy to modify for further extensions, such as the incorporation of external circuits, e.g. decoupling capacitors and vertical interconnects. Power and ground planes provide paths for the return current of signal traces. Typically, planes have discontinuities such as via holes, plane cutouts, and split planes that disturb flow of signal return currents. At the discontinuity, return currents have to detour or switch to different layers, causing signal and power integrity problems. Therefore, a separate analysis of signal interconnects will neglect the significant coupling with a PDN, and the result will not be reliable. In this dissertation, the co-simulation of the signal and power integrity is presented focusing on the modeling of RPDs created by split planes, apertures, and vias. Plane resonance is one of the main sources of power integrity problems in package and board PDNs. A number of techniques have been developed and published in literature to reduce or prevent the resonance of a plane-pair. One of the techniques is to surround plane-pair edges with absorbing material that effectively damps the outgoing parallel-plate wave and minimizes the reflection. To model this behavior, the boundary condition of MTEM needs to be changed from its original form, the open-circuit boundary condition. In this dissertation, the application of the 1st order absorbing boundary condition to MTEM is presented.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009.
Includes bibliographical references.

Le résonateur étudié s'insère dans un projet industriel porté par NXP Semiconductors. L'objectif est la réalisation d'un résonateur MEMS RF intégrable en vue de remplacer le quartz dans certaines applications. La compatibilité du procédé de fabrication avec les technologies utilisées par la société et le faible coût de production représentent les principaux enjeux du projet. Le résonateur TFEAR (Thin Film Elongation Acoustic Resonator) est un barreau, constitué d'une superposition de couches minces de type Métal/AlN/Métal. Les propriétés piézoélectriques du nitrure d'aluminium (AlN) sont ainsi exploitées : l'application d'un champ électrique alternatif, parallèle à l'épaisseur du barreau, entraîne une propagation d'ondes acoustiques suivant sa longueur. Les dimensions des résonateurs fabriqués correspondent à des fréquences de résonance comprises entre 10MHz et 50MHz. Cette thèse s'intéresse la modélisation et à la caractérisation électrique du résonateur TFEAR. Les modèles théoriques sont développés par simulations numériques 3D et par calculs analytiques 1D. Le comportement électrique du TFEAR est décrit par un schéma équivalent, dont les éléments sont exprimés en fonction des paramètres physiques et des pertes des matériaux le constituant. Un facteur de qualité de 2250 sur un TFEAR résonant à 25,79MHz et dont la résistance motionnelle est de 2,1 kOhms a été relevé. Ces mesures ont été complétées par la caractérisation des paramètres physiques de la couche piézoélectrique. Par exemple, des valeurs de coefficient piézoélectrique d33f atteignant 2,6 pm/V ont été relevées (pour un maximum théorique de 3,93 pm/V)

Le travail de recherche présenté dans ce mémoire s'inscrit dans l'objectif général d'étudier la faisabilité de filtres monolithiques radiofréquences (RF) à capacités commutées pour la radiocommunication mobile, et de pouvoir procéder à l'analyse et à la conception de ces filtres en technologie standard BiCMOS 0,35 μm. L'analyse comportementale de ces filtres a nécessité la mise au point d'un algorithme original basé sur le formalisme des matrices de conversion, dont le principe général consiste à effectuer une linéarisation des éléments non-linéaires autour du point de fonctionnement grand signal. Cette méthode d'analyse, spécialement utilisée pour l'analyse du bruit de phase des oscillateurs, semble à ce jour parmi les plus rigoureuses et les plus efficaces en terme de temps de calcul pour l'analyse de ce type de filtres. Traditionnellement, à basse fréquence la commande de ces filtres est réalisée à l'aide d'un registre à décalage. Cependant, cette technique n'est pas envisageable en RF. Une solution originale qui consiste à commander le filtre à partir d'un oscillateur en anneau contrôlé en tension et de portes logiques " ou exclusif " a été proposée. Grâce à cette solution, il a été montré que l'association d'un tel circuit de commande appliqué à ce type de filtre présente des avantages importants et par conséquent devrait le rendre beaucoup plus attractif pour les concepteurs. Pour répondre aux spécifications de la radiocommunication mobile, la structure classique du filtre a été optimisée pour réduire le facteur du bruit et augmenter la dynamique, ainsi une nouvelle architecture (filtre LC à capacités commutées) a été proposée. Des simulations ont été réalisées sur l'ensemble du circuit afin de prévoir les dégradations éventuelles qui peuvent être générées par ces circuits lors d'une transmission numérique (ex. p/4-DQPSK) et d'étudier ainsi l'impact du bruit de phase (gigue temporelle) généré par le circuit de commande sur le comportement du filtre. Parallèlement, un prototype composé d'un filtre LC à capacités commutées et de son circuit de commande a été fabriqué en technologie standard BiCMOS 0,35 mm, sur une puce de taille de 1,1 x 1,75 mm². Ce premier circuit a permis de prouver la faisabilité de cette architecture dans le domaine des RF. Les résultats expérimentaux confirment les simulations et sont susceptibles de rendre cette architecture originale attractive pour des applications radiofréquences.

To meet the ever-growing demand for higher data rates in communication networks and higher range and velocity resolutions in automotive radar sensors, fifth-generation (5G) new radio (NR) transceivers and radars used in autonomous vehicles use spectrally efficient modulation formats with large channel bandwidths available at millimeter wave (mm-wave) frequencies. However, designing energy-efficient broad-band transceivers with low manufacturing cost at mm-wave frequencies is extremely challenging because of the performance degradation of integrated circuit (IC) components, impairments due to packaging, and increased free-space path loss. This thesis presents a high-performance, compact, low-cost mm-wave transceiver solution for 5G NR and automotive radar sensors. A 28-GHz transceiver based on the local-oscillator (LO) phase-shifting architecture enabling gain-invariant phase tuning is designed in a 65-nm CMOS technology with wirebond-based packaging, enabling low manufacturing cost. The transceiver chip consists of a transmitter, a receiver, and an LO phase-shifting and distribution network. The transmitter employs an energy-efficient architecture based on direct-digital RF modulators (DDRMs) using digital-to-RF converters (DRFCs) to support BPSK, QPSK, 16-QAM, and 64-QAM modulation formats in 4 GHz of channel bandwidth accommodating both 5G and radar waveforms. The receiver is based on the complex-baseband zero-IF architecture using an active downconversion mixer with a transimpedance amplifier (TIA) load with up to 4 GHz of IF bandwidth. The downconverted signal is dynamically amplified by broad- band variable gain amplifiers (VGAs) based on Cherry-Hooper gain stages to compensate for the quadrature gain mismatch and relax the linearity requirement for analog-to-digital converters (ADCs). The in-phase and quadrature-phase LO signals are generated on-chip using a transformer-based quadrature hybrid driven by a coarse/fine tunable LC tank based phase shifter. The transceiver utilizes low-k transformer based fourth order networks for broadband input and output matching of the low-noise amplifier (LNA) and power amplifier (PA) as well as for interstage matching. The mm-wave chip-to-board interfaces are optimized using a scalable broadband model for wirebond interconnects developed using experimental data. A broadband dielectric characterization technique using coplanar waveguide (CPW) based test structures is developed to extract the frequency-dependent dielectric properties of the silicon substrate, typically not characterized by the foundry. This enhances the accuracy of the electromagnetic (EM) models of on-chip passive devices and interconnect parasitics, and consequently, the performance of the transceiver.

This thesis explores the technical feasibilty of creating a remote laboratory in the field of microelectronics fabrication. It also includes the evaluation of the developed laboratory as a teaching tool.
PhDElectronicEngineering

The oil and gas industry faces a lack of compact drilling devices capable of performing horizontal drilling maneuvers in depleted or abandoned wells in order to enhance oil recovery. The purpose of this project was to design and develop a smart sensing system that can be later implemented in compact drilling devices used to perform horizontal drilling to enhance oil recovery in wells. A smart sensor is the combination of a sensing element (sensor) and a microprocessor. Hence, a smart sensing system is an arrangement that consists of different sensors, where one or more have smart capabilities. The sensing system was built and tested in a laboratory setting. For this, a test bench was used as a case study to simulate the operation from a micro-drilling device. The smart sensing system integrated the sensors essential for the direct operational measurements required for the robot. The focus was on selecting reliable and sturdy components that can handle the operation Down the Hole (DTH) on the final lateral micro-drilling robot. The sensing system's recorded data was sent to a microcontroller, where it was processed and then presented visually to the operator through a User Interface (UI) developed in a cloud-based framework. The information was filtered, processed, and sent to a controller that executed commands and sent signals to the test bench’s actuators. The smart sensing system included novel modules and sensors suitable for the operation in a harsh environment such as the one faced in the drilling process. Furthermore, it was designed as an independent, flexible module that can be implemented in test benches with different settings and early robotic prototypes. The outcome of this project was a sensing system able to provide robotic drilling devices with flexibility while providing accurate and reliable measurements during their operation.