Relevant bibliographies by topics / Ternary Content Addressable Memory

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Ternary Content Addressable Memory'

Author: Grafiati
Published: 4 June 2021
Last updated: 8 February 2022

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Journal articles on the topic "Ternary Content Addressable Memory"

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Ullah, Zahid, and Sanghyeon Baeg. "Vertically Partitioned SRAM-Based Ternary Content Addressable Memory." International Journal of Engineering and Technology 4, no. 6 (2012): 760–64. http://dx.doi.org/10.7763/ijet.2012.v4.479.

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Datti, VenkataRamana, and Dr P. V. Sridevi. "A Novel Ternary Content Addressable Memory Cell." International Journal of Engineering & Technology 7, no. 4.24 (November 27, 2018): 67. http://dx.doi.org/10.14419/ijet.v7i4.24.21857.

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Ternary content addressable memories (TCAM) are used for parallel searching. The parallel searching, results high speed but consumes more power. For higher search speed applications, NOR type matchline TCAMs are useful. The NOR type matchline TCAM needs high power; therefore, the power reduction is the major objective of many reported designs. Here, a novel TCAM cell is proposed. The proposed Ternary CAM cell power consumption is 32% lesser than the NOR type matchline TCAM cell. Simulations are performed using cadence 45-nm technology.
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Khasanvis, Santosh, Mostafizur Rahman, and Csaba Andras Moritz. "Heterogeneous graphene–CMOS ternary content addressable memory." Journal of Parallel and Distributed Computing 74, no. 6 (June 2014): 2497–503. http://dx.doi.org/10.1016/j.jpdc.2013.08.002.

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Gnawali, Krishna Prasad, Seyed Nima Mozaffari, and Spyros Tragoudas. "Low Power Spintronic Ternary Content Addressable Memory." IEEE Transactions on Nanotechnology 17, no. 6 (November 2018): 1206–16. http://dx.doi.org/10.1109/tnano.2018.2869734.

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Ahmed, Ali, Kyungbae Park, and Sanghyeon Baeg. "Resource-Efficient SRAM-Based Ternary Content Addressable Memory." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 4 (April 2017): 1583–87. http://dx.doi.org/10.1109/tvlsi.2016.2636294.

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Ullah, Z., Kim Ilgon, and Sanghyeon Baeg. "Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory." IEEE Transactions on Circuits and Systems I: Regular Papers 59, no. 12 (December 2012): 2969–79. http://dx.doi.org/10.1109/tcsi.2012.2215736.

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Gupta, Mohit Kumar, and Mohd Hasan. "Robust High Speed Ternary Magnetic Content Addressable Memory." IEEE Transactions on Electron Devices 62, no. 4 (April 2015): 1163–69. http://dx.doi.org/10.1109/ted.2015.2398122.

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Singh, Preeti, and Rajesh Mehra. "FPGA based Ternary Content Addressable Memory using SRAM." International Journal of Engineering Trends and Technology 25, no. 2 (July 25, 2015): 66–69. http://dx.doi.org/10.14445/22315381/ijett-v25p212.

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Akurathi, Gangadhar, Suneel kumar Guntuku, and Babulu K. "Design and Implementation of Efficient Ternary Content Addressable Memory." International Journal on Cybernetics & Informatics 5, no. 4 (August 30, 2016): 279–87. http://dx.doi.org/10.5121/ijci.2016.5430.

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Ni, Kai, Xunzhao Yin, Ann Franchesca Laguna, Siddharth Joshi, Stefan Dünkel, Martin Trentzsch, Johannes Müller, et al. "Ferroelectric ternary content-addressable memory for one-shot learning." Nature Electronics 2, no. 11 (November 2019): 521–29. http://dx.doi.org/10.1038/s41928-019-0321-3.

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Dissertations / Theses on the topic "Ternary Content Addressable Memory"

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Mohan, Nitin. "Low-Power High-Performance Ternary Content Addressable Memory Circuits." Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/2873.

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Ternary content addressable memories (TCAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of TCAMs, high power consumption is one of the most critical challenges faced by TCAM designers. This work proposes circuit techniques for reducing TCAM power consumption. The main contribution of this work is divided in two parts: (i) reduction in match line (ML) sensing energy, and (ii) static-power reduction techniques. The ML sensing energy is reduced by employing (i) positive-feedback ML sense amplifiers (MLSAs), (ii) low-capacitance comparison logic, and (iii) low-power ML-segmentation techniques. The positive-feedback MLSAs include both resistive and active feedback to reduce the ML sensing energy. A body-bias technique can further improve the feedback action at the expense of additional area and ML capacitance. The measurement results of the active-feedback MLSA show 50-56% reduction in ML sensing energy. The measurement results of the proposed low-capacitance comparison logic show 25% and 42% reductions in ML sensing energy and time, respectively, which can further be improved by careful layout. The low-power ML-segmentation techniques include dual ML TCAM and charge-shared ML. Simulation results of the dual ML TCAM that connects two sides of the comparison logic to two ML segments for sequential sensing show 43% power savings for a small (4%) trade-off in the search speed. The charge-shared ML scheme achieves power savings by partial recycling of the charge stored in the first ML segment. Chip measurement results show that the charge-shared ML scheme results in 11% and 9% reductions in ML sensing time and energy, respectively, which can be improved to 19-25% by using a digitally controlled charge sharing time-window and a slightly modified MLSA. The static power reduction is achieved by a dual-VDD technique and low-leakage TCAM cells. The dual-VDD technique trades-off the excess noise margin of MLSA for smaller cell leakage by applying a smaller VDD to TCAM cells and a larger VDD to the peripheral circuits. The low-leakage TCAM cells trade off the speed of READ and WRITE operations for smaller cell area and leakage. Finally, design and testing of a complete TCAM chip are presented, and compared with other published designs.
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Gnawali, Krishna Prasad. "EMERGING MEMORY-BASED DESIGNS AND RESILIENCY TO RADIATION EFFECTS IN ICS." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/dissertations/1863.

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The performance of a modern computing system is improving with technology scaling due to advancements in the modern semiconductor industry. However, the power efficiency along with reliability does not scale linearly with performance efficiency. High leakage and standby power in sub 100 nm technology are critical challenges faced by circuit designers. Recent developments in device physics have shown that emerging non-volatile memories are very effective in reducing power dissipation because they eliminate stand by power and exhibit almost zero leakage powerThis dissertation studies the use of emerging non-volatile memory devices in designing circuit architecture for improving power dissipation and the performance of the computing system. More specically, it proposes a novel spintronic Ternary Content AddressableMemory (TCAM), a novel memristive TCAM with improved power and performance efficiency. Our experimental evaluation on 45 nm technology for a 256-bit word-size spintronic TCAM at a supply voltage of 1 V with a sense margin of 50 mV show that the delay is lessthan 200 ps and the per-bit search energy is approximately 3 fJ. The proposed spintronic TCAM consumes at least 30% less energy when compared to state-of-the-art TCAM designs. The search delay on a 144-bit proposed memristive TCAM at a supply voltage of 1 V and a sense margin of 140 mV is 175 ps with per bit search energy of 1.2 fJ on a 45 nm technology. It is 1.12 x times faster and dissipates 67% less search energy per bit than the fastest existing 144-bit MTCAM design.Emerging non-volatile memories are well known for their ability to perform fast analog multiplication and addition when they are arranged in crossbar fashion and are especially suited for neural network applications. However, such systems require the on-chip implementation of the backpropagation algorithm to accommodate process variations. This dissertation studies the impact of process variation in training memristive neural network architecture. It proposes a low hardware overhead on-chip implementation of the backpropagation algorithm that utilizes effectively the very dense memristive cross-bar arrayand is resilient to process variations.Another important issue that needs a careful study due to shrinking technology node is the impact of space or terrestrial radiation in Integrated Circuits (ICs) because the probability of a high energy particle causing an error increases with a decrease in thethreshold voltage and the noise margin. Moreover, single-event effects (SEEs) sensitivity depends on the set of input vectors used at the time of testing due to logical masking. This dissertation analyzes the impact of input test set on the cross section of the microprocessorand proposes a mechanism to derive a high-quality input test set using an automatic test pattern generation (ATPG) for radiation testing of microprocessors arithmetic and logical units..
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Lee, Jack. "Smart Memory: An Inexact Content-Addressable Memory." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4605.

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The function of a Content-Addressable Memory (CAM) is to efficiently search the information stored in the memory, by using hardware rather than software with a corresponding improvement in searching speed. This hardware allows a parallel search by matching the data stored in memory to a search key rather than sequentially searching address by address as is done in a Random Access Memory. Although existing CAMs are more efficient in finding relevant information than RAM, there are additional improvements that can be made to further improve its efficiency. For example, previous CAMs use a word parallel searching scheme that can only identify exact matches. To find the best (closest) match, previous CAMs had to use bit serial approaches. Although still more efficient than RAM searching, these CAMs were limited by the word size (bit width) of the memory. Responding to this inefficiency, the CAM described in this thesis improves best-fit searching by using analog design in combination with digital design. This design retains a mismatch line to collect the result of the comparison of each bit of a word which is decoded by a simple flash A/D. This means that after a single operation the best-fit plus all words with zero to three bits of mismatch, are determined. This word/bit parallel searching makes this CAM more efficient than existing CAMs. The best-fit function of this CAM is good for database retrieval, communications and error correction circuitry. By using the high speed searching and the inexact match feature, this CAM also provides efficient sorting and set operations. The accumulated searching time is shortened when compared to regular CAM and RAM. The inexact CAM in this thesis is designed using mixed analog/digital design in a 2~ CMOS technology.
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Chen, Wanlong. "Memristor content addressable memory : theory, design and application." Thesis, University of Kent, 2017. https://kar.kent.ac.uk/61076/.

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The memristor has been proposed as the fourth circuit element. Among the emerging nano-technologies, the memristor has become a very promising candidate for building storage structures because of its shorter switching time, higher capacity and lower power consumption. In this thesis, I will first introduce a new memristor model with controllable window functions, which is more authentic and flexible than those existing memristor models. Then I will present my novel design of a Memristor Content Addressable Memory (Memristor-CAM) structure that is based on my own design of Memristor-CAM cells. The major contribution of this work is the fuzzy look-up functionality, which is achieved by summing up the current of the matched cell lines in the Memristor-CAM. In addition, this fuzzy look-up functionality of the new Memristor-CAM design could be further extended in order to fit into a lot of practical applications. With the benefits of memristors, this Memristor-CAM storage structure could reduce the power consumption, increase the capacity and improve the performance of computer memory. My new design is tested in a common experimental design that includes computer simulations and circuit emulations. The results of my experiments support the validity of my contributions and allow further analysis and insights on the behaviours of memristors when different settings are applied.
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Podaima, Jason Edward. "A content addressable FIFO for shared memory ATM switch architectures." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0001/MQ40944.pdf.

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Blair, Gerard M. "Content addressable memory : design and usage for general purpose computing." Thesis, University of Edinburgh, 1986. http://hdl.handle.net/1842/15014.

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HOR-MEYLL, MALENA OSORIO. "A CONTENT ADDRESSABLE MEMORY BASED ARCHITECTURE TO SUPPORT A PROLOG VIRTUAL MACHINE." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 1992. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14596@1.

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COORDENAÇÃO DE APERFEIÇOAMENTO DO PESSOAL DE ENSINO SUPERIOR
FUNDAÇÃO DE APOIO À PESQUISA DO ESTADO DO RIO DE JANEIRO
As arquiteturas convencionais de computadores, baseadas no modelo de Von Neumann, não implementam eficientemente a linguagem Prolog, fundamentada em mecanismos de unificação e retrocesso automático. Este trabalho propõe a arquitetura de um acelerador, baseado a uma máquina virtual Prolog (PLM) desenvolvida na COPPE/UFRJ. A arquitetura proposta aumenta a eficiência da máquina virtual explorando o paralelismo da memória associativa na realização do mecanismo de retrocesso. O impacto no desempenho da máquina virtual decorrente da nova arquitetura foi avaliado por simulação utilizando programas clássicos encontrados na literatura.
Conventional computer architectures based on Von Neumann’s model do not efficiently implement the Prolog language, founded on unification and automatic backtracking mechanisms. This work presents the architecture of a content addressable memory accelerator to be connected to a Prolog Virtual machine (PLM) developed at COPPE/UFRJ. The presented architecture increases the virtual machine’s efficiency by exploring the content addressable memory’s parallelism to implement the backtracking mechanism. The impact on the virtual machine’s performance due to the new architecture was evaluated by simulation, using classical programs found on the literature.
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Abdelhadi, Ameer M. S. "Architecture of block-RAM-based massively parallel memory structures : multi-ported memories and content-addressable memories." Thesis, University of British Columbia, 2016. http://hdl.handle.net/2429/59146.

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Since they were first introduced three decades ago, Field-Programmable Gate Arrays (FPGAs) have evolved from being merely used as glue-logic to implementing entire compute accelerators. These massively parallel systems demand highly parallel memory structures to keep pace with their concurrent nature since memories are usually the bottleneck of computation performance. However, the vast majority of FPGA devices provide dual-ported SRAM blocks only. In this dissertation, we propose new ways to build area-efficient, high-performance SRAM-based parallel memory structures in FPGAs, specifically Multi-Ported Random Access Memory and Content-Addressable Memory (CAM). While parallel computation demands more RAM ports, leading Multi-Ported Random Access Memory techniques in FPGAs have relatively large overhead in resource usage. As a result, we have produced new design techniques that are near-optimal in resource overhead and have several practical advantages. The suggested method reduces RAM usage by over 44% and improves clock speed by over 76% compared to the best of previous approaches. Furthermore, we propose a novel switched-ports technique that allows further area reduction if some RAM ports are not simultaneously active. A memory compiler is proposed to generalize the previous approach and allow generating Multi-Switched-Ports Random Access Memory. Content-Addressable Memories (CAMs), the hardware implementation of associative arrays, are capable of searching the entire memory space for a specific value within a single clock cycle. CAMs are massively parallel search engines accessing all memory content to compare with the searched pattern simultaneously. CAMs are used in a variety of scientific fields requiring high-speed associative searches. Despite their importance, FPGAs lack an area-efficient CAM implementation. We propose a series of scalable, area-efficient, and high-performance Binary Content-Addressable Memories (BCAMs) based on hierarchical search and data compression methods. Compared to current RAM-based BCAM architectures, our BCAMs require a maximum of 18% the RAM storage while enhancing clock speed by 45% on average, hence exhibiting a superior single-cycle search rate. As a result, we can build faster and more cost-effective accelerators to solve some of the most important computational problems.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Wright, Derek. "A Comprehensive Test and Diagnostic Strategy for TCAMs." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/809.

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Content addressable memories (CAMs) are gaining popularity with computer networks. Testing costs of CAMs are extremely high owing to their unique configuration. In this thesis, a fault analysis is carried out on an industrial ternary CAM (TCAM) design, and search path test algorithms are designed. The proposed algorithms are able to test the TCAM array, multiple-match resolver (MMR), and match address encoder (MAE). The tests represent a 6x decrease in test complexity compared to existing algorithms, while dramatically improving fault coverage.
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Govindaraj, Rekha. "Emerging Non-Volatile Memory Technologies for Computing and Security." Scholar Commons, 2018. https://scholarcommons.usf.edu/etd/7674.

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With CMOS technology scaling reaching its limitations rigorous research of alternate and competent technologies is paramount to push the boundaries of computing. Spintronic and resistive memories have proven to be effective alternatives in terms of area, power and performance to CMOS because of their non-volatility, ability for logic computing and easy integration with CMOS. However, deeper investigations to understand their physical phenomenon and improve their properties such as writability, stability, reliability, endurance, uniformity with minimal device-device variations is necessary for deployment as memories in commercial applications. Application of these technologies beyond memory and logic are investigated in this thesis i.e. for security of integrated circuits and systems and special purpose memories. We proposed a spintonic based special purpose memory for search applications, present design analysis and techniques to improve the performance for larger word lengths upto 256 bits. Salient characteristics of RRAM is studied and exploited in the design of widely accepted hardware security primitives such as Physically Unclonable Function (PUF) and True Random Number Generators (TRNG). Vulnerability of these circuits to adversary attacks and countermeasures are proposed. Proposed PUF can be implemented within 1T-1R conventional memory architecture which offers area advantages compared to RRAM memory and cross bar array PUFs with huge number of challenge response pairs. Potential application of proposed strong arbiter PUF in the Internet of things is proposed and performance is evaluated theoretically with valid assumptions on the maturity of RRAM technology. Proposed TRNG effectively utilizes the random telegraph noise in RRAM current to generate random bit stream. TRNG is evaluated for sufficient randomness in the random bit stream generated. Vulnerability and countermeasures to adversary attacks are also studied. Finally, in thesis we investigated and extended the application of emerging non-volatile memory technologies for search and security in integrated circuits and systems.
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Books on the topic "Ternary Content Addressable Memory"

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Podaima, Jason Edward. A content addressable FIFO for shared memory ATM switch architectures. Ottawa: National Library of Canada, 1998.

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1943-, Hall John, and United States. National Aeronautics and Space Administration., eds. Content Addressable Memory Project: Semiannual progress report. [Washington, DC]: National Aeronautics and Space Administration, 1992.

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Content Addressable Memory Project: Semiannual progress report, March-August 1991. [Washington, DC]: National Aeronautics and Space Administration, 1991.

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Chaffin, Roger, Topher R. Logan, and Kristen T. Begosh. Performing from memory. Edited by Susan Hallam, Ian Cross, and Michael Thaut. Oxford University Press, 2012. http://dx.doi.org/10.1093/oxfordhb/9780199298457.013.0033.

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This article discusses memory for performance, focusing on the role of serial chaining and content addressability. Two areas of the episodic memory literature are particularly relevant to the discussion: oral traditions and expert memory. In oral traditions, materials such as children's rhymes and folk songs are handed down from one generation to another without the benefit of written records, often for hundreds of years. Expert memory results from years of training and the effective use of retrieval schemes. Expert memorists develop retrieval strategies to make their memories content-addressable so that they can find the information they needwhenthey need it. Anders Ericsson's theory of expert memory is used to explain how experienced performers memorize, as opposed to simply learn, a new piece.
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Book chapters on the topic "Ternary Content Addressable Memory"

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Prasad, Vikash, and Debaprasad Das. "Design of Ternary Content-Addressable Memory Using CNTFET." In Advances in Intelligent Systems and Computing, 853–58. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7834-2_80.

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Mullai, G. P., and C. Sheeba Joice. "Implementation of Z-Ternary Content-Addressable Memory Using FPGA." In Advances in Intelligent Systems and Computing, 855–63. New Delhi: Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2656-7_77.

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Santhi, C., and Moparthy Gurunadha Babu. "Design and Implementation of Reversible Logic Based Ternary Content Addressable Memory." In Smart Intelligent Computing and Applications, 405–13. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9690-9_42.

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Ghosh, Puja, and P. Rangababu. "Design and Implementation of Ternary Content Addressable Memory (TCAM) Based Hierarchical Motion Estimation for Video Processing." In Communications in Computer and Information Science, 557–69. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7_54.

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Kohonen, Teuvo. "Associative Memory, Content Addressing, and Associative Recall." In Content-Addressable Memories, 1–37. Berlin, Heidelberg: Springer Berlin Heidelberg, 1987. http://dx.doi.org/10.1007/978-3-642-83056-3_1.

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Guccione, Steven A., Delon Levi, and Daniel Downs. "A Reconfigurable Content Addressable Memory." In Lecture Notes in Computer Science, 882–89. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45591-4_122.

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Allauddin, Raheel, Stuart Boehmer, Elizabeth C. Behrman, Kavitha Gaddam, and James E. Steck. "Quantum Simulataneous Recurrent Networks for Content Addressable Memory." In Quantum Inspired Intelligent Systems, 57–76. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-78532-3_3.

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Bacha, Hamid. "A Prolog Abstract Machine for Content-Addressable Memory." In VLSI for Artificial Intelligence and Neural Networks, 153–64. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3752-6_15.

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Zhu, Yidong, Xiao Wang, Tingwen Huang, and Zhigang Zeng. "Memristor-Based Neuromorphic System with Content Addressable Memory Structure." In Advances in Neural Networks – ISNN 2016, 681–90. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-40663-3_78.

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Chang, Meng-Chou, and Yen-Ting Kuo. "Design of a Two-Phase Adiabatic Content-Addressable Memory." In Lecture Notes in Electrical Engineering, 577–83. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-21762-3_75.

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Conference papers on the topic "Ternary Content Addressable Memory"

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Cho, Mannhee, and Youngmin Kim. "Nanoelectromechanical Memory Switch based Ternary Content-Addressable Memory." In 2020 International SoC Design Conference (ISOCC). IEEE, 2020. http://dx.doi.org/10.1109/isocc50952.2020.9332924.

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Rouhi, Sadegh, and Sattar Mirzakuchaki. "Compact 5T2M ternary content addressable memory cell." In 2019 16th International Multi-Conference on Systems, Signals & Devices (SSD). IEEE, 2019. http://dx.doi.org/10.1109/ssd.2019.8893279.

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Ray, Sanchita Saha, and Surajeet Ghosh. "Smart Ternary Content Addressable Memory (STCAM) architecture." In 2012 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT). IEEE, 2012. http://dx.doi.org/10.1109/icaccct.2012.6320817.

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Zheng, Le, Sangho Shin, and Sung-Mo Steve Kang. "Memristors-based Ternary Content Addressable Memory (mTCAM)." In 2014 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2014. http://dx.doi.org/10.1109/iscas.2014.6865619.

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Dhiman, Rajni, Manjit Kaur, and Gurmohan Singh. "Memristor based ternary content addressable memory (MTCAM) Cell." In 2015 2nd International Conference on Recent Advances in Engineering & Computational Sciences (RAECS). IEEE, 2015. http://dx.doi.org/10.1109/raecs.2015.7453403.

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Jiang, Weirong. "Scalable Ternary Content Addressable Memory implementation using FPGAs." In 2013 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS). IEEE, 2013. http://dx.doi.org/10.1109/ancs.2013.6665177.

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Jayashree, S., and N. Shivashankarappa. "Deep packet inspection using ternary content addressable memory." In 2014 International Conference on Circuits, Communication, Control and Computing (I4C). IEEE, 2014. http://dx.doi.org/10.1109/cimca.2014.7057841.

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Foysal, Md Atik, Md Zahidul Anam, Md Shoriful Islam, Intisar Tahmid, and Kartick Mondal. "Performance analysis of ternary content addressable memory (TCAM)." In 2015 International Conference on Advances in Electrical Engineering (ICAEE). IEEE, 2015. http://dx.doi.org/10.1109/icaee.2015.7506807.

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Ullah, Zahid, Manish Kumar Jaiswal, Y. C. Chan, and Ray C. C. Cheung. "FPGA Implementation of SRAM-based Ternary Content Addressable Memory." In 2012 26th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE, 2012. http://dx.doi.org/10.1109/ipdpsw.2012.47.

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Bahloul, Mohamed A., Rawan Naous, and M. Masmoudi. "Hardware emulation of Memristor based Ternary Content Addressable Memory." In 2017 14th International Multi-Conference on Systems, Signals & Devices (SSD). IEEE, 2017. http://dx.doi.org/10.1109/ssd.2017.8167029.

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Reports on the topic "Ternary Content Addressable Memory"

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Levy, Saul Y., J. S. Hall, and Donald E. Smith. Content Addressable Memory Project. Fort Belvoir, VA: Defense Technical Information Center, November 1990. http://dx.doi.org/10.21236/ada234524.

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Lee, Jack. Smart Memory: An Inexact Content-Addressable Memory. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6489.

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Wang, Weizhong. Feasibility Study on Magnetic Content Addressable Memory. Fort Belvoir, VA: Defense Technical Information Center, May 2007. http://dx.doi.org/10.21236/ada468138.

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Loos, Hendricus G. Quadratic Hadamard Memories 1: Adaptive Stochastic Content-Addressable Memory. Fort Belvoir, VA: Defense Technical Information Center, December 1989. http://dx.doi.org/10.21236/ada217224.

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Grossberg, Stephen. Content-Addressable Memory Storage by Neural Networks: A General Model and Global Liapunov Method,. Fort Belvoir, VA: Defense Technical Information Center, March 1988. http://dx.doi.org/10.21236/ada192716.

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