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Mohan, Nitin. "Low-Power High-Performance Ternary Content Addressable Memory Circuits." Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/2873.
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Ternary content addressable memories (TCAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of TCAMs, high power consumption is one of the most critical challenges faced by TCAM designers. This work proposes circuit techniques for reducing TCAM power consumption. The main contribution of this work is divided in two parts: (i) reduction in match line (ML) sensing energy, and (ii) static-power reduction techniques. The ML sensing energy is reduced by employing (i) positive-feedback ML sense amplifiers (MLSAs), (ii) low-capacitance comparison logic, and (iii) low-power ML-segmentation techniques. The positive-feedback MLSAs include both resistive and active feedback to reduce the ML sensing energy. A body-bias technique can further improve the feedback action at the expense of additional area and ML capacitance. The measurement results of the active-feedback MLSA show 50-56% reduction in ML sensing energy. The measurement results of the proposed low-capacitance comparison logic show 25% and 42% reductions in ML sensing energy and time, respectively, which can further be improved by careful layout. The low-power ML-segmentation techniques include dual ML TCAM and charge-shared ML. Simulation results of the dual ML TCAM that connects two sides of the comparison logic to two ML segments for sequential sensing show 43% power savings for a small (4%) trade-off in the search speed. The charge-shared ML scheme achieves power savings by partial recycling of the charge stored in the first ML segment. Chip measurement results show that the charge-shared ML scheme results in 11% and 9% reductions in ML sensing time and energy, respectively, which can be improved to 19-25% by using a digitally controlled charge sharing time-window and a slightly modified MLSA. The static power reduction is achieved by a dual-VDD technique and low-leakage TCAM cells. The dual-VDD technique trades-off the excess noise margin of MLSA for smaller cell leakage by applying a smaller VDD to TCAM cells and a larger VDD to the peripheral circuits. The low-leakage TCAM cells trade off the speed of READ and WRITE operations for smaller cell area and leakage. Finally, design and testing of a complete TCAM chip are presented, and compared with other published designs.
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Gnawali, Krishna Prasad. "EMERGING MEMORY-BASED DESIGNS AND RESILIENCY TO RADIATION EFFECTS IN ICS." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/dissertations/1863.
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The performance of a modern computing system is improving with technology scaling due to advancements in the modern semiconductor industry. However, the power efficiency along with reliability does not scale linearly with performance efficiency. High leakage and standby power in sub 100 nm technology are critical challenges faced by circuit designers. Recent developments in device physics have shown that emerging non-volatile memories are very effective in reducing power dissipation because they eliminate stand by power and exhibit almost zero leakage powerThis dissertation studies the use of emerging non-volatile memory devices in designing circuit architecture for improving power dissipation and the performance of the computing system. More specically, it proposes a novel spintronic Ternary Content AddressableMemory (TCAM), a novel memristive TCAM with improved power and performance efficiency. Our experimental evaluation on 45 nm technology for a 256-bit word-size spintronic TCAM at a supply voltage of 1 V with a sense margin of 50 mV show that the delay is lessthan 200 ps and the per-bit search energy is approximately 3 fJ. The proposed spintronic TCAM consumes at least 30% less energy when compared to state-of-the-art TCAM designs. The search delay on a 144-bit proposed memristive TCAM at a supply voltage of 1 V and a sense margin of 140 mV is 175 ps with per bit search energy of 1.2 fJ on a 45 nm technology. It is 1.12 x times faster and dissipates 67% less search energy per bit than the fastest existing 144-bit MTCAM design.Emerging non-volatile memories are well known for their ability to perform fast analog multiplication and addition when they are arranged in crossbar fashion and are especially suited for neural network applications. However, such systems require the on-chip implementation of the backpropagation algorithm to accommodate process variations. This dissertation studies the impact of process variation in training memristive neural network architecture. It proposes a low hardware overhead on-chip implementation of the backpropagation algorithm that utilizes effectively the very dense memristive cross-bar arrayand is resilient to process variations.Another important issue that needs a careful study due to shrinking technology node is the impact of space or terrestrial radiation in Integrated Circuits (ICs) because the probability of a high energy particle causing an error increases with a decrease in thethreshold voltage and the noise margin. Moreover, single-event effects (SEEs) sensitivity depends on the set of input vectors used at the time of testing due to logical masking. This dissertation analyzes the impact of input test set on the cross section of the microprocessorand proposes a mechanism to derive a high-quality input test set using an automatic test pattern generation (ATPG) for radiation testing of microprocessors arithmetic and logical units..
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Lee, Jack. "Smart Memory: An Inexact Content-Addressable Memory." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4605.
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The function of a Content-Addressable Memory (CAM) is to efficiently search the information stored in the memory, by using hardware rather than software with a corresponding improvement in searching speed. This hardware allows a parallel search by matching the data stored in memory to a search key rather than sequentially searching address by address as is done in a Random Access Memory. Although existing CAMs are more efficient in finding relevant information than RAM, there are additional improvements that can be made to further improve its efficiency. For example, previous CAMs use a word parallel searching scheme that can only identify exact matches. To find the best (closest) match, previous CAMs had to use bit serial approaches. Although still more efficient than RAM searching, these CAMs were limited by the word size (bit width) of the memory. Responding to this inefficiency, the CAM described in this thesis improves best-fit searching by using analog design in combination with digital design. This design retains a mismatch line to collect the result of the comparison of each bit of a word which is decoded by a simple flash A/D. This means that after a single operation the best-fit plus all words with zero to three bits of mismatch, are determined. This word/bit parallel searching makes this CAM more efficient than existing CAMs. The best-fit function of this CAM is good for database retrieval, communications and error correction circuitry. By using the high speed searching and the inexact match feature, this CAM also provides efficient sorting and set operations. The accumulated searching time is shortened when compared to regular CAM and RAM. The inexact CAM in this thesis is designed using mixed analog/digital design in a 2~ CMOS technology.
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Chen, Wanlong. "Memristor content addressable memory : theory, design and application." Thesis, University of Kent, 2017. https://kar.kent.ac.uk/61076/.
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The memristor has been proposed as the fourth circuit element. Among the emerging nano-technologies, the memristor has become a very promising candidate for building storage structures because of its shorter switching time, higher capacity and lower power consumption. In this thesis, I will first introduce a new memristor model with controllable window functions, which is more authentic and flexible than those existing memristor models. Then I will present my novel design of a Memristor Content Addressable Memory (Memristor-CAM) structure that is based on my own design of Memristor-CAM cells. The major contribution of this work is the fuzzy look-up functionality, which is achieved by summing up the current of the matched cell lines in the Memristor-CAM. In addition, this fuzzy look-up functionality of the new Memristor-CAM design could be further extended in order to fit into a lot of practical applications. With the benefits of memristors, this Memristor-CAM storage structure could reduce the power consumption, increase the capacity and improve the performance of computer memory. My new design is tested in a common experimental design that includes computer simulations and circuit emulations. The results of my experiments support the validity of my contributions and allow further analysis and insights on the behaviours of memristors when different settings are applied.
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Podaima, Jason Edward. "A content addressable FIFO for shared memory ATM switch architectures." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0001/MQ40944.pdf.
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Blair, Gerard M. "Content addressable memory : design and usage for general purpose computing." Thesis, University of Edinburgh, 1986. http://hdl.handle.net/1842/15014.
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HOR-MEYLL, MALENA OSORIO. "A CONTENT ADDRESSABLE MEMORY BASED ARCHITECTURE TO SUPPORT A PROLOG VIRTUAL MACHINE." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 1992. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14596@1.
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COORDENAÇÃO DE APERFEIÇOAMENTO DO PESSOAL DE ENSINO SUPERIORFUNDAÇÃO DE APOIO À PESQUISA DO ESTADO DO RIO DE JANEIRO
As arquiteturas convencionais de computadores, baseadas no modelo de Von Neumann, não implementam eficientemente a linguagem Prolog, fundamentada em mecanismos de unificação e retrocesso automático. Este trabalho propõe a arquitetura de um acelerador, baseado a uma máquina virtual Prolog (PLM) desenvolvida na COPPE/UFRJ. A arquitetura proposta aumenta a eficiência da máquina virtual explorando o paralelismo da memória associativa na realização do mecanismo de retrocesso. O impacto no desempenho da máquina virtual decorrente da nova arquitetura foi avaliado por simulação utilizando programas clássicos encontrados na literatura.
Conventional computer architectures based on Von Neumann’s model do not efficiently implement the Prolog language, founded on unification and automatic backtracking mechanisms. This work presents the architecture of a content addressable memory accelerator to be connected to a Prolog Virtual machine (PLM) developed at COPPE/UFRJ. The presented architecture increases the virtual machine’s efficiency by exploring the content addressable memory’s parallelism to implement the backtracking mechanism. The impact on the virtual machine’s performance due to the new architecture was evaluated by simulation, using classical programs found on the literature.
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Abdelhadi, Ameer M. S. "Architecture of block-RAM-based massively parallel memory structures : multi-ported memories and content-addressable memories." Thesis, University of British Columbia, 2016. http://hdl.handle.net/2429/59146.
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Since they were first introduced three decades ago, Field-Programmable Gate Arrays (FPGAs) have evolved from being merely used as glue-logic to implementing entire compute accelerators. These massively parallel systems demand highly parallel memory structures to keep pace with their concurrent nature since memories are usually the bottleneck of computation performance. However, the vast majority of FPGA devices provide dual-ported SRAM blocks only. In this dissertation, we propose new ways to build area-efficient, high-performance SRAM-based parallel memory structures in FPGAs, specifically Multi-Ported Random Access Memory and Content-Addressable Memory (CAM). While parallel computation demands more RAM ports, leading Multi-Ported Random Access Memory techniques in FPGAs have relatively large overhead in resource usage. As a result, we have produced new design techniques that are near-optimal in resource overhead and have several practical advantages. The suggested method reduces RAM usage by over 44% and improves clock speed by over 76% compared to the best of previous approaches. Furthermore, we propose a novel switched-ports technique that allows further area reduction if some RAM ports are not simultaneously active. A memory compiler is proposed to generalize the previous approach and allow generating Multi-Switched-Ports Random Access Memory. Content-Addressable Memories (CAMs), the hardware implementation of associative arrays, are capable of searching the entire memory space for a specific value within a single clock cycle. CAMs are massively parallel search engines accessing all memory content to compare with the searched pattern simultaneously. CAMs are used in a variety of scientific fields requiring high-speed associative searches. Despite their importance, FPGAs lack an area-efficient CAM implementation. We propose a series of scalable, area-efficient, and high-performance Binary Content-Addressable Memories (BCAMs) based on hierarchical search and data compression methods. Compared to current RAM-based BCAM architectures, our BCAMs require a maximum of 18% the RAM storage while enhancing clock speed by 45% on average, hence exhibiting a superior single-cycle search rate. As a result, we can build faster and more cost-effective accelerators to solve some of the most important computational problems.Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Wright, Derek. "A Comprehensive Test and Diagnostic Strategy for TCAMs." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/809.
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Content addressable memories (CAMs) are gaining popularity with computer networks. Testing costs of CAMs are extremely high owing to their unique configuration. In this thesis, a fault analysis is carried out on an industrial ternary CAM (TCAM) design, and search path test algorithms are designed. The proposed algorithms are able to test the TCAM array, multiple-match resolver (MMR), and match address encoder (MAE). The tests represent a 6x decrease in test complexity compared to existing algorithms, while dramatically improving fault coverage.
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Govindaraj, Rekha. "Emerging Non-Volatile Memory Technologies for Computing and Security." Scholar Commons, 2018. https://scholarcommons.usf.edu/etd/7674.
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With CMOS technology scaling reaching its limitations rigorous research of alternate and competent technologies is paramount to push the boundaries of computing. Spintronic and resistive memories have proven to be effective alternatives in terms of area, power and performance to CMOS because of their non-volatility, ability for logic computing and easy integration with CMOS. However, deeper investigations to understand their physical phenomenon and improve their properties such as writability, stability, reliability, endurance, uniformity with minimal device-device variations is necessary for deployment as memories in commercial applications. Application of these technologies beyond memory and logic are investigated in this thesis i.e. for security of integrated circuits and systems and special purpose memories. We proposed a spintonic based special purpose memory for search applications, present design analysis and techniques to improve the performance for larger word lengths upto 256 bits. Salient characteristics of RRAM is studied and exploited in the design of widely accepted hardware security primitives such as Physically Unclonable Function (PUF) and True Random Number Generators (TRNG). Vulnerability of these circuits to adversary attacks and countermeasures are proposed. Proposed PUF can be implemented within 1T-1R conventional memory architecture which offers area advantages compared to RRAM memory and cross bar array PUFs with huge number of challenge response pairs. Potential application of proposed strong arbiter PUF in the Internet of things is proposed and performance is evaluated theoretically with valid assumptions on the maturity of RRAM technology. Proposed TRNG effectively utilizes the random telegraph noise in RRAM current to generate random bit stream. TRNG is evaluated for sufficient randomness in the random bit stream generated. Vulnerability and countermeasures to adversary attacks are also studied. Finally, in thesis we investigated and extended the application of emerging non-volatile memory technologies for search and security in integrated circuits and systems.
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Ly, Denys. "Mémoires résistives et technologies 3D monolithiques pour processeurs neuromorphiques impulsionnels et reconfigurables." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT016.
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Le cerveau humain est un système computationnel complexe mais énergétiquement efficace qui excelle aux applications cognitives grâce à sa capacité naturelle à faire de l'inférence. À l'inverse, les systèmes de calculs traditionnels reposant sur la classique architecture de Von Neumann exigent des consommations de puissance importantes pour exécuter de telles tâches. Ces considérations ont donné naissance à la fameuse approche neuromorphique, qui consiste à construire des systèmes de calculs inspirés du cerveau. Dans cette thèse, nous examinons l'utilisation de technologies novatrices, à savoir les mémoires résistives (RRAMs) et les technologies tridimensionnelles (3D) monolithiques, pour permettre l'implémentation matérielle compacte de processeurs neuromorphiques impulssionnels (SNNs) et reconfigurables à faible puissance. Dans un premier temps, nous fournirons une étude détaillée sur l'impact des propriétés électriques des RRAMs dans les SNNs utilisant des synapses à base de RRAMs, et entraînés avec des méthodes d'apprentissage non-supervisées (plasticité fonction du temps d'occurence des impulsions, STDP). Notamment, nous clarifierons le rôle de la variabilité synaptique provenant de la variabilité résistive des RRAMs. Dans un second temps, nous étudierons l'utilisation de matrices de mémoires ternaires adressables par contenu (TCAMs) à base de RRAMs en tant que tables de routage synaptique dans les processeurs SNNs, afin de permettre la reconfigurabilité de la topologie du réseau. Pour ce faire, nous présenterons des caractérisations électriques approfondies de deux circuits TCAMs à base de RRAMs: (i) la structure TCAM la plus courante avec deux-transistors/deux-RRAMs (2T2R), et (ii) une nouvelle structure TCAM avec un-transistor/deux-RRAMs/un-transistor (1T2R1T), toutes deux dotées de la plus petite surface silicium à l'heure actuelle. Nous comparerons les deux structures en termes de performances, fiabilité et endurance. Pour finir, nous explorerons le potentiel des technologies 3D monolithiques en vue d'améliorer l'efficacité en surface. En plus de la classique intégration monolithique des RRAMs dans le retour en fin de ligne (back-end-of-line) des technologies CMOS, nous analyserons l'empilement vertical de transistors CMOS les uns au-dessus des autres. Pour cela, nous démontrerons la possibilité d'intégrer monolithiquement deux niveaux de transistors CMOS avec un niveau de dispositifs RRAMs. Cette preuve de concept sera appuyée par des caractérisations électriques effectuées sur les dispositifs fabriquésThe human brain is a complex, energy-efficient computational system that excels at cognitive tasks thanks to its natural capability to perform inference. By contrast, conventional computing systems based on the classic Von Neumann architecture require large power budget to execute such assignments. Herein comes the idea to build brain-inspired electronic computing systems, the so-called neuromorphic approach. In this thesis, we explore the use of novel technologies, namely Resistive Memories (RRAMs) and three-dimensional (3D) monolithic technologies, to enable the hardware implementation of compact, low-power reconfigurable Spiking Neural Network (SNN) processors. We first provide a comprehensive study of the impact of RRAM electrical properties on SNNs with RRAM synapses and trained with unsupervised learning (Spike-Timing-Dependent Plasticity (STDP)). In particular, we clarify the role of synaptic variability originating from RRAM resistance variability. Second, we investigate the use of RRAM-based Ternary Content-Addressable Memory (TCAM) arrays as synaptic routing tables in SNN processors to enable on-the-fly reconfigurability of network topology. For this purpose, we present in-depth electrical characterisations of two RRAM-based TCAM circuits: (i) the most common two-transistors/two-RRAMs (2T2R) RRAM-based TCAM, and (ii) a novel one-transistor/two-RRAMs/one-transistor (1T2R1T) RRAM-based TCAM, both featuring the smallest silicon area up-to-date. We compare both structures in terms of performance, reliability, and endurance. Finally, we explore the potential of 3D monolithic technologies to improve area-efficiency. In addition to the conventional monolithic integration of RRAMs in the back-end-of-line of CMOS technology, we examine the vertical stacking of CMOS over CMOS transistors. To this end, we demonstrate the full 3D monolithic integration of two tiers of CMOS transistors with one tier of RRAM devices, and present electrical characterisations performed on the fabricated devices
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Thames, John Lane. "Advancing cyber security with a semantic path merger packet classification algorithm." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45872.
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This dissertation investigates and introduces novel algorithms, theories, and supporting frameworks to significantly improve the growing problem of Internet security. A distributed firewall and active response architecture is introduced that enables any device within a cyber environment to participate in the active discovery and response of cyber attacks. A theory of semantic association systems is developed for the general problem of knowledge discovery in data. The theory of semantic association systems forms the basis of a novel semantic path merger packet classification algorithm. The theoretical aspects of the semantic path merger packet classification algorithm are investigated, and the algorithm's hardware-based implementation is evaluated along with comparative analysis versus content addressable memory. Experimental results show that the hardware implementation of the semantic path merger algorithm significantly outperforms content addressable memory in terms of energy consumption and operational timing.
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Tirdad, Kamran. "Exploiting the Computational Power of Ternary Content Addressable Memory." Thesis, 2011. http://hdl.handle.net/10012/6315.
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Ternary Content Addressable Memory or in short TCAM is a special type of memory that can execute a certain set of operations in parallel on all of its words. Because of
power consumption and relatively small storage capacity, it has only been used in special environments. Over the past few years its cost has been reduced and its storage capacity has increased signifi cantly and these exponential trends are continuing. Hence it can be used in more general environments for larger problems. In this research we study how to exploit its computational power in order to speed up fundamental problems and needless to say that we barely scratched the surface. The main problems that has been addressed in our research are namely Boolean matrix multiplication, approximate subset queries using bloom filters, Fixed universe priority queues and network flow classi cation. For Boolean matrix multiplication our simple algorithm has a run time of O (d(N^2)/w) where N is the
size of the square matrices, w is the number of bits in each word of TCAM and d is the
maximum number of ones in a row of one of the matrices. For the Fixed universe priority
queue problems we propose two data structures one with constant time complexity and
space of O((1/ε)n(U^ε)) and the other one in linear space and amortized time complexity of
O((lg lg U)/(lg lg lg U)) which beats the best possible data structure in the RAM model namely Y-fast trees. Considering each word of TCAM as a bloom filter, we modify the hash functions of the bloom filter and propose a data structure which can use the information capacity of each word of TCAM more efi ciently by using the co-occurrence probability of possible members. And finally in the last chapter we propose a novel technique for network flow classi fication using TCAM.
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Liu, Wen-Yen, and 劉文彥. "Low Power Ternary Content Addressable Memory Array and Circuit Design." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/18669233118729605377.
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碩士國立交通大學
電子工程系所
95
A new high speed, low-power and noise-tolerant ternary content-addressable memories (TCAMs) using multi-mode data retention power gating technique and super cut-off power-gating technique are proposed in this thesis. These two techniques significantly reduce cell leakage current by taking the advantage of input don’t care patterns of IPv6 addressing lookup application. Furthermore, search power is also reduced by applying super cut-off power gating technique under search operation. butterfly match-line scheme reduces switching activity also. A 256-word x 144-bit low-power ternary CAM is also proposed. Based on 65nm Berkeley Predictive Technology Model, simulation results shows that 0.23ns search time and 0.047fJ/bit/search energy metric is achieved. Layout is implemented in TSMC 0.13μm CMOS technology, which indicates a 19% area overhead.
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Lai, Chun-Kai, and 賴駿凱. "Design of a Low-Power and Self-Repairable Ternary Content Addressable Memory." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/49414221325596135387.
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碩士國立中央大學
電機工程研究所
96
Ternary content addressable memory (TCAM) is widely used in digital systems, especially for network applications. To support parallel comparison function, however, a TCAM has complex function. The complex function causes that the TCAM becomes an area-consuming and power-consumption component. Therefore, low-area and low-power are two major challenges in designing a cost-efficient TCAM. Also, yield improvement techniques are very important for the TCAM since the area of TCAM is usually very large. In this thesis, we propose a low-power TCAM with hybrid tree-NAND/NOR match line. The hybrid tree-NAND/NOR structure can increase the number of bits of NAND-type cells in a TCAM word such that the compare power of the word and the compare delay caused by the NAND-type cells can be minimized. Therefore, the energy of compare operation of the proposed TCAM with hybrid NAND/NOR match lines is very low. We have implemented a 32x64-bit TCAM with hybrid NAND/NOR match lines. Measurement results of the TCAM test chip show that the power consumption of the TCAM is only about 0.4122mW at 110MHz. Also, the energy consumption is very low, which is only about 1.90fJ/bit/search. In comparison with the existing TCAMs for general applications, the proposed TCAM achieve better energy consumption. We also propose a built-in self-repair (BISR) scheme for the TCAM. In the BISR scheme, a programmable built-in self-test circuit is proposed to test the functional faults of the TCAM and a novel reconfiguration mechanism is proposed to swap defective elements. Differing from the widely-used shift redundancy scheme, the proposed redundancy reconfiguration scheme incurs constant delay penalty regardless of the number of implemented redundancies. Experimental results show that the delay and the area cost of the BISR circuit are only about 0.85ns and 21920um^2, respectively.
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Zhao, Wei-Chang, and 趙威丞. "A High Speed, Energy Efficient and High Density 14T Ternary Content Addressable Memory." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/s685m5.
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Liu, Siao-Siang, and 劉曉祥. "Design of Matchline Sense Amplifiers for FinFET-Based Ternary Content-Addressable Memory（TCAM）." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/99784352426715471019.
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碩士國立彰化師範大學
電子工程學系
104
Content-addressable memory (CAM) compares input search data in parallel against a table of stored data, and returns the address of the matching data. CAMs can be used in a wide variety of applications requiring high-speed parallel search. These applications include pattern recognition, data compression, and network address translation. The parallel search operation of CAM consumes a significant amount of energy due to the charging and discharging of the search lines and match lines with large capacitance. As the feature size continues to shrink and the corresponding transistor density increases, the planar MOSFET suffer from the increased subthershold and gate leakage currents. FinFET is considered as one of the best substitutes for planar MOSFET technology in the sub-20 nm regime. This thesis proposed two new sensing techniques for low power Ternary Content-Addressable Memory (TCAM). Matchline-Accelerating Sense Amplifiers (MLA-SA) using pulse current to reduce the power consumption of Matchlien in TCAM and employs the feedback network to boost the search speed of TCAM. We proposed a second Matchline sensing technique call “Matchline-Accelerating Low-Power sense amplifiers (MLA-LP-SA) “. MLA-LP-SA using the pulse current to charge the Matchlines and then detects the voltage development on Matchlines to determine whether the Matchline is matched. In contrast to conventional MLSAs, which adjust the charging current to the match lines based on matching result, MLA-LP-SA will not provide additional current to the match lines regardless of the matching result. We have employed Hspice to evaluate various Matchline sensing circuits using the Berkeley Short-channel IGFET Model (BSIM) common multi-gate (CMG) FinFETs with supply voltage of 0.6V and temperature of 25℃. The simulation results show that the proposed MLA-SA can reduce the energy consumption by 39%-65% and 25%-44% compared to the conventional Precharge MLSA and Current-Race MLSA. The proposed MLA-LP-SA can reduce the energy consumption by 66%-73% and 54%-63%, compared to the conventional Precharge MLSA and Current-Race MLSA. MLA-SA and MLA-LP-SA, respectively, can achieve a search time of 150.2 ps and 89.6 ps, and Energy-delay product of 0.775×10-27JS and 0.372×10-27JS, for conventional Precharge MLSA and Current-Race MLSA decreased by 64.38%, 51.65% and 82.9%, 76.79%. Keywords: Content-addressable memory, FinFET devices, Matchline Sense Amplifiers
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Tawakol, Abdel Maguid. "Performance Analysis of TCAMs in Switches." Thesis, 2012. http://hdl.handle.net/10012/6654.
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The Catalyst 6500 is a modern commercial switch, capable of processing millions of packets per second through the utilization of specialized hardware. One of the main hardware components aiding the switch in performing its task is the Ternary Content Addressable Memory (TCAM). TCAMs update themselves with data relevant to routing and switching based on the traffic flowing through the switch. This enables the switch to forward future packets destined to a location that has already been previously discovered - at a very high speed.
The problem is TCAMs have a limited size, and once they reach their capacity, the switch has to rely on software to perform the switching and routing - a much slower process than performing Hardware Switching that utilizes the TCAM. A framework has been developed to analyze the switch’s performance once the TCAM has reached its capacity, as well as measure the penalty associated with a cache miss. This thesis concludes with some recommendations and future work.
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Feng-Sheng, Tsai. "The Content-Addressable Memory Problem." 2002. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0021-2603200719125215.
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Tsai, Feng-Sheng, and 蔡豐聲. "The Content-Addressable Memory Problem." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/86343578736626370368.
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碩士國立臺灣師範大學
數學研究所
91
Abstract. We propose a solution to a fundamental problem in neural nets : " Stored an arbitrary set of fundamental memories, does there exist a recursive network for which these fundamental memories are stable equilibrium states of the network ? " The heart of it is the conception of the emergent set, a Hamming star-convexity packing in the n-cube, the mathematical framework of Hebb's strengthened learning rule, and the CAM algorithm. We prove that the set of stable equilibrium states of the threshold network constructed by Hebb's strengthened learning rule that responds to incoming signals of the states of fundamental memories is the 01-span of the emergence of fundamental memories. On this basis, we reduce the question to a problem for constructing a threshold network with sparse connections that responds to incoming signals of the states of a generator of fundamental memories, and thereby probing the collective dynamics of the network. One of the great intellectual challenges is to nd the mechanism for storage of memory. The solution of the Content-Addressable Memory Problem indicates a mechanism for storage of memory that a network produced in the brains by sucking the kernel of the received stored memory items as incoming signals can correctly yield the entire memory items on the basis of sucient partial information by the chaotic dynamics with a regular strategy-set.
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Wen, Yu-Ching, and 溫又卿. "Multi-Purposed Precomputation-Based Content Addressable Memory." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/45360317764500502347.
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碩士國立彰化師範大學
電子工程學系
99
Content addressable memory has the advantage of high-speed data searching, so it is widely used in communication network and cache system. However, owing to mass and parallel comparison, the area overhead, power dissipation and reliability are still the major issues for content addressable memory device. Precomputation is usually applied in content addressable memory for predictive speedup and power disabling. In this paper, three efficient subspace codes are surveyed for precomputation based content addressable memory. The side benefits are also analyzed in the experiments. Form our evaluations the most significant bits concept does not need the extra-content addressable memory area overhead. Berger codes can be applied to hold the equal-weight property for cell reduction or searching-once. The proposed precomputation using Hamming codes can takes more benefits on low-power, small checkers and error correction. The novel Hamming codes is presented for improve the power consumption of 30%. In this paper we also propose an equal-weigh codes multi-level cell flash content addressable memory with low-cost and high-speed features. Firstly applying the EWC theory the searching times can be reduced to once for MLC FCAM. Secondly we use the Berger codes to reduce the floating gate transistor count of the data memory circuitry. In the experimental result, the flash-based CAM based on equal-weigh codes design was implemented with the TSMC 0.18μm CMOS technology under 3.3V supply voltage. The Search-to-Match delay time of flash cell is about 0.37ns.
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Lin, Chou-Kun, and 林周坤. "Low-Power Design and Test Techniques for Ternary Content Addressable Memories." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/55602370121087132680.
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碩士國立中央大學
電機工程研究所
92
Power dissipation and area cost are two major design concerns of the ternary content addressable memory (TCAM). This thesis presents a 10T static cell and a low-power design methodology for TCAMs. The proposed 10T cell makes a static TCAM be able to be implemented with very low area cost. Compared with a typical 9T static binary cell, only one additional transistor is needed to realize a static ternary cell. Experimental results show that the proposed 10T cell only need about 13.83um2. A low-power design technique is also proposed to reduce the Search power by dividing the match line of a word into multiple cascaded small match lines. Simulation results show that for a 32 x 64 TCAM, about 10%~70% Search power reduction can be achieved if the ratio of empty segments is higher than 37.5% and the segment width is 8. On the other hand, testing TCAMs is very complicated due to their special structure. In this thesis we develop functional fault models based on physical defects, such as short defects, open defects, transistor stuck-on defects, and transistor stuck-off defects. We also propose a March-like test algorithm for TCAMs based on the proposed functional faults. The test algorithm only requires basic TCAM operations, Write, Search, and Erase, and the test response can be observed entirely from the single-bit Hit output. The test algorithm requires 4N+2W Search operations, 4N Write operations, and 4N Erase operations to cover 100% target comparison faults for an N x W-bit TCAM.
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Manikandan, Palanichamy, and 麥肯德. "Design of Low Power Fully Parallel Binary and Ternary Content Addressable Memories." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/31077159041841274519.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
95
This thesis presents a novel VLSI architecture for fully parallel static type binary and ternary content addressable memories (BCAM and TCAM) with low power and high flexibility features by using novel CAM cell structures. The proposed CAM core cell structures eliminate the drawbacks and adapt the advantages of single bit line and dual bit line cell structures. In this work, the word match line (ML) structure of low power BCAM and TCAM adapts the proposed NAND based static pseudo CMOS (NPC) logic and static pseudo CMOS (PC) logic respectively which comprises the advantages of NAND structure such as low static power, pseudo NMOS logic such as high speed operation and CMOS logic such as low power and low cost. HSPICE simulations for 128×32 BCAM systems were performed with 0.18 �慆 technology and the result shows that the proposed design provides the power dissipation of 3.94 mW with the delay time of 2.02 ns under 1.8 V supply voltage. The measurement results of 128×32 PC-BCAM (under 0.18 �慆 CMOS technology) shows that the proposed BCAM cell reduces 76% of power dissipation and improves 65% of search speed. Further more, spice simulations were carried out for 64×128 TCAM systems with advanced local search line control (LSC) technique under 0.13 �慆 technology which shows that the proposed design gives the power dissipation of 2.04mw with the delay time of 6.06 ns under 1.2 V supply voltage. In 64×128 TCAM, proposed TCAM cell reduces 26% of power dissipation and improves about 23% of search speed.
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Chen, Yao-Lun, and 陳要綸. "Design of CNTFET Content-Addressable Memories Using Ternary Inverters and Precharge Controllers." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/99yh9m.
Full textAbstract:
碩士國立彰化師範大學
電子工程學系
107
Content-Addressable Memory (CAM) is a special kind of memory that allows parallel search of data, and it is widely used for pattern recognition, data compression, and network address translation. In recent years, because the characteristic size of the transistor continues to shrink and the corresponding transistor density increases, the conventional planer MOSFET may have problems such as increasing subthreshold and gate leakage currents. This thesis uses a carbon nanotube transistor (CNTFET) to replace the traditional MOSFET, to effectively overcome the shortcomings of the traditional planar MOSFETs. The threshold voltage of a CNTFET can be controlled by its diameter, which is determined by the chirality vector of the carbon nanotubes in the CNTFET. Thus, CNTFETs can easily support multi-threshold design. This thesis is based on Ternary-Inverter-Based TCAM (TIB TCAM), which was previously proposed by our research group. First, we used three kinds of ternary inverters, including Shreya-Inv, Lomb1-Inv and Our-Inv, to form three kinds of TIB TCAMs, called Shreya-TIB-TCAM, Lomb1-TIB-TCAM and Our-TIB-TCAM, respectively. Then, we combined Precharge Controller (PC), which was proposed by Konga Suresh et al., with the three TIB TCAMs to form three TIB TCAMs with PC, called Shreya-TIB-TCAM w. PC, Lomb1-TIB-TCAM w. PC and Our-TIB-TCAM w. PC, respectively. To evaluate the performance of Shreya-TIB-TCAM w. PC, Lomb1-TIB-TCAM w. PC and Our-TIB-TCAM w. PC, we used HSPICE to do the simulations, comparing the power consumption for Shreya-TIB-TCAM, Lomb1-TIB-TCAM and Our-TIB-TCAM with/without PC. The simulation results show that the proposed Shreya-TIB-TCAM w. PC, Lomb1-TIB-TCAM w. PC and Our-TIB-TCAM w. PC can reduce 36.0%, 39.6% and 37.2% of power consumption and reduce 18.6%, 20.7% and 5.3% of search time.
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Kuo, Yen-Ting, and 郭彥廷. "Design of a Two-phase Adiabatic Content-addressable Memory." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/02060065956225861352.
Full textAbstract:
碩士國立彰化師範大學
電子工程學系
100
A content-addressable memory (CAM) compares in parallel input search data to all contents of the memory and then returns the address of the matching data. This thesis presents the design of a two-phase adiabatic CAM, which achieves low-power dissipation employing adiabatic operation and the selective charging/discharging of match-lines. Adiabatic logic is considered as an effective method for low-power circuit design. When an adiabatic logic charges/discharges its output nodes, the switch elements on the charging/discharging path consume almost zero power by keeping the voltage drop between the power supply and the output nodes close to zero. In our CAM architecture, the match-line in each CAM word is partitioned into two segments, and the second segment is selectively charged/discharged according to the match result of the first segment. If the match result of the first word segment is mismatch, the further charging/discharging of the second segment of the match-line will be eliminated, thus reducing power dissipation. Simulation results showed that the proposed two-phase adiabatic CAM using Efficient Charge Recovery Logic (ECRL) with a size of 256 words × 144 bits can achieve 31.39% power reduction, compared with the single-phase adiabatic CAM using Complementary Pass-transistor Adiabatic Logic (CPAL), at frequency 100M Hz and 22.06% power reduction at frequency 500M Hz.
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Tsai, Yu-Chu. "Design and Analysis of Low Power Content Addressable Memory." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2406200811120200.
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Chang, Chen-Hui. "Low power Content-Addressable Memory using Feedback matchline structure." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2207200816441800.
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Chen, Tai-An, and 陳泰安. "Design of Content Addressable Memory for Sub-threshold Operation." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/33632734472824476627.
Full textAbstract:
碩士國立中正大學
電機工程所
96
In this thesis we propose circuit design of NAND type and NOR type content addressable memories(CAM) for sub-threshold operation. The NAND type ternary CAM has an equivalent bitcell size of 22-T and the NOR has 24-T. These two CAM cells are the first design for ultra-low-voltage operation. The proposed CAM cells using a 90-nm CMOS process can operate in 0.3-V. At this low voltage, the CAM offer substantial power saving and base on standard CMOS technology. The proposed CAM cells have distinct read, write, and search sub-circuits. We can size each sub-circuit independently for optimizing system efficiency without affecting functions. The write sub-circuit uses 6-T SRAM and it can be designed to write more easily without considering read. The read sub-circuit remove the problem of read SNM by buffering the stored data to read bit-line during a read access. The read sub-circuit also reduces read bit-line leakage through unaccessed CAM cells by the stack effect. The search sub-circuit use transmission-gates to pass the match signal without Vth-drop. The search sub-circuit in NOR type CAM cell reduces match-line leakage with rising NMOS Vth by the stack effect. It makes the NOR type match-line fitting in low voltage. The NAND type CAM cell can be used in the AND-type match-line to achieve high-speed and low-power. These two sub-Vt CAM cells both have writing-easily, large-SNM, and low-leakage. In addition we implement the CAM cells to decrease the effects of process variation. We verify the two CAM cells with a 256×32-b AND-NOR mixed TCAM using 90-nm CMOS technology. Post-simulation shows that the proposed TCAM achieves a 21.15-ns search time with the 0.28-fJ/bit/search of energy in 0.3-V and passes all process corners.
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Chang, Chen-Hui, and 張振輝. "Low power Content-Addressable Memory using Feedback matchline structure." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/01598840417002889579.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
96
With the evolution of VLSI and computer system, the requirement of low power consumption is enhanced too. The low power design can not only reduce the heat scatter, but also can increase the product life time. The power saving method usually used the low supply voltage to reduce power consumption, but reduce power supply voltage would have some problem, like noise immunity decreased, etc. Content addressable memory is widely used in database, routers, etc. in the applications that require high search speed, because the content addressable memory does parallel comparison so it has high speed characteristic, but result in quite high power consumption. In this thesis, we propose a new method using the feedback from matchline signal to turn off the discharge path and reduce power consumption. We further implement and simulate the whole architecture by Synopsys Hspice using 0.18μm technology. Simulation results of the 32-bit show our method has a reduction of power consumption up to 44% with a 16% longer latency in comparison of the conventional structure. When simulated in the 64-bit, the reduction of the power consumption is up to 46% with an 18% longer latency. In 128-bit, the power consumption of our method is 47% less with a 15% longer latency in comparison of the conventional structure.
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Tsai, Yu-Chu, and 蔡育筑. "Design and Analysis of Low Power Content Addressable Memory." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/28806351695469393094.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
96
Content addressable memories (CAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of CAMs, high power consumption is one of the most critical challenges faced by CAM designers, This work proposes circuit techniques for reducing CAM power consumption. The main contribution of this work is reduction in match line (ML) sensing energy, and static-power reduction techniques. The ML sensing energy is reduced by employing positive-feedback ML sense amplifiers (MLSAs). We simulate the circuit with TSMC 0.18 μm process at 1.8 V. The simulation results of the postive-feedback MLSA show 86.3% reduction in ML power-delay product. Finally, design and analysis of a complete CAM circuit are presented, and compared with other published designs.
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HAN, DE-WEI, and 韓德威. "The design and applications of a novel content-addressable memory." Thesis, 1991. http://ndltd.ncl.edu.tw/handle/79900940268614640826.
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Lin, Chi-Wei, and 林志威. "Banked-Associative Hybrid Architecture for Precomputation-Based Content-Addressable Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/25238431850325448762.
Full textAbstract:
碩士臺灣大學
資訊工程學研究所
98
Content addressable-memory (CAM) can be used in wide application and implements the lookup- table function within a single clock cycle. CAM compares input searched data with its stored data parallel that provide high-speed data searched operation. If data search is successful, which indicates that a stored data matches the search word, then CAM outputs the address of the matching word. This thesis presents a novel architecture for precomputation-base content addressable memory (PB-CAM) that includes low power, and low cost characters. The new architecture combines the architectural design technique of associative scheme as well as the banked approach. The experimental results showed that the proposed architecture average reduced by 47% power than the ones count PB-CAM architecture and average reduced by 25 % in chip area reduction while a minimal increase of latency that is caused by the additional circuit design.
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Hsu, Wei-Ning, and 許韋寧. "Dependable and Area-Efficient Equal-Weight Coded Content-Addressable Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/83322171330714414018.
Full textAbstract:
碩士國立彰化師範大學
電子工程學系
99
Content addressable memory, a high-performance lookup engine in many systems, is widely used in communication network and cache system. However, owing to the mass and parallel comparison, the area overhead, power dissipation and reliability are still the major issues for a content addressable memory device. In this thesis the Berger code, a well-known error-detection code, is applied in the binary-valued content-addressable memory design to reduce the redundant area of the logic transistor stacks. A three-transistor DRAM based binary-valued content-addressable memory cell is then innovated. Furthermore an improved coding technique called Berger Invert code is developed to promote the dependability especially when the DRAM is approximated to a fully-asymmetric system. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detection mechanism for reliability. Eventually this paper presents a DRAM-based CAM based on Berger invert code with dependable and area efficient. Especially for memory with seriously asymmetrically retention error probability, the novel Berger invert code is presented for improve the dependability for about 21% and information energy for 25%. In addition, the SRAM-based CAM based on Berger invert code design was implemented with the TSMC 0.18 CMOS technology under 1.8 V supply voltage. The Search-to-Match delay time of a 64 words by 14 bits BIC-CAM is about 1.62ns.
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Wu, Tung-Chi, and 吳桐其. "Low Power Match Line Design Used in Content Addressable Memory." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/3sp3x8.
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博士國立中興大學
資訊科學與工程學系
106
Content-Addressable Memory （CAM） and Ternary Content-Addressable memory （TCAM） are often used in fast lookup applications. Because using parallel comparisons for fast searching, rsulting in high power consumption. In this paper we propose two ML designs to reduce the ML power consumption of the CAM and TCAM. For the CAM, we propose a new ML architecture, called MSML （Master-Slave Match Line） design, by combining the master-slave ML architecture and charge refill minimization technique to reduce the MLs power dissipated of the CAM. The MSML’s ML is composed of one master ML （MML）, several slaves ML （SMLs） and one final ML （FML） to perform the search operation. By sharing the MML charge to the SML when mismatched search, our design can minimize the MML charge refill swing, such that the ML power consumption can be reduced effectively. The ML power saving is at least 50%, From the HSPICE simulation, the MSML desing can reduce the ML energy consumption by 7% to 57%. In addition, we further modify the CAM cell structure to improve the search performance of the CAM and called MSMLhp design. In the 128-bit configuration, the MSMLhp improves energy-delay product （EDP） by 28% over MSML design, and improves EDP by 69% compares with the traditional CAM designs. In addition, we propose the MAML （mask-aware match-line） technology for the TCAM ML design. Use the prefix don''t care continuity feature, MAML design divides the ML to several segments and adds a gate node（GN） between each ML. Avoiding the no need precharge of MLs to reduce power consumption. Due to the segmentation design, the voltage on the ML will be limited between 0~Vdd-Vtn. Compare with other related research, MAML design can reduce the power consumption effectively on the ML, and without adding many complicated control circuits. MAML uses TSMC''s 0.18um process with a capacity of 256*128-bit. The HSPICE simulation results show that the refined MAML design which reduced the ML energy consumption about 22% to 58% compared to the traditional design like NOR-Type TCAM.
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Lee, Long-En, and 李龍恩. "A Special Purpose Content Addressable Memory for Network Packet Classifier." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/xad5w7.
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碩士中原大學
電子工程研究所
91
The internet is formed by reticulated connections that are mutually connected and these network points are composed by a router. In virtue of the Internet information data is increasing rapidly makes the existent bandwidth not useful enough. Therefore brings the concept of different service. Different service needs that routers in each network point look up the internet protocol in the packet header and give a suitable action at the right time. Then the data can be sent to the destination without any problem according the administrator. When the data is being classified needs to look up the information in the header and find out if they can fit in with the rules defined previously. Once the quantity of rules increases, the look up time increases proportionally. The special hardware architecture design of a Content addressable memory can finish the look up in a specific time which makes it suitable to look up in a high speed packet classification. But the use of it is limited because the Content addressable memory needs more cost and power consumption. The data search is compared by bit, therefore could produce a (2W-2) expand factor as the worst situation. One rule probably needs a number of Content addressable memory entries which makes it no efficient. This paper proposed a special purpose content addressable memory to avoid the multiplicative factor where one rule only needs an entry. The coming of IPV6 can use the special purpose content addressable memory to compose the frame that the packet classification needs for data search. Finally we use the TSMC 0.35um and the fully-custom methodology to implement the special purpose content addressable memory. Then we use transistor level simulation tool called “TimeMill” to verificate the functions and the timing.
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Er, Yee-Sin, and 余宇昕. "A Cache Memory Using SOI DTMOS Technique and a Content-Addressable-Memory Cell Approach." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/24685181077921662368.
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Cheng, Shih-Sheng, and 鄭時昇. "Low-Power Dependable Content Addressable Memory Based on Hamming Code Precomputation." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/85665580477783730368.
Full textAbstract:
碩士國立彰化師範大學
電子工程學系
101
Abstract Content addressable memory has the advantage of high-speed data searching, so it is widely used in communication network and cache system. However, owing to mass and parallel comparison, the area overhead, power dissipation and reliability are still the major issues for content addressable memory device. Precomputation is usually applied for predictive speedup and power disabling. In this paper low-power precomputation is surveyed in view of subspace codes. Four efficient subspace codes are proposed for precomputation based content address memory design. The side benefits are also surveyed and analyzed in the experiments. From our evaluations the MSB concept can be combined with m/n codes or sentry tagging with few overhead. Berger and m/n codes can be applied to hold the equal-weight property for cell reduction or searching-once. The proposed precomputation using Hamming codes can take more benefits on small checkers and error correction. The proposed precomputation using Hamming codes can take more benefits on low-power, small checkers and error correction. The novel Hamming codes are presented for improve the power consumption of 30%. Keywords: Precomputation, Subspace code, Content addressable memory,Hamming code
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Pao, Chien-Yuan, and 包建元. "Low-Power Fully-Parallel Content Addressable Memory - Analysis, Design, and Application." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/05060476658569781202.
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碩士國立中正大學
電機工程研究所
87
A partial-current-mode fully-parallel CAM is proposed in this thesis. The proposed fully-parallel CAM performs current-mode operation when either for both read data and write data, but when match data is still performed by voltage-mode. This thesis also describes several different CAM structures using different CAM cells in published paper and re-implement these CAM structures to analyze their operation and power dissipation. A 512x15-bits CAM was designed and implemented in a 0.6-mm CMOS technology, and then this design is automatically converted to a design using a 0.35-mm CMOS technology by a technology migration technique developed by the VLSI GROUP of EE/CCU. The design of the 0.35-mm version has also been submitted for fabrication. This CAM design is really used in a CCMAC control chip We have implemented a CCMAC ASIC to verify the hardware feasibility of this new architecture and also to verify the performance of the new content addressable memory. This ASIC will also be installed in a backer-upper control system.
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Chang, Jui-Chuan, and 張瑞娟. "Design of Low-Power Precomputation-Based Fully Parallel Content addressable Memory." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/86g37f.
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碩士國立成功大學
電機工程學系碩博士班
90
This paper presents a novel VLSI architecture for a fully parallel precomputation-based content addressable memory (PB-CAM) with low-power, low-cost, high-speed, and high-reliability features. This design is based on a precomputation skill that not only saves power consumption of the PB-CAM system, but also reduces transistor count and operating voltage of the PB-CAM cell. The proposed PB-CAM architecture adopts the static pseudo nMOS circuit design to replace the dynamic CMOS circuit design. The static pseudo nMOS circuit avoids some system reliable problems such as process violation and charge sharing. Based on the proposed PB-CAM architecture, a new 7-transistor memory cell circuit is proposed. In the new 7-transistor circuit, since bit comparison circuit adopts NAND type design in instead of XOR type design, the power consumption and hardware cost are largely reduced. In order to accelerate the bit comparison speed, alternative 10-transistor memory cell circuit which achieves high bit comparison speed is proposed. The hardware cost, however, is increased correspondingly. The whole design was fabricated with the TSMC 0.35 μm SPQM CMOS process parameters under 3.3 V supply voltage. With a 128 keys by 30 bits CAM size, the measurement results indicate that the proposed circuit works up to 72 MHz (include I/O pad delay) with the power consumption less than 33 mW. Furthermore, by the low voltage measurement results, the proposed circuit works up to 4 MHz (include I/O pad delay), and under 1.6 V supply voltage.
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Chang, Shu-Wei, and 張書瑋. "Energy-Efficient Content-Addressable Memory Design For IPv6 Addressing Lookup Application." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/74020164688413929649.
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碩士國立交通大學
電子工程系所
94
The new high speed, low-power and noise-tolerant ternary content-addressable memories (TCAMs) using butterfly match-line scheme and don’t care based low power technique are realized in this thesis. Butterfly match-line scheme reduces search delay by high parallel search. Furthermore, for IPv6 addressing lookup application, butterfly match-line scheme reduces switching activity also. By use of XOR-based conditional keepers, power consumption and search delay further reduced. The potential charge-sharing problem in the AND match-line could be solved also. Don’t-care based low power technique takes the advantage of application future of TCAM. Don’t-care based power-gating eliminate unnecessary precharege. Don’t-care based hierarchical search-line scheme decrease switching capacitance. A 256-word x 128-bit energy-efficient ternary CAM is also proposed and simulations and layout are implemented in TSMC 0.13μm CMOS technology. Simulation results show that 0.29fJ/bit/search energy performance and 0.65ns search time operate in maximum frequency 500Hhz.
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Yang, Ren-Yang, and 楊人仰. "High speed lempel ziv data compressor design using content addressable memory." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/04436840231874552758.
Full textAbstract:
碩士國立交通大學
電子研究所
82
In this thesis, a novel VLSI architecture is proposed for high- speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units, namely content addressable memory, match logic, and output stage. The content addressable memory generates a set of hit signals which identify those positions whose symbols in a specified buffer are the same as input symbol. These hits signals are then passed to the match logic which determines one matched string and its match length and location in the buffer to form the kernel of compressed data. These two items are then passed to the output stage for packetization before sent out. By trading off hardware complexity and compression ratio, 2KB buffer size and adjustable maximum match length are considered in our proto-type VLSI chip. Simulation results show that, based on a 0.8μm CMOS process technology, clock speed up to 50MHz can be achieved. This implies that the developing data compressor chip can handle many real-life applications such as in video coding and high-speed data storage systems.
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Tung, I.-Jui, and 童顗叡. "A SystemC Content Addressable Memory Power Estimation Tool for Early Design Verification." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/77984009767099566134.
Full textAbstract:
碩士臺灣大學
資訊工程學研究所
98
Content Addressable memory (CAM) is a storage device which is widely implemented in the IP look-up table of a network router due to its high speed searching performance. In IPv6, the IP address will be 128 bits, as a result, the storage size of CAM will be larger in the future. The simulation time is an important factor affecting time-to-market. Using transistor level simulation such as SPICE in the early design stage of CAM will take huge time and delay time-to-market. SystemC is a system level modelling language and simulation platform, it provides better simulation efficiency and ability of hardware software co-design. However SystemC does not provide the function to estimate power consumption for low power algorithm or structure design. In this thesis, we developed a SystemC CAM power estimation tool (SystemC CAM PET) to estimate match-line power of CAM in the early design stage. We construct a new CAM match-line power model to estimate match-line power consumption. We simulated 10 benchmarks of Mibench and compared our SystemC CAM PET simulation results with SPICE simulation results. The simulation time is shorter in average 1654 and error rate of match-line power, search-line and storage cell estimation is average 14.79%, 11.681%, 3.66%. In addition, our SystemC CAM PET is able to calculate the miss rate, data comparison times, input and search data activity of each benchmark for PB-CAM structure. We also proposed a low power improvement example for PB-CAM structure using Gate-Block selection algorithm and verify it by our SystemC CAM PET. The number of data comparisons, miss rate and match-line power consumption are reduced by 49%, 51%, 51% in average.
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Yang, Tse-Chun Ou. "NOR-type logic Content-Addressable Memory circuit of two segment matchline schem." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2107200800380800.
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Lin, Ya-Chun, and 林雅純. "Master-Slave Match-Line Circuit Design for Low-Power Content Addressable Memory." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/5u43q4.
Full textAbstract:
碩士國立中興大學
資訊科學與工程學系所
101
Content addressable memory (CAM) is a fast lookup hardware table. However, its parallel comparison feature and frequent lookup cause significant power consumption. In this paper we propose a low power match-line architecture, called master slave (MS) match-line design, in which we combine the charge sharing and segmentation technique to largely reduce the CAM power dissipated in the ML switching activity. Unlike the conventional CAM design, where only a single ML is used, our design uses two MLs to perform the search operation. By reducing the ML swing, our design can minimize the charge loss in the search operation. Based on TSMC 90nm technology, the simulation results show that our design can reduce the search energy consumption of the CAM by 84% at most compared to the conventional NOR-type CAM design.
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Chang, Wei-Keng, and 張維耿. "Low Power Pre-comparison Content Addressable Memory and Translation Lookaside Buffer Design." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/g5h3gt.
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Tsai, Shih-Ju, and 蔡仕儒. "Two Novel Designs of Match-Line Sense Amplifiers for Content-Addressable Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/44372904742591242240.
Full textAbstract:
碩士國立彰化師範大學
電子工程學系
98
Content-addressable memory（CAM）is a memory structure that supports parallel data search. The applications of CAM include the IP address search in a network router, cache memory, data compression, and image processing. The parallel search operation of CAM consumes a significant amount of energy due to the charging and discharging of the search lines and match lines with large capacitance. This thesis proposed two new CAM match-line sensing circuits, the double positive-feedback match-line sense amplifier (DPF-MLSA) and the pulse current based match-line sense amplifier (PCB-MLSA). DPF-MLSA uses the pulse current to reduce the power consumption of match lines in a ternary content-addressable memory (TCAM) and employs the double positive-feedback network to boost the search speed of TCAM. PCB-MLSA uses the pulse current to charge the match lines and then detects the voltage development on match lines to determine whether the match line is matched. In contrast to conventional MLSAs, which adjust the charging current to the match lines based on matching result, PCB-MLSA will not provide additional current to the match lines regardless of the matching result. We have employed Hspice to evaluate various match-line sensing circuits using the Berkeley Predictive Technology Model (BPTM) for 65nm transistor model with supply voltage of 1.1V and temperature of 25 . The simulation results show that the proposed DPFMLSA and PCBMLSA, respectively, can achieve a search time of 0.49699 ns and 0.41797 ns and a energy consumption of 0.201474 and 0.194466 fJ/bit/search. The measured results show that the proposed DPFMLSA can reduce the energy consumption by 85.481%, 21.195%, and 10.545% compared to the conventional precharge MLSA, the match sensing technique using match-line stability, and the positive-feedback MLSA, respectively. The proposed PCBMLSA can reduce the energy consumption by 85.987%, 23.936%, and 13.657% compared to the conventional precharge MLSA, the match sensing technique using match-line stability, and the positive-feedback MLSA, respectively.
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Yang, Tse-Chun Ou, and 歐陽策群. "NOR-type logic Content-Addressable Memory circuit of two segment matchline schem." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/49854084304074182006.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
96
The design of the Low power VLSI circuit is one of the most important issues at the present time technology. In the chip, with ever increasing complexity of VLSI design and transistors, the power saving becomes the noteworthy challenge. In order to solve the problem of the power consumption, the Network-on-Chip is proposed to deal with the difficulties of inter-communication between IP cores. In the NoC, the main components are Switch (or so-called Router) and Network Interface (NI, or so-called Wrapper), and CAM (Content-Addressable Memory) is an indispensable part in the router. In this thesis, we propose a NOR-type logic Content-Addressable Memory circuit of two segment matchline scheme to Reduce power consumption, in this thesis, the proposed matching scheme can be saved about 70% on average power consumption.
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Wei, Chia-Hung, and 魏嘉宏. "Static Divided Word Matching Line for Low-Power Content-Addressable Memory Design." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/23929657275601076957.
Full textAbstract:
碩士淡江大學
電機工程學系
92
Recently, data searching and comparison operations have played a very important role in computer science and its applications. To accelerate the searching speed required by these applications, content-addressable memory (CAM) is used in applications where searching time is very critical. The CAM, especially the fully parallel CAM, provides highly efficient hardware architecture for high-speed data searching topic. Thereby the CAM function is used in a wide range of applications requiring pattern-matching operations on bits, such as virtual memory, lookup table, databases, data compression and image processing. Recently, in high-speed network computing applications, for example gigabit Ethernet, asynchronous transfer mode (ATM) switches and high-speed lookup tables, higher speeds and lower power CAMs are needed to satisfy requirements of these leading-edge applications. One of the major problems of a CAM design compared to a random access memory (RAM) design is its complexity. There are extra transistors and extra wiring in each cell, which are needed for the searching and comparison capabilities. Another problem is the amount of the power consumption needed for data searching and comparison operation. This is because all the CAM cells are accessed on every searching and comparison access due to the simultaneous comparison, where as in RAM only the portion used cell is accessed during the read/write operations that leads to the CAM consumes huge amounts of power. Consequently, the goal of this thesis is to reduce the evaluated power consumption of the CAM. A variety of CAM structures have been proposed over the years to improve the overall system performance and reduce power consumption. However, based on the standard CMOS technology, similar CAM word circuits and CAM cells have become the industry standard of these techniques. The CAM word circuits are used the dynamic circuit design, and based on the nine-transistor CAM cell circuit. In conventional CAMs, the dynamic circuit design is faced with the high-power, low-reliability and circuit complexity problems. In addition, the comparison circuit with XOR gate function of conventional CAM cells is constructed using the pass transistor logic (PTL) type circuit. Thus the output voltage of the comparison circuit cannot effectively achieve the full logic level, and the operating voltage is limited in this factor, so it is not suitable for low supply voltage design and portable applications. In view of the problems in CAMs, this thesis proposes a new static CAM with divided word match line structure that achieves the low-power feature. The proposed divided word match line technique separates the comparison operation into two comparison stages. By using the proposed two comparison stages approach, most parts of comparison power consumption can be reduced effectively. Furthermore, in the portable system, its lower supply voltage is one of the key design factors. To reduce the supply voltage for low-power applications, this thesis presents a new CAM cell circuit design, whose comparison circuit is constructed of CMOS function circuits instead of the pass transistor logic function circuits to achieve the full output voltage swing. Moreover, the proposed static CAM circuit does not require the clock signal. Without the high driving capability buffer used to drive the heavy clock loading line in the overall system, the static CAM can avoid some circuit reliability problems such as clock skew and clock distribution. The high power dissipation in high driving capability buffer can also reduced effectively. The proposed CAM configuration is 128-word by 32-bit, and is designed and fabricated based on TSMC 0.25 um CMOS technology with one polysilicon and five metal layers. The measurement results show that the experiment chip has 100 MHz operation frequency with I/O capacitive loading at 1.9 V supply voltage, and the power consumption is 7.1 mW. Furthermore, the operation frequency of the proposed CAM chip can achieve 25 MHz under the 1.3 V supply voltage. Moreover, for the embedded system applications, the operation frequency of the proposed CAM chip can achieve 200 MHz at 2.5 V supply voltage.
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Shen, Ruei-Chi, and 沈睿騏. "An Estimation Approach for the Low Power Precomputation-Based Content-Addressable Memory Design." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/17285638535652726963.
Full textAbstract:
碩士國立臺灣大學
電機工程學研究所
100
Content addressable memory (CAM) is often used in many applications which require searching in high speed such as network router, translation look-aside buffer (TLB), Huffman decoding, discrete cosine transform or the applications having quick lookup table operation. Due to its operational characteristic of parallel data searching, the power consumption is also exacerbated. In this thesis, a methodology was proposed for synthesizing a low power pre-computation-based content addressable memory (PB-CAM) effectively. The concept of discrete uniform distribution is adopted in pre-computation block so as to verify the outcomes of power reduction when the adaptive parameter extractors are synthesized in a different manner. With our proposed approach, we are able to estimate the tendency towards power consumption efficiently and determine which type of parameter extractor is superior in power reduction for the specific data. Experiments show that the power consumption of our approach is better by at least 29% compared with original parameter extractors.
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Lin, Yung-Shiang, and 林雍翔. "Design of a Low-power Content Addressable Memory with Current Self-adjusted Mechanism." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/86403611232242154557.
Full textAbstract:
碩士國立彰化師範大學
電子工程學系
97
Abstract In a traditional NOR-type content-addressable memory (CAM), the power consumption of match lines accounts for one major component of the total power consumption. This paper proposes a novel CAM architecture with a new current-saving match-line sensing mechanism. In the proposed architecture, each data row of the CAM has its own virtual match line (VML) and virtual ground line (VGL), and the comparison cells for one data row behave as switches between the corresponding VML and VGL. If the data in the current row is matched with the search key, all switches between VML and VGL are turned off, and VML are charged by a current source to a higher voltage than VGL to indicate the case of data match. If the data in the current row is different from the search key, at least one switch between VML and VGL is turned on, and the charging current for VML will be reduced by a self-adjusted mechanism to avoid excessive power consumption. Also, a dummy data row is placed in the proposed CAM architecture to turn off the current sources after a specific search period. Experiment results have shown that our CAM architecture can achieves 29.675% reduction in power consumption compared to the traditional NOR-type CAM. Keywords: Content-Addressable Memory、virtual match line (VML)、virtual ground line (VGL).