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Journal articles on the topic 'Ternary Content Addressable Memory'

Author: Grafiati

Published: 4 June 2021

Last updated: 8 February 2022

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1

Ullah, Zahid, and Sanghyeon Baeg. "Vertically Partitioned SRAM-Based Ternary Content Addressable Memory." International Journal of Engineering and Technology 4, no. 6 (2012): 760–64. http://dx.doi.org/10.7763/ijet.2012.v4.479.

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2

Datti, VenkataRamana, and Dr P. V. Sridevi. "A Novel Ternary Content Addressable Memory Cell." International Journal of Engineering & Technology 7, no. 4.24 (November 27, 2018): 67. http://dx.doi.org/10.14419/ijet.v7i4.24.21857.

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Ternary content addressable memories (TCAM) are used for parallel searching. The parallel searching, results high speed but consumes more power. For higher search speed applications, NOR type matchline TCAMs are useful. The NOR type matchline TCAM needs high power; therefore, the power reduction is the major objective of many reported designs. Here, a novel TCAM cell is proposed. The proposed Ternary CAM cell power consumption is 32% lesser than the NOR type matchline TCAM cell. Simulations are performed using cadence 45-nm technology.

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3

Khasanvis, Santosh, Mostafizur Rahman, and Csaba Andras Moritz. "Heterogeneous graphene–CMOS ternary content addressable memory." Journal of Parallel and Distributed Computing 74, no. 6 (June 2014): 2497–503. http://dx.doi.org/10.1016/j.jpdc.2013.08.002.

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4

Gnawali, Krishna Prasad, Seyed Nima Mozaffari, and Spyros Tragoudas. "Low Power Spintronic Ternary Content Addressable Memory." IEEE Transactions on Nanotechnology 17, no. 6 (November 2018): 1206–16. http://dx.doi.org/10.1109/tnano.2018.2869734.

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5

Ahmed, Ali, Kyungbae Park, and Sanghyeon Baeg. "Resource-Efficient SRAM-Based Ternary Content Addressable Memory." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 4 (April 2017): 1583–87. http://dx.doi.org/10.1109/tvlsi.2016.2636294.

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6

Ullah, Z., Kim Ilgon, and Sanghyeon Baeg. "Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory." IEEE Transactions on Circuits and Systems I: Regular Papers 59, no. 12 (December 2012): 2969–79. http://dx.doi.org/10.1109/tcsi.2012.2215736.

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7

Gupta, Mohit Kumar, and Mohd Hasan. "Robust High Speed Ternary Magnetic Content Addressable Memory." IEEE Transactions on Electron Devices 62, no. 4 (April 2015): 1163–69. http://dx.doi.org/10.1109/ted.2015.2398122.

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8

Singh, Preeti, and Rajesh Mehra. "FPGA based Ternary Content Addressable Memory using SRAM." International Journal of Engineering Trends and Technology 25, no. 2 (July 25, 2015): 66–69. http://dx.doi.org/10.14445/22315381/ijett-v25p212.

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9

Akurathi, Gangadhar, Suneel kumar Guntuku, and Babulu K. "Design and Implementation of Efficient Ternary Content Addressable Memory." International Journal on Cybernetics & Informatics 5, no. 4 (August 30, 2016): 279–87. http://dx.doi.org/10.5121/ijci.2016.5430.

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10

Ni, Kai, Xunzhao Yin, Ann Franchesca Laguna, Siddharth Joshi, Stefan Dünkel, Martin Trentzsch, Johannes Müller, et al. "Ferroelectric ternary content-addressable memory for one-shot learning." Nature Electronics 2, no. 11 (November 2019): 521–29. http://dx.doi.org/10.1038/s41928-019-0321-3.

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11

Guo, Qing, Xiaochen Guo, Yuxin Bai, Ravi Patel, Engin Ipek, and Eby G. Friedman. "Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing." IEEE Micro 35, no. 5 (September 2015): 62–71. http://dx.doi.org/10.1109/mm.2015.89.

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12

Vardhanarao, K. Vamsi. "Performance Evaluation of Ternary Content Addressable Memory and 3T-2R TCAM." International Journal for Research in Applied Science and Engineering Technology 7, no. 8 (August 31, 2019): 753–62. http://dx.doi.org/10.22214/ijraset.2019.8109.

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13

Spurthi Sowjanya, E., and N. Vinod Kumar. "A Novel Ternary Content Addressable Memory (TCAM) Design Using Reversible Logic." International Journal of Advanced Trends in Engineering, Science and Technology 2, no. 1 (January 1, 2017): 33. http://dx.doi.org/10.22413/ijatest/2017/v2/i1/48976.

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14

Yang, Shun-Hsun, Yu-Jen Huang, and Jin-Fu Li. "A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 10 (October 2012): 1909–13. http://dx.doi.org/10.1109/tvlsi.2011.2163205.

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15

Kimura, Shinya, Takuma Watanabe, Ryohei Yukawa, Takeshi Kumaki, Tomohiro Fujita, and Takeshi Ogura. "FPGA Implementation and Evaluation of Ternary Content Addressable Memory with Individuality." Journal of Signal Processing 20, no. 4 (2016): 137–40. http://dx.doi.org/10.2299/jsp.20.137.

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16

Manasi, Susmita Dey, Md Mamun Al-Rashid, Jayasimha Atulasimha, Supriyo Bandyopadhyay, and Amit Ranjan Trivedi. "Skewed Straintronic Magnetotunneling-Junction-Based Ternary Content-Addressable Memory—Part II." IEEE Transactions on Electron Devices 64, no. 7 (July 2017): 2842–48. http://dx.doi.org/10.1109/ted.2017.2706744.

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17

Manasi, Susmita Dey, Md Mamun Al-Rashid, Jayasimha Atulasimha, Supriyo Bandyopadhyay, and Amit Ranjan Trivedi. "Skewed Straintronic Magnetotunneling-Junction-Based Ternary Content-Addressable Memory—Part I." IEEE Transactions on Electron Devices 64, no. 7 (July 2017): 2835–41. http://dx.doi.org/10.1109/ted.2017.2706755.

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18

Ni, Kai, Xunzhao Yin, Ann Franchesca Laguna, Siddharth Joshi, Stefan Dünkel, Martin Trentzsch, Johannes Müller, et al. "Author Correction: Ferroelectric ternary content-addressable memory for one-shot learning." Nature Electronics 3, no. 2 (February 2020): 130. http://dx.doi.org/10.1038/s41928-020-0374-3.

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19

Kudithipudi, Dhireesha, and Eugene John. "Static Power Analysis and Estimation in Ternary Content Addressable Memory Cells." Journal of Low Power Electronics 3, no. 3 (December 1, 2007): 293–301. http://dx.doi.org/10.1166/jolpe.2007.144.

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20

Govindaraj, Rekha, and Swaroop Ghosh. "Design and Analysis of STTRAM-Based Ternary Content Addressable Memory Cell." ACM Journal on Emerging Technologies in Computing Systems 13, no. 4 (August 11, 2017): 1–22. http://dx.doi.org/10.1145/3060578.

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21

Zheng, Le, Sangho Shin, and Sung-Mo Steve Kang. "Memristor-based ternary content addressable memory (mTCAM) for data-intensive computing." Semiconductor Science and Technology 29, no. 10 (September 18, 2014): 104010. http://dx.doi.org/10.1088/0268-1242/29/10/104010.

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22

Irfan, Muhammad, Zahid Ullah, Mehdi Hasan Chowdhury, and Ray C. C. Cheung. "RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, no. 8 (August 2020): 1925–29. http://dx.doi.org/10.1109/tvlsi.2020.2993168.

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23

K., Dr Sharmilee. "Low Power and Low Latency Memristive-Ternary Content Addressable Memory Design Using Absolute Path Search Optimization (APSO) Algorithm." International Journal of Psychosocial Rehabilitation 23, no. 3 (September 30, 2019): 979–86. http://dx.doi.org/10.37200/ijpr/v23i3/pr190498.

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24

Baeg, S. "Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line." IEEE Transactions on Circuits and Systems I: Regular Papers 55, no. 6 (July 2008): 1485–94. http://dx.doi.org/10.1109/tcsi.2008.916624.

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25

Liu, Shu, Shaojing Su, Desheng Liu, Zhiping Huang, and Mingyan Xiao. "Efficient compression algorithm for ternary content addressable memory‐based regular expression matching." Electronics Letters 53, no. 3 (February 2017): 152–54. http://dx.doi.org/10.1049/el.2016.2613.

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26

Sardinha, Luiz H. B., Douglas S. Silva, Marcos A. M. Vieira, Luiz F. M. Vieira, and Omar P. Vilela Neto. "TCAM/CAM-QCA: (Ternary) Content Addressable Memory using Quantum-dot Cellular Automata." Microelectronics Journal 46, no. 7 (July 2015): 563–71. http://dx.doi.org/10.1016/j.mejo.2015.03.020.

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27

Uemura, Tetsuya, and Masafumi Yamamoto. "Three-valued magnetic tunnel junction for nonvolatile ternary content addressable memory application." Journal of Applied Physics 104, no. 12 (December 15, 2008): 123911. http://dx.doi.org/10.1063/1.3054174.

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28

Irfan, Muhammad, and Zahid Ullah. "G-AETCAM: Gate-Based Area-Efficient Ternary Content-Addressable Memory on FPGA." IEEE Access 5 (2017): 20785–90. http://dx.doi.org/10.1109/access.2017.2756702.

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29

Yang, Rui, Haitong Li, Kirby K. H. Smithe, Taeho R. Kim, Kye Okabe, Eric Pop, Jonathan A. Fan, and H. S. Philip Wong. "Ternary content-addressable memory with MoS2 transistors for massively parallel data search." Nature Electronics 2, no. 3 (March 2019): 108–14. http://dx.doi.org/10.1038/s41928-019-0220-7.

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30

Hellkamp, Daniel, and Kundan Nepal. "True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors." Journal of Circuits, Systems and Computers 28, no. 05 (May 2019): 1950085. http://dx.doi.org/10.1142/s0218126619500853.

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Carbon nanotube-based transistors (CNTFETs) have been shown to exhibit ambipolar field-effect transistor behavior, allowing circuit designers to easily choose between [Formula: see text]- and [Formula: see text]-conduction channels by applying correct voltages at a polarity gate. In this paper, we explore this ambipolar behavior of the CNTFET to design both binary and ternary content addressable memory (AM) cells. Using SPICE simulation, we show the designs of a traditional ternary CAM (TCAM) and a true three-valued TCAM (T3-CAM) functionality of the proposed cells and show that the ambipolar design can lead to a savings of up to 31% in terms of transistor count over a traditional design. We also explore issues related to matchline leakage, cell stability and design in the presence of metallic tubes.

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31

Ahn, Eun Hye, and Jun Rim Choi. "High Speed TCAM Design using SRAM Cell Stability." Journal of the Korea Industrial Information System Society 18, no. 5 (October 31, 2013): 19–23. http://dx.doi.org/10.9723/jksiis.2013.18.5.019.

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32

Chen, Ting-Sheng, Ding-Yuan Lee, Tsung-Te Liu, and An-Yeu Wu. "Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing." IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 10 (October 2016): 1661–72. http://dx.doi.org/10.1109/tcsi.2016.2584658.

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33

Hellkamp, Daniel, and Kundan Nepal. "Metallic tube-tolerant ternary dynamic content-addressable memory based on carbon nanotube transistors." Micro & Nano Letters 10, no. 4 (April 1, 2015): 209–12. http://dx.doi.org/10.1049/mnl.2014.0582.

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34

Durai, Jothi, Sivakumar Rajagopal, and Geetha Ganesan. "Design and Analysis of Power-Efficient Quasi-Adiabatic Ternary Content Addressable Memory (QATCAM)." IET Circuits, Devices & Systems 14, no. 7 (October 1, 2020): 923–28. http://dx.doi.org/10.1049/iet-cds.2019.0223.

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35

Trinh, Nguyen, Anh Le Thi Kim, Hung Nguyen, and Linh Tran. "Algorithmic TCAM on FPGA with data collision approach." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (April 1, 2021): 89. http://dx.doi.org/10.11591/ijeecs.v22.i1.pp89-96.

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<span>Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.</span>

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36

Ullah, Inayat, Joon-Sung Yang, and Jaeyong Chung. "ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, no. 4 (April 2020): 1084–88. http://dx.doi.org/10.1109/tvlsi.2020.2968365.

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37

Yakopcic, C., V. Bontupalli, R. Hasan, D. Mountain, and T. M. Taha. "Self‐biasing memristor crossbar used for string matching and ternary content‐addressable memory implementation." Electronics Letters 53, no. 7 (March 2017): 463–65. http://dx.doi.org/10.1049/el.2017.0394.

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38

Venkata Mahendra, Telajala, Sheikh Wasmir Hussain, Sandeep Mishra, and Anup Dandapat. "Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 7 (July 2020): 2345–57. http://dx.doi.org/10.1109/tcsi.2020.2978295.

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39

Kim, Jeong-Su, and Jeong-Beom Kim. "Low-Power Ternary Content-Addressable Memory Using Power Reduction of Match-Line and Search-Line." International Journal of Intelligent Engineering and Systems 11, no. 4 (August 31, 2018): 42–49. http://dx.doi.org/10.22266/ijies2018.0831.05.

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40

Matsunaga, Shoun, Kimiyuki Hiyama, Atsushi Matsumoto, Shoji Ikeda, Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu. "Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices." Applied Physics Express 2 (February 6, 2009): 023004. http://dx.doi.org/10.1143/apex.2.023004.

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41

Cho, Dooho, Kyungmin Kim, and Changsik Yoo. "A Non-Volatile Ternary Content-Addressable Memory Cell for Low-Power and Variation-Toleration Operation." IEEE Transactions on Magnetics 54, no. 2 (February 2018): 1–3. http://dx.doi.org/10.1109/tmag.2017.2763579.

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42

Pao, D., P. Zhou, B. Liu, and X. Zhang. "Enhanced prefix inclusion coding filter-encoding algorithm for packet classification with ternary content addressable memory." IET Computers & Digital Techniques 1, no. 5 (2007): 572. http://dx.doi.org/10.1049/iet-cdt:20060226.

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43

Nguyen, Triet, Kiet Ngo, Nguyen Trinh, Bao Bui, Linh Tran, and Hoang Trang. "Efficient TCAM design based on dual port SRAM on FPGA." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (April 1, 2021): 104. http://dx.doi.org/10.11591/ijeecs.v22.i1.pp104-112.

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<span><span>Ternary content addressable memory (TCAM) is a memory that allows high speed searching for data. Not only it is acknowledged as associative memory/storage but also TCAM can compare input searching content (key) against a collection of accumulated data and return the matching address which compatible with this input search data. SRAM-based TCAM utilizes and allocates blocks RAM to perform application of TCAM on FPGA hardware. This paper presents a design of 480×104 bit SRAM-based TCAM on altera cyclone IV FPGA. Our design achieved lookup rate over 150 millions input search data and update speed at 75 million rules per second. The architecture is configurable, allowing various performance trade-offs to be exploited for different ruleset characteristics</span>.</span>

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44

Kay, Ng Shao, and M. N. Marsono. "Ternary content addressable memory for longest prefix matching based on random access memory on field programmable gate array." TELKOMNIKA (Telecommunication Computing Electronics and Control) 17, no. 4 (August 1, 2019): 1882. http://dx.doi.org/10.12928/telkomnika.v17i4.11000.

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45

Han, Runze, Wensheng Shen, Peng Huang, Zheng Zhou, Lifeng Liu, Xiaoyan Liu, and Jinfeng Kang. "A novel ternary content addressable memory design based on resistive random access memory with high intensity and low search energy." Japanese Journal of Applied Physics 57, no. 4S (February 21, 2018): 04FE02. http://dx.doi.org/10.7567/jjap.57.04fe02.

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46

Shaban, Ahmed, Sayeed Ahmad, Naushad Alam, and Mohd Hasan. "Compact and Low Power 11T-2MTJ Non-Volatile Ternary Content Addressable Memory Cell with High Sense Margin." Journal of Low Power Electronics 15, no. 2 (June 1, 2019): 193–203. http://dx.doi.org/10.1166/jolpe.2019.1608.

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47

Igor, A., C. Trevis, and A. Sheikholeslami. "A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme." IEEE Journal of Solid-State Circuits 38, no. 1 (January 2003): 155–58. http://dx.doi.org/10.1109/jssc.2002.806264.

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48

Matsunaga, Shoun, Akira Katsumata, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu. "Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory." Japanese Journal of Applied Physics 51, no. 2 (February 20, 2012): 02BM06. http://dx.doi.org/10.1143/jjap.51.02bm06.

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49

Matsunaga, Shoun, Akira Katsumata, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu. "Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory." Japanese Journal of Applied Physics 51, no. 2S (February 1, 2012): 02BM06. http://dx.doi.org/10.7567/jjap.51.02bm06.

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50

Chang, Yen-Jen, Kun-Lin Tsai, Yu-Cheng Cheng, and Meng-Rong Lu. "Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment." Computers & Electrical Engineering 81 (January 2020): 106528. http://dx.doi.org/10.1016/j.compeleceng.2019.106528.

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