Relevant bibliographies by topics / Test Pattern Compaction

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Test Pattern Compaction'

Author: Grafiati
Published: 4 June 2021
Last updated: 7 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Test Pattern Compaction.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Test Pattern Compaction"

1

Hou, Jing Ru, and Li Jun Zhao. "Effect of Different Compaction Methods on Bridge Pavement." Advanced Materials Research 671-674 (March 2013): 1073–77. http://dx.doi.org/10.4028/www.scientific.net/amr.671-674.1073.

Full text
Abstract:
In order to analyze the influence of different compaction methods on bridge deck vibration and bridge pavement compaction quality, the field test and laboratory test of oscillating compaction and vibrating compaction were carried out. The results demonstrated bridge deck vibration caused by the intrinsic exciting force of compactor contributed to vibrating compaction. On the pattern of oscillating compaction, the disturbance of bridge deck due to the exciting force of compactor is the main factor to induce bridge vibration. Furthermore, the vibration acceleration and amplitude in lateral, long
APA, Harvard, Vancouver, ISO, and other styles
2

Ayari, B., and B. Kaminska. "A new dynamic test vector compaction for automatic test pattern generation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 3 (1994): 353–58. http://dx.doi.org/10.1109/43.265676.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

MATSUNAGA, Yusuke. "A Test Pattern Compaction Method Using SAT-Based Fault Grouping." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E99.A, no. 12 (2016): 2302–9. http://dx.doi.org/10.1587/transfun.e99.a.2302.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Abdullah, Ayub Chin, and Chia Yee Ooi. "Study on Test Compaction in High-Level Automatic Test Pattern Generation (ATPG) Platform." Circuits and Systems 04, no. 04 (2013): 342–49. http://dx.doi.org/10.4236/cs.2013.44046.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Saravanan, S., and Har Narayan Upadhyay. "Achieving Low Power Test Pattern By Efficient Compaction Method For SoC Design." Journal of Artificial Intelligence 5, no. 4 (2012): 244–48. http://dx.doi.org/10.3923/jai.2012.244.248.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Qu, Yang, Ying Dai, and Han Yang Li. "Transverse Compaction Analysis of 2.5D Preform Composite." Key Engineering Materials 729 (February 2017): 51–57. http://dx.doi.org/10.4028/www.scientific.net/kem.729.51.

Full text
Abstract:
Transverse compaction is an important pattern of deformation during the composite resin transfer molding (RTM) process. Reasonable compaction rate is related to both the composite mould design and the fiber volume fraction of the final composite. In this paper, a mesoscopic geometry model based on CT scanning of 2.5D preform reinforcements is presented. Applying this model to the FEM simulation of transverse compaction, we prove the validation on simulating transverse compaction property of 2.5D preform by comparing to results of compaction test. Orientation angle during the progressive compac
APA, Harvard, Vancouver, ISO, and other styles
7

Nithya, N. "An Efficient Implementation of Built in Self Diagnosis for Low Power Test Pattern Generator." International Journal of Students' Research in Technology & Management 3, no. 2 (2015): 269–72. http://dx.doi.org/10.18510/ijsrtm.2015.326.

Full text
Abstract:
A New architecture of Built-In Self-Diagnosis is presented in this project. The logic Built-In-Self-Test architecture method is extreme response compaction architecture. This architecture first time enables an autonomous on-chip evaluation of test responses with negligible hardware overhead. Architecture advantage is all data, which is relevant for a subsequent diagnosis, is gathered during just one test session. Due to some reasons, the existing method Built-In Self-Test is less often applied to random logic than to embedded memories. The generation of deterministic test patterns can become p
APA, Harvard, Vancouver, ISO, and other styles
8

Santini, Manuela Favarin, Marília Pivetta Rippe, Gisele Jung Franciscatto, et al. "Canal Preparation and Filling Techniques do not Influence the Fracture Resistance of Extensively Damaged Teeth." Brazilian Dental Journal 25, no. 2 (2014): 129–35. http://dx.doi.org/10.1590/0103-6440201302392.

Full text
Abstract:
The purpose of this study was to assess the fracture resistance of extensively damaged teeth after two root canal preparation techniques (hand and rotary files) and after two filling techniques (active and passive compaction). Sixty-eight maxillary canines roots with an apical diameter equal to that of a #25 K-file were embedded in acrylic resin and the periodontal ligament was simulated by using a polyether impression material. The roots were randomly distributed into four groups (n=17): hand preparation and active compaction (HA), hand preparation and passive compaction (HP), rotary preparat
APA, Harvard, Vancouver, ISO, and other styles
9

ZHANG, Wenpo, Kazuteru NAMBA, and Hideo ITO. "Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement." IEICE Transactions on Information and Systems E97.D, no. 3 (2014): 533–40. http://dx.doi.org/10.1587/transinf.e97.d.533.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

YAMAZAKI, Hiroshi, Motohiro WAKAZONO, Toshinori HOSOKAWA, and Masayoshi YOSHIMURA. "A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution." IEICE Transactions on Information and Systems E96.D, no. 9 (2013): 1994–2002. http://dx.doi.org/10.1587/transinf.e96.d.1994.

Full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Test Pattern Compaction"

1

Jha, Sharada. "Compaction mechanism to reduce test pattern counts and segmented delay fault testing for path delay faults." Diss., University of Iowa, 2013. https://ir.uiowa.edu/etd/2533.

Full text
Abstract:
With rapid advancement in science and technology and decreasing feature size of transistors, the complexity of VLSI designs is constantly increasing. With increasing density and complexity of the designs, the probability of occurrence of defects also increases. Therefore testing of designs becomes essential in order to guarantee fault-free operation of devices. Testing of VLSI designs involves generation of test patterns, test pattern application and identification of defects in design. In case of scan based designs, the test set
APA, Harvard, Vancouver, ISO, and other styles
2

Chen, Yu-Wei, and 陳佑維. "Parallel Order Automatic Test Pattern Generation for Test Compaction." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/3gdz7u.

Full text
Abstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>105<br>Generating a compacted test set is very important to reduce the cost of testing. In this thesis, we proposed a novel test compaction algorithm which achieve high compaction, called Parallel Order Dynamic Test Compaction (PO-DTC). Our results show that the order of secondary faults within a single test generation is very important for test compaction. We use GPU to launch many parallel ATPG with different orders of secondary faults. Then we choose the best test pattern, which detects the largest number of faults. Experimental results show that our test le
APA, Harvard, Vancouver, ISO, and other styles
3

Li, Bo-Yi, and 李柏毅. "Reducing Test Pattern Count by A Parallel N-pattern Compaction ATPG." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/s29q7e.

Full text
Abstract:
碩士<br>國立臺灣大學<br>電子工程學研究所<br>106<br>As VLSI designs continue to grow in size and complexity, the demand for high-quality test sets arises for testing. However, the size of the high-quality test set is usually very large so the method of test pattern compaction becomes very important. In this thesis, we proposed a parallel N-pattern compaction ATPG which is based on a multi-threading system. The proposed ATPG can improve the compaction efficiency to reduce the test pattern count. Determinism is also considered in our technique. The proposed techniques are validated using ISCAS89 (Internationa
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Test Pattern Compaction"

1

Badura, Dariusz. "Efficiency of Self-Test Path as a Test Pattern Generator and Test Response Compactor." In Fehlertolerierende Rechensysteme / Fault-tolerant Computing Systems. Springer Berlin Heidelberg, 1989. http://dx.doi.org/10.1007/978-3-642-75002-1_30.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Test Pattern Compaction"

1

Czutro, Alexander, Sudhakar M. Reddy, Ilia Polian, and Bernd Becker. "SAT-Based Test Pattern Generation with Improved Dynamic Compaction." In 2014 27th International Conference on VLSI Design. IEEE, 2014. http://dx.doi.org/10.1109/vlsid.2014.17.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Kajihara, Seiji, Makoto Matsuzono, Hisato Yamaguchi, Yasuo Sato, Kohei Miyase, and Xiaoqing Wen. "On test pattern compaction with multi-cycle and multi-observation scan test." In 2010 10th International Symposium on Communications and Information Technologies (ISCIT). IEEE, 2010. http://dx.doi.org/10.1109/iscit.2010.5665084.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Galke, C., U. Gatzschmann, and H. T. Vierhaus. "Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes." In 9th EUROMICRO Conference on Digital System Design (DSD'06). IEEE, 2006. http://dx.doi.org/10.1109/dsd.2006.83.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Haghbayan, M. H., S. Karamati, F. Javaheri, and Z. Navabi. "Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment." In 2010 19th Asian Test Symposium (ATS). IEEE, 2010. http://dx.doi.org/10.1109/ats.2010.85.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Tatenguem, Herve', Alessandro Strano, Vineeth Govind, Jaan Raik, and Davide Bertozzi. "Ultra-low latency NoC testing via pseudo-random test pattern compaction." In 2012 International Symposium on System-on-Chip - SOC. IEEE, 2012. http://dx.doi.org/10.1109/issoc.2012.6376370.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Gao, Lixin, Yongliang Zhang, and Jinhong Zhao. "BIST using Cellular Automata as test pattern generator and response compaction." In 2012 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet). IEEE, 2012. http://dx.doi.org/10.1109/cecnet.2012.6201620.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Li, Bo-Yi, and Jiun-Lang Huang. "A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction." In 2018 International SoC Design Conference (ISOCC). IEEE, 2018. http://dx.doi.org/10.1109/isocc.2018.8649901.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Ju-Yueh Lee, Yu Hu, Rupak Majumdar, and Lei He. "Simultaneous test pattern compaction, ordering and X-filling for testing power reduction." In 2009 10th International Symposium on Quality of Electronic Design (ISQED). IEEE, 2009. http://dx.doi.org/10.1109/isqed.2009.4810379.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Hasan, Shehzad, Ajoy K. Palit, and Walter Anheier. "Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults." In 2010 23rd International Conference on VLSI Design: concurrently with the 9th International Conference on Embedded Systems Design (VLSID). IEEE, 2010. http://dx.doi.org/10.1109/vlsi.design.2010.30.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Quadrini, Fabrizio, Daniele Santoro, Leandro Iorio, and Loredana Santo. "Conical Thermoplastic Composite Anisogrid Lattice Structure by Innovative Out-of-Autoclave Molding Process." In ASME 2021 16th International Manufacturing Science and Engineering Conference. American Society of Mechanical Engineers, 2021. http://dx.doi.org/10.1115/msec2021-63821.

Full text
Abstract:
Abstract A new manufacturing process for thermoplastic (TP) composite parts has been used to produce conical anisogrid composite lattice structure (ACLS). An out-of-autoclave (OOA) process has been prototyped by using the compaction exerted by a heat-shrink tube after its exposition to heat in oven. Narrow thermoplastic prepreg tapes have been wounded on a metallic conical patterned mold at room temperature; then, the conical structure has been inserted in the heat-shrink tube and heated. TP unidirectional prepreg tapes have been used with polypropylene matrix and glass fibers. After molding,
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Test Pattern Compaction' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography