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Dissertations / Theses on the topic 'Test pattern generation'

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Published: 4 June 2021

Last updated: 26 July 2025

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1

Wong, Mike Wai-Tak. "Test pattern generation for synthesis systems." Thesis, University of Southampton, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.334672.

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2

Veskoukis, Damianos. "Automatic MC/DC Test Pattern Generation." OpenSIUC, 2018. https://opensiuc.lib.siu.edu/theses/2377.

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Today’s critical systems of military and aviation grade consist of several complex requirements that need to be assessed for a safe and continuous operation before they are deployed for use. Several coverage methodologies have been proposed over the years with Modified Condition / Decision Coverage (MC/DC) being chosen by the aviation industry. This practice is becoming a highly recommended coverage methodology among several modern standards such as the Automotive Safety Integrity Level (ASIL) of automotive standard ISO 26262 and the Safety integrity level (SIL) 4 in part 3 Annex B of the bas

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3

Vasudevan, Dilip Prasad. "Automatic test pattern generation for asynchronous circuits." Thesis, University of Edinburgh, 2012. http://hdl.handle.net/1842/7670.

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The testability of integrated circuits becomes worse with transistor dimensions reaching nanometer scales. Testing, the process of ensuring that circuits are fabricated without defects, becomes inevitably part of the design process; a technique called design for test (DFT). Asynchronous circuits have a number of desirable properties making them suitable for the challenges posed by modern technologies, but are severely limited by the unavailability of EDA tools for DFT and automatic test-pattern generation (ATPG). This thesis is motivated towards developing test generation methodologies for asy

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4

Samala, Keerthana. "Test Pattern Generation for Double Transition faults." OpenSIUC, 2018. https://opensiuc.lib.siu.edu/theses/2374.

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Keerthana Samala, for the Master of Science degree in Electrical and Computer, presented on 05/11/2018, at Southern Illinois University Carbondale. TITLE: Test Pattern Generation for Double Transition Faults MAJOR PROFESSOR: Dr. Spyros Tragoudas Under double transition fault model, a fault is associated with a pair of lines and a pair of transitions on these lines. The proposed double transition fault model includes set of cases where the increased delay of a single faulty line may be too small to cause the faulty behavior of the circuit. However, when this delay propagates through another fau

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5

Abdulrahman, Arkan M. "Test pattern generation techniques that target low test application time /." Available to subscribers only, 2008. http://proquest.umi.com/pqdweb?did=1564033201&sid=10&Fmt=2&clientId=1509&RQT=309&VName=PQD.

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Thesis (Ph. D.)--Southern Illinois University Carbondale, 2008.<br>"Department of Electrical and Computer Engineering." Keywords: Test pattern generation, Test application time Includes bibliographical references (p. 87-95). Also available online.

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6

Geada, Joao Moreno Colaco. "A study of mixed mode test pattern generation methods." Thesis, University of Newcastle Upon Tyne, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.315547.

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7

LIU, JIANXUN. "TEST PATTERN GENERATION FOR CROSSTALK FAULT IN DYNAMIC PLA." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1069779563.

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8

Udar, Snehal. "Built-In Schemes for Test Pattern Generation and Fault Location." OpenSIUC, 2011. https://opensiuc.lib.siu.edu/dissertations/410.

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Snehal Udar, for the Doctor of Philosophy degree in Electrical and Computer Engineering, presented on May 4, of 2011, at Southern Illinois University Carbondale. TITLE: BUILT-IN SCHEMES FOR TEST PATTERN GENERATION AND FAULT LOCATION MAJOR PROFESSOR: Dr. D. Kagaris In this dissertation, we studied the areas of test pattern generation and fault location for detecting and diagnosing the faults in today's complex chips. In the first problem, a novel reseeding based test pattern generation scheme is analyzed by proposing a hardware efficient technique that uses irreducible polynomial-primitive elem

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9

Asokan, Anu. "Signal Integrity - Aware Pattern Generation for Delay Testing." Thesis, Montpellier, 2015. http://www.theses.fr/2015MONTS206/document.

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La miniaturisation des circuits intégrés permet d'avoir une intégration plus élevée dans une même puce. Cela, conduit a des problèmes de qualité dans les signaux de communication et d’alimentation comme le phénomène de bruit de diaphonie entre les interconnections (Crosstalk) et de bruit dans le lignes d'alimentation (PSN, GB). Aussi problèmes de fiabilité peuvent éventuellement arriver a cause des variations dans les paramètres technologiques pendant le processus de fabrication. De ce fait, tout ces phénomènes ont un effet négatif sur le délai dans les circuits embarques (IC) et donnent lieu

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10

Doshi, Alok Shreekant Agrawal Vishwani D. "Independence fault collapsing and concurrent test generation." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Spring/master's/DOSHI_ALOK_48.pdf.

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11

Robinson, Markus F. "A method of test pattern generation for programmable logic arrays /." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59285.

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A method for PLA test pattern generation based on a branch and bound algorithm that exploits function monotonicity is presented. The algorithm makes irrevocable input assignments first, resulting in the efficient generation of compact test sets. In most cases there is no backtracking. An intelligent branching heuristic is presented. The algorithm handles extended fault models including crosspoint and delay faults. Heuristics which speed up test set generation and improve test set compaction are discussed.<br>Results of tests on a wide range of benchmark PLAs are included.

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12

Cox, Henry. "On necessary and nonconflicting assignments in algorithmic test pattern generation." Thesis, McGill University, 1991. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=74628.

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Necessary, nonconflicting, and arbitrary assignments can be distinguished during algorithmic test pattern generation. A necessary assignment is one which must be made in order to find a test--there is no test in the half-space define by the opposite assignment. Certain other assignments are nonconflicting in the sense that they narrow the search space and never lead to backtracking--if the fault is testable, then there is at least one test vector in the half-space defined by the assignment. The remaining assignments are arbitrary--they may or may not lead in the direction of a test and may or

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13

Koripalli, Venkat N. "An automatic test pattern generation technique for sequential circuits using scan applications /." Available to subscribers only, 2006. http://proquest.umi.com/pqdweb?did=1203571411&sid=16&Fmt=2&clientId=1509&RQT=309&VName=PQD.

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14

Lee, Hyung Ki. "Fault simulation and test pattern generation for synchronous and asynchronous sequential circuits." Diss., This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-06062008-171759/.

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15

Prabhu, Sarvesh P. "Techniques for Enhancing Test and Diagnosis of Digital Circuits." Diss., Virginia Tech, 2015. http://hdl.handle.net/10919/51181.

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Test and Diagnosis are critical areas in semiconductor manufacturing. Every chip manufactured using a new or premature technology or process needs to be tested for manufacturing defects to ensure defective chips are not sold to the customer. Conventionally, test is done by mounting the chip on an Automated Test Equipment (ATE) and applying test patterns to test for different faults. With shrinking feature sizes, the complexity of the circuits on chip is increasing, which in turn increases the number of test patterns needed to test the chip comprehensively. This increases the test application t

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16

Sudireddy, Samara Simha Reddy. "Accumulator Based Test Set Embedding." OpenSIUC, 2009. https://opensiuc.lib.siu.edu/theses/18.

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In this paper a test set embedding based on accumulator driven by an odd additive constant is presented. The problem is formulated around finding the location of the test pattern in the sequence generated by the accumulator, given a odd constant C and test set T, in terms of linear Diophantine equation of two variables. We show that the search space for finding the best constant corresponding to the shortest length, is greatly reduced. Experimental results show a significant improvement in run time with practically acceptable test length.

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17

Duong, Khanh Viet. "On Enhancing Deterministic Sequential ATPG." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/31283.

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This thesis presents four different techniques for improving the average-case performance of deterministic sequential circuit Automatic Test Patterns Generators (ATPG). Three techniques make use of information gathered during test generation to help identify more unjustifiable states with higher percentage of â donâ t careâ value. An approach for reducing the search space of the ATPG was introduced. The technique can significantly reduce the size of the search space but cannot ensure the completeness of the search. Results on ISCASâ 85 benchmark circuits show that all of the proposed tech

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18

Bhamidipati, Harini. "SINGLE TROJAN INJECTION MODEL GENERATION AND DETECTION." Case Western Reserve University School of Graduate Studies / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=case1253543191.

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19

Acevedo, Oscar. "On the Computation of LFSR Characteristic Polynomials for One-Dimensional and Two-Dimensional Test Pattern Generation." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/893.

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Current methodologies for built-in test pattern generation usually employ a predetermined linear feedback shift register (LFSR) in order to generate or decompress deterministic test patterns. As a direct consequence, the test pattern computation and the fault coverage are constrained to the preselected architecture. Work has been done to determine desirable characteristics in the LFSR to be used. Also, work has been done in the use of these predefined architectures, in order to compact the test data. In general, these methodologies take advantage of the large amount of don't care bits present

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20

Bieliauskas, Petras. "Funkcinių testinių rinkinių vėlinimo gedimams atrinkimo programinės įrangos sudarymas ir tyrimas." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2010. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2010~D_20100813_113257-52202.

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Dėl didėjančio integrinių schemų sudėtingumo ir darbinių dažnių vėlinimo gedimų nustatymas tampa svarbia schemų kūrimo dalimi. Programiniai schemų prototipai leidžia atlikti schemų testavimą ankstyvojoje stadijoje. Šiame darbe yra pateikiama vėlinimo gedimų nustatymo metodų analizė ir jų palyginimas. Tyrimo objektu pasirinktas perėjimo gedimų modelis. Dokumente aprašomas AntiRandom metodo pritaikymo galimybės funkcinių testų generavimui. Taip pat yra trumpai apžvelgiami egzistuojantys sprendimai rinkoje. Projektavimo skyriuje yra aprašoma suprojektuota ir realizuota sistema, kuri susideda iš d

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21

Drovnenkov, Aleksej. "Testinių rinkinių atrinkimo programinės įrangos sudarymas ir tyrimas." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2007. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2007~D_20070816_143508-11175.

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Automatinis testų rinkinių generavimas (pasaulyje priimtas angliškas sutrumpinimas – ATPG) yra pakankamai senai sprendžiama problema. Jos tikslas – surasti optimalų testinių vektorių sekas, kurios pilnai užtikrintų visas schemos gamybos etape padarytas klaidas per mažiausią laiką. Vienas iš skaitmeninių schemų testavimo ir testų rinkinių sudarymo metodas yra funkcinis testavimo metodas. Jo privalumai yra tame, kad testų rinkinių sudarymo programa nežino schemos vidinės struktūros, o testuoja tik idealų schemos modelį, kuri yra pateikta juodos dėžės pavidale, tai yra programa gali gauti idealau

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22

Lee, Hoon-Kyeu. "An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183139647.

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23

Cosgrove, S. J. "Expert system technology applied to the testing of complex digital electronic architectures : TEXAS; a synergistic test strategy planning and functional test pattern generation methodology applicable to the design, development and testing of complex digit." Thesis, Brunel University, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234077.

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24

Qiang, Qiang. "FORMAL a sequential ATPG-based bounded model checking system for VLSI circuits /." online version, 2006. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=case1144614543.

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25

Tanwir, Sarmad. "Online Techniques for Enhancing the Diagnosis of Digital Circuits." Diss., Virginia Tech, 2018. http://hdl.handle.net/10919/82736.

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The test process for semiconductor devices involves generation and application of test patterns, failure logging and diagnosis. Traditionally, most of these activities cater for all possible faults without making any assumptions about the actual defects present in the circuit. As the size of the circuits continues to increase (following the Moore's Law) the size of the test sets is also increasing exponentially. It follows that the cost of testing has already surpassed that of design and fabrication. The central idea of our work in this dissertation is that we can have substantial savings in

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26

Benali, Aadil. "Contribution à l'amélioration de la qualité du test de circuits imprimés nus : exploitation des informations CAO, par des techniques de traitement d'images, en vue de la génération des données du test électrique." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0189.

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La presente these traite du test de circuits imprimes nus et en particulier de l'amelioration de la qualite du test par l'etude et l'optimisation des diverses parties du processus de test. En raison de l'evolution rapide de la micro-electronique et en particulier de la connectique (conditionnement des puces), les cartes electroniques sont de plus en plus complexes avec des circuits imprimes tres denses presentant des pistes de largeur inferieure a 100m et des pastilles rapprochees les unes des autres a moins de 200m. En outre et a raison de la finesse souhaitee par des contraintes electriques

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27

Kummari, Chandrashekar. "Embedded test pattern generator for memories /." Available to subscribers only, 2006. http://proquest.umi.com/pqdweb?did=1240704151&sid=1&Fmt=2&clientId=1509&RQT=309&VName=PQD.

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28

Thakar, Sarita. "On the generation of test patterns for combinational circuits." Thesis, Virginia Tech, 1993. http://hdl.handle.net/10919/41915.

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29

Sánchez, Clara. "BIST test pattern generator based on partitioning circuit inputs." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/36580.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.<br>Includes bibliographical references (leaves 33-35).<br>by Clara Sánchez.<br>M.Eng.

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30

Mohamed, Mohamed Hassan Wahba Ayman. "Diagnostic des erreurs de conception dans les circuits digitaux : le cas des erreurs simples." Grenoble 1, 1997. http://www.theses.fr/1997GRE10086.

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Le diagnostic automatique des erreurs de conception est un probleme important dans le domaine de la cao. Bien que des outils automatises de synthese soient employes pour generer des structures de circuits correctes-par-construction, celles-ci sont souvent modifiees manuellement pour refleter des petites modifications faites sur la specification, ou pour ameliorer certaines caracteristiques critiques de la conception. Les outils de verification peuvent reveler l'existence d'erreurs, mais ils ne donnent aucune information sur leurs emplacements ou la facon de les corriger. Ces outils generent se

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31

Dworak, Jennifer Lynn. "Modeling defective part level due to static and dynamic defects based upon site observation and excitation balance." Diss., Texas A&M University, 2004. http://hdl.handle.net/1969.1/323.

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Manufacture testing of digital integrated circuits is essential for high quality. However, exhaustive testing is impractical, and only a small subset of all possible test patterns (or test pattern pairs) may be applied. Thus, it is crucial to choose a subset that detects a high percentage of the defective parts and produces a low defective part level. Historically, test pattern generation has often been seen as a deterministic endeavor. Test sets are generated to deterministically ensure that a large percentage of the targeted faults are detected. However, many real defects do not behave like

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32

Guntzel, Jose Luis Almada. "Functional timing analysis of VLSI circuits containing complex gates." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2000. http://hdl.handle.net/10183/1883.

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Os recentes avanços experimentados pela tecnologia CMOS tem permitido a fabricação de transistores em dimensões submicrônicas, possibilitando a integração de dezenas de milhões de dispositivos numa única pastilha de silício, os quais podem ser usados na implementação de sistemas eletrônicos muito complexos. Este grande aumento na complexidade dos projetos fez surgir uma demanda por ferramentas de verificação eficientes e sobretudo que incorporassem modelos físicos e computacionais mais adequados. A verificação de timing objetiva determinar se as restrições temporais impostas ao projeto podem o

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33

Pagalone, Vinod. "Automatic test pattern generator for full scan sequential circuits using limited scan operations /." Available to subscribers only, 2006. http://proquest.umi.com/pqdweb?did=1251871351&sid=8&Fmt=2&clientId=1509&RQT=309&VName=PQD.

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34

Kincl, Zdeněk. "Metody pro testování analogových obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-233583.

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Práce se zabývá metodami pro testování lineárních analogových obvodů v kmitočtové oblasti. Cílem je navrhnout efektivní metody pro automatické generování testovacího plánu. Snížením počtu měření a výpočetní náročnosti lze výrazně snížit náklady za testování. Práce se zabývá multifrekveční parametrickou poruchovou analýzou, která byla plně implementována do programu Matlab. Vhodnou volbou testovacích kmitočtů lze potlačit chyby měření a chyby způsobené výrobními tolerancemi obvodových prvků. Navržené metody pro optimální volbu kmitočtů byly statisticky ověřeny metodou MonteCarlo. Pro zvýšení př

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35

Kang, Lei. "Robust Handwritten Text Recognition in Scarce Labeling Scenarios: Disentanglement, Adaptation and Generation." Doctoral thesis, Universitat Autònoma de Barcelona, 2020. http://hdl.handle.net/10803/672067.

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Els documents escrits a mà no només es conserven en arxius històrics, sinó que també s’utilitzen àmpliament en documents administratius, com ara xecs o formularis. Amb l’auge de de l’anomenat aprenentatge profund (Deep Learning), s’ha aconseguit un bon rendiment en conjunts de dades específics per al reconeixement de text manuscrit. Tot i això, encara és difícil resoldre casos d’ús reals a causa de la variació entre estils d’escriptura de diferents escriptors i el fet de tenir dades etiquetades limitades. Per tant, es requereix explorar arquitectures de reconeixement d’escriptura més sòlides a

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36

WANG, LING-LING, and 王玲玲. "Hierarchical test pattern generation." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/66441163652381714552.

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37

Lu, Zhen Li, and 呂貞里. "Test pattern generation in BIST." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/49583747299427144123.

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38

LI, ZHENG-YU, and 李正宇. "Techniques of test pattern generation." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/96030065102587239556.

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39

Liao, Chien-Feng, and 廖健峰. "Low Power Test Pattern Generation." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/79913466081945640392.

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碩士<br>元智大學<br>資訊工程學系<br>98<br>This paper presents a method to produce test patterns which can reduce shift power and capture power. The method is implemented by D-algorithm and SCOAP. By setting the initial controllability values of state inputs and primary inputs, and setting the initial observability values of state outputs and primary outputs, and propagating the faults to primary outputs as far as possible, so the numbesr of capture will be reduced .And we loacate care bits possible on primary inputs, then we find the corrsponding pattern by justify when producing the test data using D-al

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Chen, Yu-Wei, and 陳佑維. "Parallel Order Automatic Test Pattern Generation for Test Compaction." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/3gdz7u.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>105<br>Generating a compacted test set is very important to reduce the cost of testing. In this thesis, we proposed a novel test compaction algorithm which achieve high compaction, called Parallel Order Dynamic Test Compaction (PO-DTC). Our results show that the order of secondary faults within a single test generation is very important for test compaction. We use GPU to launch many parallel ATPG with different orders of secondary faults. Then we choose the best test pattern, which detects the largest number of faults. Experimental results show that our test le

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41

GAO, YI-LANG, and 高一郎. "Sequential circuit test pattern generation with reduction." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/04121290713157945995.

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42

Gao, Yi-Lang, and 高一郎. "Sequential circuit test pattern generation with reduction." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/92248929444755266746.

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43

潘世勳. "Simulation-based sequential circuit test pattern generation." Thesis, 1991. http://ndltd.ncl.edu.tw/handle/69256368885394538793.

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44

Tseng, Yen-Po, and 曾彥博. "Test Pattern Generation for Capture Power Reduction." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/60149471222792635659.

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碩士<br>元智大學<br>資訊工程學系<br>95<br>Power dissipation has become an important issue in VLSI testing due to the growing complexity of designing integrated circuits. In scan-based testing, switching activity dominates total power consumption. Additionally, high power dissipation causes excessive IR drop during capture cycles and thus the loss of yield is significant. In this thesis we proposed a test pattern generation method to reduce the power dissipation during capture cycle. As the fault coverage will not be affected by assigning the don’t care bits, the proposed method is based on generating a te

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45

So, Byungse. "Time efficient automatic test pattern generation systems." 1994. http://catalog.hathitrust.org/api/volumes/oclc/32437734.html.

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Thesis (Ph. D.)--University of Wisconsin--Madison, 1994.<br>Typescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (leaves 121-128).

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46

GUO, DA-YUAN, and 郭達源. "Automatic test pattern generation for CMOS combinational circuits." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/24125839437845306704.

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47

Tsai, Cheng-Liang, and 蔡政良. "Automatic Test Pattern Generation for CMOS Bridging Faults." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/10936393632964352478.

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碩士<br>國立成功大學<br>電機工程研究所<br>83<br>In this thesis an ATPG (Automatic Test Pattern Generation) system for CMOS bridging faults is developed. The test generation part of the system is PODEM-based. Some improvement techniques from other efficient test generators such as FAN and SOCRATES are also implemented. The fault simulation part is based on PPSFP algorithm. Recently developed as well as some new techniques are incorporated into the system to achieve high quality of test, These techniques in

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48

Chang, Soon Jyh, and 張順志. "Functional Test Pattern Generation for CMOS Operational Amplifier." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/91909796176583601266.

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碩士<br>國立交通大學<br>電子研究所<br>84<br>In this thesis, we generate functional test patterns for CMOS operational amplifier. The circuit behavior of an analog circuit can be represented by an arithmetic function. It will deviate from its normal operation when a "fault" exists at the circuit. A good test pattern must give the maximum difference of the output response between the good circuit and the faulty one. We derive a set of functional test patterns based on the analysis to find the maximum diff

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49

GAO, ZONG-HONG, and 高宗宏. "Automated test pattern generation from VHDL behavioral description." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/64361367967908278273.

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Huang, Yin-Chao, and 黃英兆. "Hierarchical Fault Model and Its Test Pattern Generation." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/31912958687151182371.

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Abstract:

碩士<br>國立交通大學<br>電子工程系<br>87<br>"Hierarchy" approach is usually used either in analysis or design large scale system. In this thesis, we propose a hierarchical fault model and test pattern generation based on this model. At first, a transfer function model for an open-loop operational amplifier (OP) is presented based on analysis of element faults at the transistor level. Then another transfer function model is presented based on the derived open-loop OP level for the closed-loop OP level. This model is then used again to derive the higher level fault model for a system, for which a state-varia

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