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Dissertations / Theses on the topic 'Testability'

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Published: 4 June 2021

Last updated: 4 May 2024

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1

Zhou, Lixin. "Testability Design and Testability Analysis of a Cube Calculus Machine." PDXScholar, 1995. https://pdxscholar.library.pdx.edu/open_access_etds/4911.

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Cube Calculus is an algebraic model popular used to process and minimize Boolean functions. Cube Calculus operations are widely used in logic optimization, logic synthesis, computer image processing and recognition, machine learning, and other newly developing applications which require massive logic operations. Cube calculus operations can be implemented on conventional general-purpose computers by using the appropriate "model" and software which manipulates this model. The price that we pay for this software based approach is severe speed degradation which has made the implementation of several high-level formal systems impractical. A cube calculus machine which has a special data path designed to execute multiplevalued input, and multiple-valued output cube calculus operations is presented in this thesis. This cube calculus machine can execute cube calculus operations 10-25 times faster than the software approach. For the purpose of ensuring the manufacturing testability of the cube calculus machine, emphasize has been put on the testability design of the cube calculus machine. Testability design and testability analysis of the iterative logic unit of the cube calculus machine was accomplished. Testability design and testability analysis methods of the cube calculus machine are weli discussed in this thesis. Full-scan testability design method was used in the testability design and analysis. Using the single stuck-at fault model, a 98.30% test coverage of the cube calculus machine was achieved. A Povel testability design and testability analysis approach is also presented in this thesis.

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2

Lindström, Birgitta. "Methods for Increasing Software Testability." Thesis, University of Skövde, Department of Computer Science, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-494.

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We present a survey over current methods for improving software testability. It is a well-known fact that the cost for testing of software takes 50\% or more of the development costs. Hence, methods to improve testability, i.e. reduce the effort required for testing, have a potential to decrease the development costs. The test effort needed to reach a level of sufficient confidence for the system is dependent on the number of possible test cases, i.e., the number of possible combinations of system state and event sequences. Each such combination results in an execution order. Properties of the execution environment that affect the number of possible execution orders can therefore also affect testability. Which execution orders that are possible and not are dependent of processor scheduling and concurrency control policies. Current methods for improving testability are investigated and their properties with respect to processor scheduling and concurrency control analyzed. Especially, their impact on the number of possible test cases is discussed. The survey revealed that (i) there are few methods which explicitly address testability, and (ii) methods that concern the execution environment suggest a time-triggered design. It is previously shown that the effort to test an event-triggered real-time system is inherently higher than testing a time-triggered real-time system. Due to the dynamic nature of the event-triggered system the number of possible execution orders is high. A time-triggered design is, however, not always suitable. The survey reveals an open research area for methods concerning improvement of testability in event-triggered systems. Moreover, a survey and analysis of processor scheduling and concurrency control properties and their effect on testability is presented. Methods are classified into different categories that are shown to separate software into different levels of testability. These categories can form a basis of taxonomy for testability. Such taxonomy has a potential to be used by system designers and enable them to perform informed trade-off decisions.

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3

Shi, Cheng. "High-level design for testability." Thesis, University of Southampton, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.336135.

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4

Bhattacharyya, Arnab. "Testability of linear-invariant properties." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/68435.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 75-80).
Property Testing is the study of super-efficient algorithms that solve "approximate decision problems" with high probability. More precisely, given a property P, a testing algorithm for P is a randomized algorithm that makes a small number of queries into its input and distinguishes between whether the input satisfies P or whether the input is "far" from satisfying P, where "farness" of an object from P is measured by the minimum fraction of places in its representation that needs to be modified in order for it to satisfy P. Property testing and ideas arising from it have had significant impact on complexity theory, pseudorandomness, coding theory, computational learning theory, and extremal combinatorics. In the history of the area, a particularly important role has been played by linearinvariant properties, i.e., properties of Boolean functions on the hypercube which are closed under linear transformations of the domain. Examples of such properties include linearity, homogeneousness, Reed-Muller codes, and Fourier sparsity. In this thesis, we describe a framework that can lead to a unified analysis of the testability of all linear-invariant properties, drawing on techniques from additive combinatorics and from graph theory. We also show the first nontrivial lowerbound for the query complexity of a natural testable linear-invariant property.
by Arnab Bhattacharyya.
Ph.D.

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5

Hock, Joel M. (Joel Michael) 1977. "Exposing testability in GUI objects." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86608.

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Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
Includes bibliographical references (leaf 28).
by Joel M. Hock.
M.Eng.and S.B.

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6

Kito, Nobutaka, and Naofumi Takagi. "Level-Testability of Multi-operand Adders." IEEE, 2008. http://hdl.handle.net/2237/12025.

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7

Lindström, Birgitta. "Testability of Dynamic Real-Time Systems." Doctoral thesis, Linköpings universitet, ESLAB - Laboratoriet för inbyggda system, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16486.

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This dissertation concerns testability of event-triggered real-time systems. Real-time systems are known to be hard to test because they are required to function correct both with respect to what the system does and when it does it. An event-triggered real-time system is directly controlled by the events that occur in the environment, as opposed to a time-triggered system, which behavior with respect to when the system does something is constrained, and therefore more predictable. The focus in this dissertation is the behavior in the time domain and it is shown how testability is affected by some factors when the system is tested for timeliness. This dissertation presents a survey of research that focuses on software testability and testability of real-time systems. The survey motivates both the view of testability taken in this dissertation and the metric that is chosen to measure testability in an experiment. We define a method to generate sets of traces from a model by using a meta algorithm on top of a model checker. Defining such a method is a necessary step to perform the experiment. However, the trace sets generated by this method can also be used by test strategies that are based on orderings, for example execution orders. An experimental study is presented in detail. The experiment investigates how testability of an event-triggered real-time system is affected by some constraining properties of the execution environment. The experiment investigates the effect on testability from three different constraints regarding preemptions, observations and process instances. All of these constraints were claimed in previous work to be significant factors for the level of testability. Our results support the claim for the first two of the constraints while the third constraint shows no impact on the level of testability. Finally, this dissertation discusses the effect on the event-triggered semantics when the constraints are applied on the execution environment. The result from this discussion is that the first two constraints do not change the semantics while the third one does. This result indicates that a constraint on the number of process instances might be less useful for some event-triggered real-time systems.

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8

Yu, Hua-Long. "Testability-directed specification of communications software." Thesis, University of Ottawa (Canada), 1992. http://hdl.handle.net/10393/7560.

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In this thesis, we make a contribution to improving software testability by providing a useful model and guide-lines for constructing highly testable specifications of distributed real time (communications) systems. A global events model is developed based on relative clock for interpreting concurrent aspect of a communications system. Extended trace assertion language (ETAL) is presented for formally representing both the sequential and concurrent aspects of the system. A relative clock based specification in ETAL method also facilitates subsequent testing activity. Subsequently, based on the global events model, a new test result analysis approach including timing information is presented for communication service and protocol conformance testing. This approach is also ETAL specification-based. After the descriptions of the contributions mentioned above, the definition of a testability-directed specification and a study on the relations between the testability-directed specification and ETAL are then presented. Finally, the feasibility and usefulness of the relative clock based formal specification method is demonstrated by its application to OSI transport software (service and protocol). Also, the effectiveness of the relative clock based approach for test result analysis is illustrated in a set of realistic conformance testing examples. (Abstract shortened by UMI.)

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9

Kumar, Mahilchi Milir Vaseekar. "Testability considerations in delay fault testing /." Available to subscribers only, 2006. http://proquest.umi.com/pqdweb?did=1232421401&sid=5&Fmt=2&clientId=1509&RQT=309&VName=PQD.

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10

Al-Khanjari, Zuhoor Abdullah. "Investigations into testability and related concepts." Thesis, University of Liverpool, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.366661.

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11

Park, Byung-Goo. "A system-level testability allocation model /." free to MU campus, to others for purchase, 1997. http://wwwlib.umi.com/cr/mo/fullcit?p9842588.

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12

Malla, Prakash, and Bhupendra Gurung. "Adaptation of Software Testability Concept for Test Suite Generation : A systematic review." Thesis, Blekinge Tekniska Högskola, Sektionen för datavetenskap och kommunikation, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-4322.

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Context: Software testability, which is the degree to which a software artifact facilitates process of testing, is not only the indication of the test process effectiveness but also gives the new perspective on code development. Since more than fifty percent of total software development costs is related to testing process activities, Software testability has always been the improving area in software domain so that we can make the software development process effective with respect to test cases writing and fault detection process. Objectives: The research though this thesis will have the objective of proposing a conceptual framework considering the testability issues for the simpler test suite generation and facilitating the concerned persons with better effectiveness of testing. We investigate the testability factors and testability metrics basically with the help of the systematic literature review and the proposed framework’s feasibility is evaluated with case study. Methods: Initially, we conduct the literature review to get broad knowledge on this domain as well for the key documents. Then study starts with the systematic literature review process guided by the review protocol to collect the testability factors and measurements. The framework is validated with the case study. The research documents are included from highly trusted e-database including Compendex, Inspec, IEEE Xplore, ACM Digital Library, Springer Link and Scopus. Altogether 36 primary documents are included for the study and results are extracted. Results: From the results of systematic literature review, Software testability factors and associated measurements are found and the construction of framework for simple test generation as guidelines evaluate with case study. To make the test suite generation simpler, we propped a framework based on the FTA concepts and breakdown of high level testability factors to its simpler form of measureable level. Conclusions: Numbers of different software testability factors are presented in different researches in different perspectives. We collect important testability factors and associated measurement methods and we concluded the effect of testability in simpler test suite generation with the help of framework evaluated by case study.

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13

Li, Lin. "RF transceiver front-end design for testability." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2256.

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In this thesis, we analyze the performance of a loop-back built-in-self-test for a RF transceiver front-end. The tests aim at spot defects in a transceiver front-end and they make use of RF specifications such as NF (Noise Figure), G (power gain) and IIP3 (third order Intercept point). To enhance fault detectability, RF signal path sensitization is introduced. We use a functional RF transceiver model that is implemented in MatLab™ to verify this analysis.

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14

Gross, Hans-Gerhard. "Measuring evolutionary testability of real-time software." Thesis, University of South Wales, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.365087.

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15

Oikonomakos, Petros. "High-level synthesis for on-line testability." Thesis, University of Southampton, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.414359.

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16

Bastos, Antonio Josefran de Oliveira. "Convergent Sequences of Discrete Structures and Testability." Universidade Federal do CearÃ, 2012. http://www.teses.ufc.br/tde_busca/arquivo.php?codArquivo=7654.

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FundaÃÃo Cearense de Apoio ao Desenvolvimento Cientifico e TecnolÃgico
In this work, we studied the recent theory of convergent graph sequences and its extensions to permutation and partially ordered sets with fix dimension. Weâve conjectured a lemma of weak regularity on intervals that, if this conjecture is true, we can extend this theory to ordered graphs, which are graphs such that there is a total order on its vertices. We show some interesting relations on permutation and partially ordered sets with ordered graphs. Then, we obtain another proof to the existence of limit objects for all convergent permutation sequences. We also proved that all hereditary property of either permutation or ordered graph is testable.
Neste trabalho, estudamos a teoria recente de convergÃncia de sequÃncias de grafos e suas extensÃes para permutaÃÃes e ordens parciais de dimensÃo fixa. Conjecturamos um lema de regularidade fraca de grafos em intervalos que, se for verdadeira, nos possibilita estender essa teoria para grafos ordenados, que sÃo grafos tais que existe uma ordem total entre os vÃrtices. Mostramos algumas relaÃÃes interessantes de permutaÃÃes e ordens parciais com grafos ordenados. Com isso, conseguimos uma prova alternativa para a existÃncia de objetos limites de qualquer sequÃncia convergente de permutaÃÃes. Provamos tambÃm que toda propriedade hereditÃria de permutaÃÃes ou grafos ordenados Ã testÃvel.

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17

Larsson, Erik. "An Integrated System-Level Design for Testability Methodology." Doctoral thesis, Linköpings universitet, ESLAB - Laboratoriet för inbyggda system, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4932.

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HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems. The main objective of this thesis is to address test problems faced by the designer at the system level. Considering the testability issues at early design stages can reduce the test problems at lower abstraction levels and lead to the reduction of the total test cost. The objective is achieved by developing several new methods to help the designers to analyze the testability and improve it as well as to perform test scheduling and test access mechanism design. The developed methods have been integrated into a systematic methodology for the testing of system-on-chip. The methodology consists of several efficient techniques to support test scheduling, test access mechanism design, test set selection, test parallelization and test resource placement. An optimization strategy has also been developed which minimizes test application time and test access mechanism cost, while considering constraints on tests, power consumption and test resources. Several novel approaches to analyzing the testability of a system at behavioral level and register-transfer level have also been developed. Based on the analysis results, difficult-to-test parts of a design are identified and modified by transformations to improve testability of the whole system. Extensive experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodology and techniques. The experimental results show clearly the advantages of considering testability in the early design stages at the system level.

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18

Elbably, M. E. "On the testability and diagnosability of digital systems." Thesis, Brunel University, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.380169.

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19

Roberts, M. W. "Logic circuit testability for reconvergent fan-out nodes." Thesis, University of York, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.374197.

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20

Almajdoub, Salahuddin A. "A Design Methodology for Physical Design for Testability." Diss., Virginia Tech, 1996. http://hdl.handle.net/10919/30574.

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Physical design for testability (PDFT) is a strategy to design circuits in a way to avoid or reduce realistic physical faults. The goal of this work is to define and establish a speci c methodology for PDFT. The proposed design methodology includes techniques to reduce potential bridging faults in complementary metal-oxide-semiconductor (CMOS) circuits. To compare faults, the design process utilizes a new parameter called the fault index. The fault index for a particular fault is the probability of occurrence of the fault divided by the testability of the fault. Faults with the highest fault indices are considered the worst faults and are targeted by the PDFT design process to eliminate them or reduce their probability of occurrence. An implementation of the PDFT design process is constructed using several new tools in addition to other "off-the-shelf" tools. The first tool developed in this work is a testability measure tool for bridging faults. Two other tools are developed to eliminate or reduce the probability of occurrence of bridging faults with high fault indices. The row enhancer targets faults inside the logic elements of the circuit, while the channel enhancer targets faults inside the routing part of the circuit. To demonstrate the capabilities and test the eff ectiveness of the PDFT design process, this work conducts an experiment which includes designing three CMOS circuits from the ISCAS 1985 benchmark circuits. Several layouts are generated for every circuit. Every layout, except the rst one, utilizes information from the previous layout to minimize the probability of occurrence for faults with high fault indices. Experimental results show that the PDFT design process successfully achieves two goals of PDFT, providing layouts with fewer faults and minimizing the probability of occurrence of hard-to-test faults. Improvement in the total fault index was about 40 percent in some cases, while improvement in total critical area was about 30 percent in some cases. However, virtually all the improvements came from using the row enhancer; the channel enhancer provided only marginal improvements.
Ph. D.

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21

Albattah, Waleed. "SOFTWARE MAINTAINABILITY AND TESTABILITY PREDICTIONS USING PACKAGE COHESION." Kent State University / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=kent1415737576.

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22

Das, Debaleena. "Design-for-testability techniques for deep submicron technology /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.

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23

Sarabi, Andisheh. "Logic Synthesis with High Testability for Cellular Arrays." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4752.

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The new Field Programmable Gate Array (FPGA) technologies and their structures have opened up new approaches to logic design and synthesis. The main feature of an FPGA is an array of logic blocks surrounded by a programmable interconnection structure. Cellular FPGAs are a special class of FPGAs which are distinguished by their fine granularity and their emphasis on local cell interconnects. While these characteristics call for specialized synthesis tools, the availability of logic gates other than Boolean AND, OR and NOT in these architectures opens up new possibilities for synthesis. Among the possible realizations of Boolean functions, XOR logic is shown to be more compact than AND/OR and also highly testable. In this dissertation, the concept of structural regularity and the advantages of XOR logic are used to investigate various synthesis approaches to cellular FPGAs, which up to now have been mostly nonexistent. Universal XOR Canonical Forms, Two-level AND/XOR, restricted factorization, as well as various Directed Acyclic Graph structures are among the proposed approaches. In addition, a new comprehensive methodology for the investigation of all possible XOR canonical forms is introduced. Additionally, a new compact class of XOR-based Decision Diagrams for the representation of Boolean functions, called Kronecker Functional Decision Diagrams (KFDD), is presented. It is shown that for the standard, hard, benchmark examples, KFDDs are on average 35% more compact than Binary Decision Diagrams, with some reductions of up to 75% being observed.

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24

Karel, Amit. "Comparative Study of FinFET and FDSOI Nanometric Technologies Based on Manufacturing Defect Testability." Thesis, Montpellier, 2017. http://www.theses.fr/2017MONTS084/document.

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Deux innovations en matière de procédés technologiques des semi-conducteurs sont des alternatives à la technologie traditionnelle des transistors MOS (« Metal-Oxide-Semiconductor ») « Bulk » planaires : d’une part le silicium totalement déserté sur isolant (FDSOI – « Fully Depleted Silicon on Insulator ») et d’autre part les transistors à effet de champ à aileron (FinFET – « Fin Field Effect Transistor »). En effet, alors que la technologie « Bulk » arrive à ses limites de miniaturisation des composants et systèmes, notamment du fait de l’effet de canal court, ces deux technologies présentent des propriétés prometteuses pour poursuivre cette réduction des dimensions, grâce à un meilleur contrôle électrostatique de la grille sur le canal du transistor. La technologie FDSOI est, comme l’historique « Bulk », une technologie MOS planaire, ce qui la place naturellement davantage dans la continuité technologique que les ailerons verticaux des transistors FinFETs. La compétition entre ces deux technologies est rude et de nombreuses études publiées dans la littérature comparent ces technologies en termes de performance en vitesse de fonctionnement, de consommation, de coût, etc. Néanmoins, aucune étude ne s’était encore penchée sur leurs propriétés respectives en termes de testabilité ; pourtant l’impact de défauts sur les circuits réalisés en technologies FDSOI et FinFET est susceptible d’être significativement de celui induit par des défauts similaires sur des circuits planaires MOS.Le travail présenté dans cette thèse se concentre sur la conception de circuits d’étude similaires dans chacune des trois technologies et l’analyse comparative de leur comportement électrique sous l’effet d’un même défaut. Les défauts considérés dans notre étude sont les courts-circuits résistifs inter-portes, court-circuit résistif à la masse (GND), court-circuit résistif à l’alimentation (VDD), et circuits ouverts résistifs. La détectabilité des défauts est évaluée pour le test logique statique et le test dynamique en « délai ». Des simulations HSPICE et Cadence SPECTRE ont été effectuées en faisant varier la valeur de la résistance du défaut et le concept de résistance critique est utilisé afin de comparer la plage de détectabilité du défaut dans les différentes technologies. Les conditions optimales de polarisation du substrat (« body-biasing »), de tension d’alimentation et de température en vue d’obtenir la meilleure couverture de défauts possible sont déterminées pour chaque type de défaut. Un modèle analytique, basé sur la résistance équivalente des réseaux de transistors N et P actifs (« ON-resistance »), est proposé pour les courts-circuits résistifs, et permet d’évaluer la valeur de la résistance critique sans effectuer de simulation de fautes. Les propriétés en termes de testabilité sont également établies en tenant compte des variations de procédés, par des simulations Monte-Carlo réalisées aussi bien pour les dispositifs à tension de seuil nominale (« Regular-VT devices » : FDSOI-RVT et Bulk-LR) que pour les dispositifs à tension de seuil basse (« Low-VT devices » : FDSOI-LVT et Bulk-LL) disponibles pour les technologies 28 nm Bulk et FDSOI
Fully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are new innovations in silicon process technologies that are likely alternatives to traditional planar Bulk transistors due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better electrostatic control by the gate over the channel of the transistor. FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testability properties while the impact of defects on circuits implemented in FDSOI and FinFET technologies might be significantly different from the impact of similar defects in planar MOS circuit.The work of this thesis is focused on implementing similar design in each technology and comparing the electrical behavior of the circuit with the same defect. The defects that are considered for our investigation are inter-gate resistive bridging, resistive short to ground terminal (GND), resistive short to power supply (VDD) and resistive open defects. Defect detectability is evaluated in the context of either logic or delay based test. HSPICE and Cadence SPECTRE simulations are performed varying the value of the defect resistance and the concept of critical resistance is used to compare the defect detectability range in different technologies. The optimal body-biasing, supply voltage and temperature settings to achieve the maximum defect coverage are determined for these defect types. An analytical analysis is proposed for short defects based on the ON-resistance of P and N networks, which permits to evaluate the value of the critical resistance without performing fault simulations. Testability properties are also established under the presence of process variations based on Monte-Carlo simulations for both Regular-VT devices (FDSOI-RVT and Bulk-LR) and Low-VT devices (FDSOI-LVT and Bulk-LL) available for 28nm Bulk and FDSOI technologies

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25

Lewis, Dean Leon. "Design for pre-bond testability in 3D integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45756.

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In this dissertation we propose several DFT techniques specific to 3D stacked IC systems. The goal has explicitly been to create techniques that integrate easily with existing IC test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. First, we describe a general test architecture for 3D ICs. In this architecture, each tier of a 3D design is wrapped in test control logic that both manages tier test pre-bond and integrates the tier into the large test architecture post-bond. We describe a new kind of boundary scan to provide the necessary test control and observation of the partial circuits, and we propose a new design methodology for test hardcore that ensures both pre-bond functionality and post-bond optimality. We present the application of these techniques to the 3D-MAPS test vehicle, which has proven their effectiveness. Second, we extend these DFT techniques to circuit-partitioned designs. We find that boundary scan design is generally sufficient, but that some 3D designs require special DFT treatment. Most importantly, we demonstrate that the functional partitioning inherent in 3D design can potentially decrease the total test cost of verifying a circuit. Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm co-designs the pre-bond and post-bond wrappers to simultaneously minimize test time and routing cost. On average, our algorithm utilizes over 90% of the wires in both the pre-bond and post-bond wrappers. Finally, we look at the 3D vias themselves to develop a low-cost, high-volume pre-bond test methodology appropriate for production-level test. We describe the shorting probes methodology, wherein large test probes are used to contact multiple small 3D vias. This technique is an all-digital test method that integrates seamlessly into existing test flows. Our experimental results demonstrate two key facts: neither the large capacitance of the probe tips nor the process variation in the 3D vias and the probe tips significantly hinders the testability of the circuits. Taken together, this body of work defines a complete test methodology for testing 3D ICs pre-bond, eliminating one of the key hurdles to the commercialization of 3D technology.

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26

El-Maleh, Aiman H. "Testability preservation of combinational and sequential logic synthesis transformations." Thesis, McGill University, 1995. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29016.

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In order to reduce the test development cost and guarantee testable designs, it is essential to have synthesis transformations that are testability and test-set preserving. In this thesis, we study testability preservation of transformations that form the basis of existing state-of-the-art logic synthesis and optimization techniques.
We show that the concurrent decomposition and factorization transformations, except dual-extraction of multiplexor structures, preserve testablility and test-set under several testing constraints. Furthermore, we provide sufficient conditions for test-set preservation under the algebraic resubstitution with complement transformation that cover a larger class of complementary expressions than was known previously. Experimental results show that dual-extraction of multiplexor structures is utilized in only 2 out of 50 benchmark circuits. We demonstrate that while disabling this transformation has negligible effect on area, it results in an efficient test-set preserving multilevel logic synthesis algorithm.
Recently, it has been shown that retiming has a very strong impact on the run time of sequential, structural automatic test pattern generators (ATPGs), as well as the levels of fault coverage and fault efficiency attained. We show that retiming preserves testability with respect to a single stuck-at fault test set by adding a prefix sequence of a pre-determined number of arbitrary input vectors. Furthermore, we show that a new circuit attribute, termed density of encoding, is the main reason for high test generation time. We also propose a novel approach for reducing test pattern generation cost based on test-set preserving transformations. Experimental results show that high fault coverages can be achieved on high performance circuits optimized by retiming with a much less CPU time (a reduction of two orders of magnitude in several instances) than if ATPG is attempted directly on those circuits.

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27

Miles, J. R. "Cost modelling for VLSI circuit conversion to aid testability." Thesis, Brunel University, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.383718.

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28

Rahagude, Nikhil Prakash. "Integrated Enhancement of Testability and Diagnosability for Digital Circuits." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/35609.

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While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid silicon diagnosis. In this thesis, test point insertions are conducted with the aim to detect more faults and also synergistically distinguish currently indistinguishable fault-pairs. We achieve this by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, we propose a novel low-cost metric to identify such TD points. Further, we propose a new DFT + DFD architecture, which adds just one pin (to identify test/functional mode) and small additional combinational logic to the circuit under test. Our experiments indicate that the proposed architecture can distinguish 4x more previously indistinguishable fault-pairs than existing DFT architectures while maintaining similar fault coverages. Further, the experiments illustrate that quality results can be achieved with an area overhead of around 5%. Additional experiments conducted on hard-to-test circuits show an increase in fault coverage by 48% while maintaining similar diagnostic resolution. Built-in Self Test (BIST) is a technique of adding additional blocks of hardware to the circuits to allow them to perform self-testing. This enables the circuits to test themselves thereby reducing the dependency on the expensive external automated test equipment (ATE). At the end of a test session, BIST generates a signature which is a compaction of the obtained output responses of the circuit for that session. Comparison of this signature with the reference signature categorizes the circuit as error free or buggy. While BIST provides a quick and low cost alternative to check circuit's correctness, diagnosis in BIST environment remains poor because of the limited information present in the lossily compacted final signature. The signature does not give any information about the possible defect location in the circuit. To facilitate diagnosis, researchers have proposed the use of two additional on-chip embedded memories,response memory to store reference responses and fail memory to store failing responses. We propose a novel architecture in which only one additional memory is required. Experimental results conducted on benchmark circuits substantiate that the same fault coverage can be maintained using just 5% of the available test vectors. This reduces the size of memory required to store responses which in turn reduces area overhead. Further, by adding test points to the circuit using our proposed architecture, we can improve the diagnostic resolution by 60% with respect to external testing.
Master of Science

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29

Donglikar, Swapneel B. "Design for Testability Techniques to Optimize VLSI Test Cost." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/43712.

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High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test data volume and test application time. The degree of test data volume reduction depends on the fault coverage achievable in the broadcast mode. However, the fault coverage achieved in the broadcast mode of ILS architecture depends on the actual configuration of individual scan chains, i.e., the number of chains and the mapping of the individual flip-flops of the circuit to the respective scan chain positions. Current methods for constructing scan chains in ILS are either ad-hoc or use test pattern information from an a-priori automatic test pattern generation (ATPG) run. In this thesis, we present novel low cost techniques to construct ILS scan configuration for a given design. These techniques efficiently utilize the circuit topology information and try to optimize the flip-flop assignment to a scan chain location without much compromise in the fault coverage in the broadcast mode. Thus, they eliminate the need of an a-priori ATPG run or any test set information. In addition, we also propose a new scan architecture which combines the broadcast mode of ILS and Random Access Scan architecture to enable further test volume reduction on and above effectively configured conventional ILS architecture using the aforementioned heuristics with reasonable area overhead. Experimental results on the ISCASâ 89 benchmark circuits show that the proposed ILS configuration methods can achieve on an average 5% more fault coverage in the broadcast mode and on average 15% more test data volume and test application time reduction than existing methods. The proposed new architecture achieves, on an average, 9% and 33% additional test data volume and test application time reduction respectively on top of our proposed ILS configuration heuristics.
Master of Science

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30

Rockliff, John E. "The implementation of testability strategies in a VLSI circuit /." Title page, contents and abstract only, 1986. http://web4.library.adelaide.edu.au/theses/09ENS/09ensr683.pdf.

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31

Taylor, David. "Design of certain silicon semi-customised structures incorporating self-test." Thesis, University of Huddersfield, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.329218.

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32

Birgisson, Ragnar. "Improving Testability of Applications in Active Real-Time Database Environments." Thesis, University of Skövde, Department of Computer Science, 1998. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-226.

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The test effort required to achieve full test coverage of an event-trigered real-time system is very high. In this dissertation, we investigate a method for reducing this effort by constraining behavior of the system. We focus on system level testing of applications with respect to timeliness. Our approach is to define a model for constraining real-time systems to improve testability. Using this model applicability of our constraints is easily determined because all the pertinent assumptions are clearly stated. We perform a validation of a test effort upper bound for event-triggered real-time systems with respect to this model. Effects that constraints for improving testability have on predictability, efficiency, and scheduling are investigated and validated. Specific design guidelines for selection of appropriate constraint values are presented in this work. Finally, we discuss mechanisms for handling constraint violations.

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Vermaak, Hermanus Jacobus. "Design-for-delay-testability techniques for high-speed digital circuits." Enschede : University of Twente [Host], 2005. http://doc.utwente.nl/57440.

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34

Jagadeesh, Vasudevamurthy. "On the testability-preserving decomposition and factorization of Boolean expressions." Thesis, McGill University, 1991. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=74653.

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This thesis presents a new concurrent method for the decomposition and factorization of Boolean expressions based on two simple objects: two-literal single-cube divisors, and double-cube divisors along with their complements. It is proved that the presence of common multiple-cube algebraic divisors, from a set of Boolean expressions, can be found by analyzing the set of double-cube divisors. It is also shown that in order to find the duality relations that may exist between various objects, only a subset of two-literal single-cube and double-cube divisors needs to be analyzed. Since the number of these objects grows polynomially with the size of the network, the number of objects that are to be analyzed for finding common algebraic divisors, and for finding the duality relations between them, is much less than the set of all algebraic divisors. Also, since the duality relations between these objects are exploited along with DeMorgan's laws, these objects constitute a richer set of divisors than the strictly algebraic divisors.
It is also proved that the transformations based on these simple objects preserve testability. This result implies that if the input Boolean network before decomposition and factorization is 100% testable for single stuck-at faults by a test set T, then the area optimized output network will also be 100% testable for single stuck-at faults, and can be tested by the same test set T. These results are proved using the concepts of corresponding faults in the circuits and relations between complete test sets. Since the method assumes that the initial network is only single stuck-at fault testable, and because single stuck-at fault testability is maintained through the transformations, the method can be applied to a large class of irredundant two-level and multi-level circuits to synthesize fully testable circuits.
Experimental results are presented and compared with various logic synthesis systems to demonstrate the efficiency and effectiveness of the method.

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35

Khomentrakarn, Chusak. "Testability analysis of asynchronous circuits designed from signal transition graphs." Thesis, McGill University, 1995. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=22657.

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This work investigates testability of asynchronous circuits and its relation with signal transition graphs (STGs), using a state based approach on non-scan asynchronous circuits. In addition to the testability characteristics studied, this work suggests some test generation techniques for asynchronous circuits designed from STGS.
An event fault, interpreted as either a stimulating fault or an inhibiting fault of a transition, is used to cover the stuck-at-fault (SAF) behavior of an asynchronous circuit. An advantage of such analysis is that test vectors for an inhibiting fault can be obtained from operations on a signal transition graph (STG) or a state graph (SG) rather than simulation at the circuit level. A test vector for a test state is represented in an STG by a test marking for each event fault.
The lock relation of signals is a property proposed for hazard-free asynchronous circuit's synthesis. However, it is found that there is a special case of the lock relation that can prohibit the testing of some faults, the introduction of which cannot be avoided by the circuit level mapping. Some independent undetectable faults due to uncontrollable test states however can be detected if the reset state is the test state.
Using a minimized two-level sum-of-products representation, each literal in a cube of the sum-of-products form is found to have its own function corresponding to the STG. Consequently, four types of literals are defined and their relations with the SAF behavior over the stimulating/inhibiting fault are analyzed. Although factorization of a logic equation binded to a C-element or a set-reset (SR) flip-flop is not always possible, a correct implementation on a set-dominant SR flip-flop is guaranteed. (Abstract shortened by UMI.)

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36

Platino, Vincenzo. "Existence, regularity and testability results in economic models with externalities." Doctoral thesis, Universita degli studi di Salerno, 2012. http://hdl.handle.net/10556/1312.

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2008 - 2009
This thesis deals with economic models in the presence of externalities. The thesis consists of three chapters. In chapter 1, we consider a general model of production economies with consumption and production externalities. That is, the choices of all agents (households and firms) affect individual consumption sets, individual preferences and production technologies. Describing equlibria in terms of first order conditions and market clearing conditions, and using a homotopy, under differentiability and boundary conditions, we prove the non-emptiness and compactness of the set of competitive equilibria with consumptions and prices strictly positive. In chapter 2 we consider a general model of private ownership economies with consumption and production externalities. Showing by an example that basic assumptions are not enough to guarantee a regularity result in the space of initial endowments, we provide sufficient conditions for the regularity in the space of endowments and transformation functions. In chapter 3 we study the testability implications of public versus private consumption in collective models of group consumption. To the contrary at the previous literature, we find that assumptions regarding the public or private nature of specific goods do have testability implications, even if one only observes the aggregate group consumption. In fact, these testability implications apply as soon as the analysis includes three goods and four observations. In our opinion, our revealed preference approach obtains stronger testability conclusions because it focuses on conditions which involve personalized prices and personalized quantities, although we do not require that personalized prices and personalized quantities are observable. [edited by author]
VIII n.s.

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37

Ramzan, Rashad. "Flexible Wireless Receivers: On-Chip Testing Techniques and Design for Testability." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18208.

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In recent years the interest in the design of low cost multistandard mobile devices has gone from technical aspiration to the commercial reality. Usually, the emerging wireless applications prompt the conception of new wireless standards. The end user wants to access voice, data, and streaming media using a single wireless terminal. In RF perspective, these standards differ in frequency band, sensitivity, data rate, bandwidth, and modulation type. Therefore, a flexible multistandard radio receiver covering most of the cellular, WLAN, and short range communication standards in 800MHz to 6GHz band is highly desired. To keep the cost low, high level of integration becomes a necessity for the multistandard flexible radio. Due to aggressive CMOS scaling the fT of the transistors has surpassed the value of 200 GHz. Moreover, as the CMOS technology has proven to be the best suited for monolithic integration, therefore it seems to be the future choice for the physical implementation of such a flexible receiver. In this thesis, two multiband sampling radio receiver front-ends implemented in 130 nm and 90 nm CMOS including test circuitry (DfT) are presented that is one step ahead in this direction. In modern radio transceivers the estimated cost of testing is a significant portion of manufacturing cost and is escalating with every new generation of RF chips. In order to reduce the test cost it is important to identify the faulty circuits very early in the design flow, even before packaging. In this thesis, on-chip testing techniques to reduce the test time and cost are presented. For integrated RF transceivers the chip reconfiguration by loopback setup can be used. Variants including the bypassing technique to improve testability and to enable on-chip test when the direct loopback is not feasible are presented. A technique for boosting the testability by the elevated symbol error rate test (SER) is also presented. It achieves better sensitivity and shorter test time compared to the standard SER test. Practical DfT implementation is addressed by circuit level design of various test blocks such as a linear attenuator, stimulus generator, and RF detectors embedded in RF chips without notable performance penalty. The down side of CMOS scaling is the increase in parameter variability due to process variations and mismatch. Both the test circuitry (DfT) and the circuit under test (CUT) are affected by these variations. A new calibration scheme for the test circuitry to compensate this effect is presented. On-chip DC measurements supported by a statistical regression method are used for this purpose. Wideband low-reflection PCB transmission lines are needed to enable the functional RF testing using external signal generators for RF chips directly bonded on the PCB. Due to extremely small chip dimensions it is not possible to layout the transmission line without width discontinuity. A step change in the substrate thickness is utilized to cancel this effect thus resulting in the low-reflection transmission line. In summary, all of these techniques at the system and circuit level pave a way to new opportunities towards low-cost transceiver testing, especially in volume production.

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38

Zhou, Qing. "Test support processor for enhanced testability of high performance integrated circuits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13010.

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39

Ramzan, Rashad M. "Flexible wireless receivers : on-chip testing techniques and design for testability /." Linköping : Department of of Electrical Engineering, Linköping University, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18208.

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40

Ho, Chung Kin. "Fault diagnosis and design for testability applied to analogue integrated circuits." Thesis, University of Bath, 1998. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.242531.

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41

Survila, Vytautas. "Abstrakčių automatų valdomumo tyrimo programinė įranga." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2005. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2005~D_20050527_201609-31343.

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One of possible expenditures of reduction and testability process acceleration choices is to increase circuit’s testability. It means to increase controllability and observability of the circuit. As to determine the circuit’s controllability and observability manually takes lots of time, it is meaningful to automate this process. The main purpose is to determine and improve the controllability of the circuit by offering some suggestions to system on chip’s designers how to improve circuit’s controllability. We try to analyze if it is possible to do this only by using created software. This software’s architecture uses client-server mode and all computations are performed on a server side. The system is realized on Apache server with Linux OS. System modules are realized using C++, PHP, JAVA, HTML and JavaScript programming languages. In this paper it is being introduced the definition of controllability, explored methods of controllability estimation and increase. Also there is introduced the research how to improve accuracy of software results. The methods of the controllability estimation for “white box” are modified to work with “black box”. Assumptions made during the research were validated by experiments.

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42

Chiang, Kang-Chung. "Scan path design of PLA to improve its testability in VLSI realization." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183128113.

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43

CHEN, JIN-ZHUO, and 陳勁卓. "Testability design rule checker." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/14271064470504656602.

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44

Huang, Yun-Xi, and 黃允熙. "A functional level testability measure." Thesis, 1991. http://ndltd.ncl.edu.tw/handle/50702886131311401758.

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45

Nahvi, Mohsen. "Testability infrastructure for Systems-on-Chip." Thesis, 2004. http://hdl.handle.net/2429/16116.

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Relying on external automatic test equipment (ATE) resources is insufficient for the new paradigm of billion-transistor core-based System-on-Chip (SoC) designs. Embedded testers that take over some functionality of these ATEs are increasingly deemed essential. To achieve high-quality test and reduce cost, these embedded infrastructures need to perform deterministic tests and exploit the advantages of automatic test pattern generation (ATPG) test vector sets. This thesis proposes an embedded testing infrastructure that leverages the potentials of the classical embedded testing in the form of Built-in Self-Test (BIST). However, unlike BIST, the methodology of this thesis is based on the conventional scan/ATPG approach. This novel methodology partitions test resources to embed the test application and test results analysis on-chip while keeping the ATPG test vector files off-chip. The proposed infrastructure was implemented on silicon and experimental area and test time results are reported. Using the methodology of this thesis, a high-quality deterministic test, with reduced overall test time through ideal multi-site testing, can be achieved. Modular, flexible, and systematic test architectures are also deemed essential in SoC tests. The conventional testing paradigm requires a direct connection between a tester and the circuit under test (CUT). This arrangement undermines the modularity in the test architecture by tightly coupling its elements. This thesis proposes to de-couple test data processing and communication to lower test cost. To that end, a novel systematic and indirect test architecture that is based on network-oriented protocols is proposed. In this new architecture, test stimuli and expected results for digital cores are formatted into new protocols and then encapsulated into packets. These packets are augmented with control and address bits allowing them to be autonomously transmitted to their destination through a switching infrastructure. Finally, embedded autonomous blocks at each core are used for applying the test and comparing the results. In this way, the methodology of this thesis facilitates test cycle automation and eliminates the need for control lines. This results in better utilisation of available resources. A first implementation of this new architecture and its area and test time impact are presented.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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46

Wu, Peng. "Test Generation Guided Design for Testability." 1988. http://hdl.handle.net/1721.1/6837.

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This thesis presents a new approach to building a design for testability (DFT) system. The system takes a digital circuit description, finds out the problems in testing it, and suggests circuit modifications to correct those problems. The key contributions of the thesis research are (1) setting design for testability in the context of test generation (TG), (2) using failures during FG to focus on testability problems, and (3) relating circuit modifications directly to the failures. A natural functionality set is used to represent the maximum functionalities that a component can have. The current implementation has only primitive domain knowledge and needs other work as well. However, armed with the knowledge of TG, it has already demonstrated its ability and produced some interesting results on a simple microprocessor.

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47

Yin-He, Su, and 蘇胤合. "Novel Techniques for Improving Testability Analysis." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/28209401642066487421.

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碩士
國立中正大學
資訊工程研究所
88
The purpose of a testability analysis program is to estimate the difficulties of testing a fault. A good measurement can give an early warning about the testing problem so as to provide guidance in improving the testability of a circuit. There have been researches attempting to efficiently compute the testability analysis. Among those, the Controllability and Observability Procedure COP [4] can calculate the testability value of a stuck-at fault efficiently in a tree-structured circuit but may be very inaccurate for a general circuit. The inaccuracy in COP is due to the ignorance of signal correlations. Recently, the algorithm of TAIR in [7] proposes a testability analysis algorithm, which starts from the result of COP and then gradually improves the result by applying a set of rules. The set of rules in TAIR can capture some signal correlations and therefore the results of TAIR are more accurate than COP. In this paper, we first prove that the rules in TAIR can be replaced by a closed-form formulation. Then, based on the closed-form formulation, we proposed two novel techniques to further improve the testability analysis results. Our experimental results have shown the improvement over the results of TAIR.

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Lee, Yung-Chang, and 李勇璋. "Circuit Rewiring and Random Pattern Testability." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/53949656151461421585.

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碩士
國立中正大學
資訊工程學系
85
This thesis presents a circuit testability and fault coverage improvement methodby using circuit rewiring. This method is achieved by removing redundant wires in a circuit to increase the circuit testability. The testability is measuredby controllability and observability, and is determined by the strcuture ofa design. Our algorithm applies the reasoning of automatic test pattern generation (ATPG) which can detect redundancy efficiency. The reasoning ismainly based on mandatory assignments that are assignments which must be satisfied. Our experimental results show that the circuit testability and thefault coverage are both improved by removing redundant wires in a circuit.

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LIN, SZU-WEN, and 林思雯. "A MODEL OF SOFTWARE TESTABILITY MEASUREMENT." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/17287977979172002186.

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碩士
大同工學院
資訊工程學系
84
Software testability is becoming an important factor to be considered during software development and assessment, especailly for those criticalsoftwares. This measurement which is done before random black-box testingwith repect to a simulated input distribution. We also compared our mea-surement results with the one simulated by Voas model. It showed that our testability estimation provides enough information and will be used as guidelines for software development.

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50

Loureiro, Antonio Alfredo Ferreira. "Design for testability of communication protocols." Thesis, 1995. http://hdl.handle.net/2429/4776.

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There is growing consensus that some design principles are needed to overcome the ever increasing complexity in verifying and testing software in order to build more reliable systems. Design for testability (DFT) is the process of applying techniques and methods during the design phase in order to reduce the effort and cost in testing its implementations. In this thesis, the problem of design for testability of communication protocols is studied. A framework that provides a general treatment to the problem of designing communication protocols with testability in mind and some basic design principles are presented. Following the protocol engineering life cycle we have identified and discussed in detail issues related to design for testability in the analysis, design, implementation, and testing phases. We discuss two important aspects that affect the testing of communication protocols: testing taking the environment into consideration and distributed testing. We present a novel algorithm and the corresponding design principles for tackling an important class of faults caused by an unreliable environment, namely coordination loss, that are very difficult to catch in the testing process. These design principles can be applied systematically in the design of self-stabilizing protocols. We show that conformance relations that are environment independent are not adequate to deal with errors caused by the environment such as coordination loss. A more realistic conformance relation based on external behavior as well as a "more testable" relation for environments which exhibit coordination loss are introduced. We also present a novel algorithm and the corresponding design principles for checking dynamic unstable properties during the testing process. The method proposed can be used in distributed testing of communication protocols and distributed programs in general. This technique can also be used in normal execution of the protocol implementation to tackle the problems of state build-up and exception handling when a fault is detected. A specific type of communication protocol, namely 3-way handshake protocols, is used to show it is possible to check general properties using this algorithm. A comprehensive survey of testability and design for testability in the software domain is also included in the thesis.

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