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Dissertations / Theses on the topic 'Testing of Digital Circuits'
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1
Damianos, J. "Testing hybrid circuits using digital techniques." Thesis, University of Southampton, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.483107.
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Maiuri, Ovidio V. "Testing of digital CMOS integrated circuits : the multidimensional testing paradigm." Thesis, University of Oxford, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299132.
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Shi, Junhao. "Boolean techniques in testing of digital circuits." [S.l.] : [s.n.], 2006. http://deposit.ddb.de/cgi-bin/dokserv?idn=98361816X.
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Joseph, Arun Antony. "Defect-based testing of LTS digital circuits." Enschede : University of Twente [Host], 2006. http://doc.utwente.nl/57765.
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Yogi, Nitin Agrawal Vishwani D. "Spectral methods for testing of digital circuits." Auburn, Ala, 2009. http://hdl.handle.net/10415/1750.
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Bekheit, Mahmoud A. M. "Digital testing of analogue systems." Thesis, University of Strathclyde, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.275164.
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Park, Intaik. "Fault properties and their uses in testing digital integrated circuits /." May be available electronically:, 2009. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
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Kelly, Richard Thevenet. "DETERMINING COST EFFECTIVE TEST FLOWS FOR DIGITAL PRINTED CIRCUIT BOARDS." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275385.
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Patel, Mayank Raman. "HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275246.
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Pant, Pankaj. "Automated diagnosis of path delay faults in digital integrated circuits." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13556.
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Alani, Alaa Fadhil. "A steady-state response test generation technique for mixed-signal integrated circuits." Thesis, Brunel University, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.316941.
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Lima, José Erick de Souza. "Sistema integrado para caracterização automática de conversores analógico-digitais." [s.n.], 2010. http://repositorio.unicamp.br/jspui/handle/REPOSIP/262025.
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Orientador: Carlos Alberto dos Reis Filho<br>Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação<br>Made available in DSpace on 2018-08-16T07:16:47Z (GMT). No. of bitstreams: 1
Lima_JoseErickdeSouza_M.pdf: 6787187 bytes, checksum: 105b3b5aec8638e48cd17d79b4962b1d (MD5)
Previous issue date: 2010<br>Resumo: Este trabalho descreve um sistema constituído de diversos instrumentos, que se encontram interligados e gerenciados por um aplicativo de software, implementando um ambiente compacto para a caracterização de conversores analógico-digitais, de acordo com os procedimentos descritos nas normas IEEE 1057-1994 e IEEE 1241-2000. O sistema desenvolvido possui limitações quanto aos tipos de conversores analógico-digitais que podem ser testados, devidas às restrições impostas pelos equipamentos disponíveis neste momento. Sua estrutura, no entanto, foi concebida para permitir a expansão destes limites com a troca dos instrumentos limitantes à medida que estes forem adquiridos. A avaliação da sua funcionalidade foi realizada testando dois conversores analógico-digitais que têm características distintas. Enquanto um dos dispositivos testados tem resolução nominal de 10 bits e taxa de conversão de 80 MSPS, o outro tem resolução de 8 bits e taxa de conversão nominal de 8kSPS. A motivação para o desenvolvimento deste sistema está no projeto de conversores analógico-digitais integrados que se encontra em andamento no LPM-FEEC-Unicamp. A disponibilidade de um ambiente de teste com as propriedades do sistema desenvolvido é um requisito importante para o sucesso do projeto, pois viabiliza a verificação imediata dos circuitos construídos, reduzindo o tempo de convergência às metas do projeto<br>Abstract: This paper describes a system composed of various instruments, which are interconnected and managed by a software application, implementing a compact environment for characterization of analog-digital converters, according to the procedures described in IEEE 1057-1994 and IEEE 1241 -2000. The developed system has limitations on the kinds of analog-digital converters that can be tested due to restrictions imposed by the equipment available at the moment. Its structure, however, was designed to allow the expansion of these limits with the exchange of the limiting instruments as they are acquired. The evaluation of its functionality was performed by testing two analog-digital converters that have distinct characteristics. While one of the tested devices has nominal resolution of 10 bits and conversion rate of 80 MSPS, the other has 8-bit resolution and conversion rate four orders of magnitude below. The motivation for developing this system is the design of integrated analog-digital converters that is being carried on at the LPM-FEEC-Unicamp. The availability of a test environment with the properties of the developed system is an important requisite for the success of the project because it enables the immediate verification of the constructed circuits, thus reducing the convergence time to the project goals<br>Mestrado<br>Eletrônica, Microeletrônica e Optoeletrônica<br>Mestre em Engenharia Elétrica
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Korhonen, E. (Esa). "On-chip testing of A/D and D/A converters:static linearity testing without statistically known stimulus." Doctoral thesis, University of Oulu, 2010. http://urn.fi/urn:isbn:9789514263064.
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The static linearity testing of analog-to-digital and digital-to-analog converters (ADCs and DACs) has traditionally required test instruments with higher linearity and resolution than that of the device under test. In this thesis ways to test converters without expensive precision instruments are studied. A novel calculation algorithm for the ADC differential non-linearity (DNL) and integral non-linearity (INL) estimation is proposed. The algorithm assumes that two stimuli with constant offset between them are applied to the ADC under test and that the code density histograms for both stimuli are recorded. The probability density function (PDF) of the stimulus is then solved using simple calculations so that DNL and INL of the ADC can be estimated without a priori known stimuli. If a DAC is used to generate the stimulus to ADC, all inputs and outputs are digital and the new algorithm can be used to obtain the PDF of the DAC output. Moreover, the PDF of DAC actually characterizes its INL and DNL so that this all-digital test configuration enables a simultaneous testing of both converters thanks to the new algorithm.
The proposed algorithm is analyzed thoroughly both mathematically and by carrying out several simulations and experimental tests. On the basis of the analysis it is possible to approximate the impending estimation error and select the optimal value for the offset between the stimuli. In theory, the accuracy of the algorithm proposed equals that of the standard histogram method with ideal stimulus, but in practice, the accuracy is limited by that of the offset between the stimuli. Therefore, special attention is paid to development of an accurate and small offset generator which enables ratiometric test setup and solves the problems in the case of reference voltage drift. The proposed on-chip offset generator is built using only four resistors and switches. It occupies 122·22 μm2 in a 130 nm CMOS process and accuracy is appropriate for the INL testing of 12-bit converters from rail-to-rail. Based on the analysis of the influence of resistor non-linearity on the accuracy of offset, it is possible to improve the offset generator further. With discrete resistors, the INL of 16-bit ADCs was tested using a 12-bit signal generator.
The proposed simple algorithm and tiny offset generator are considered to be important steps towards built-in DNL and INL testing of ADCs and DACs.
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Cosgrove, S. J. "Expert system technology applied to the testing of complex digital electronic architectures : TEXAS; a synergistic test strategy planning and functional test pattern generation methodology applicable to the design, development and testing of complex digit." Thesis, Brunel University, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234077.
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Neuberger, Gustavo. "Protecting digital circuits against hold time violations due to process variations." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/12924.
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Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado.<br>With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.
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Sarmiento, Leon Mayra Susana. "Testing platform implementation and system integration for an active/passive imager system including readout circuit design." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file 5.32 Mb., 170 p, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&res_dat=xri:pqdiss&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:3220740.
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Mozaffari, Mojaveri Seyed Nima. "DESIGN AND TEST OF DIGITAL CIRCUITS AND SYSTEMS USING CMOS AND EMERGING RESISTIVE DEVICES." OpenSIUC, 2018. https://opensiuc.lib.siu.edu/dissertations/1526.
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The memristor is an emerging nano-device. Low power operation, high density, scalability, non-volatility, and compatibility with CMOS Technology have made it a promising technology for memory, Boolean implementation, computing, and logic systems. This dissertation focuses on testing and design of such applications. In particular, we investigate on testing of memristor-based memories, design of memristive implementation of Boolean functions, and reliability and design of neuromorphic computing such as neural network. In addition, we show how to modify threshold logic gates to implement more functions. Although memristor is a promising emerging technology but is prone to defects due to uncertainties in nanoscale fabrication. Fast March tests are proposed in Chapter 2 that benefit from fast write operations. The test application time is reduced significantly while simultaneously reducing the average test energy per cell. Experimental evaluation in 45 nm technology show a speed-up of approximately 70% with a decrease in energy by approximately 40%. DfT schemes are proposed to implement the new test methods. In Chapter 3, an Integer Linear Programming based framework to identify current-mode threshold logic functions is presented. It is shown that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of existing threshold functions is reduced when comparing to the traditional CMOS-based threshold logic implementation. In Chapter 4, a new method to implement threshold logic functions using memristors is presented. This method benefits from the high range of memristor’s resistivity which is used to define different weight values, and reduces significantly the transistor count. The proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45 nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption. Finally, Chapter 5 focuses on current-based designs for neural networks. CMOS aging impacts the total synaptic current and this impacts the accuracy. Chapter 5 introduces an enhanced memristive crossbar array (MCA) based analog neural network architecture to improve reliability due to the aging effect. A built-in current-based calibration circuit is introduced to restore the total synaptic current. The calibration circuit is a current sensor that receives the ideal reference current for non-aged column and restores the reduced sensed current at each column to the ideal value. Experimental results show that the proposed approach restores the currents with less than 1% precision, and the area overhead is negligible.
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Gupta, Anil K. "Functional fault modeling and test vector development for VLSI systems." Thesis, Virginia Polytechnic Institute and State University, 1985. http://hdl.handle.net/10919/90932.
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The attempts at classification of functional faults in VLSI chips have not been very successful in the past. The problem is blown out of proportions because methods used for testing have not evolved at the same pace as the technology. The fault-models proposed for LSI systems are no longer capable of testing VLSI devices efficiently. Thus the stuck-at and short/open fault models are outdated. Despite this fact, these old models are used in the industry with some modifications. Also, these gate-level fault models are very time-consuming and costly to run on the mainframe computers.
In this thesis, a new method is developed for fault modeling at the functional level. This new method called 'Model Perturbation' is shown to be very simple and viable for automation. Some general sets of rules are established for fault selection and insertion. Based on the functional fault model introduced, a method of test vector development is formulated. Finally, the results obtained from functional fault simulation are related to gate level coverage.
The validity and simplicity of using these models for combinational and sequential VLSI circuits is discussed. As an example, the modeling of IBM's AMAC chip, the work on which was done under contract YD 190121, is described.<br>M.S.
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Davis, Justin S. "An FPGA-based digital logic core for ATE support and embedded test applications." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15639.
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Elbably, M. E. "On the testability and diagnosability of digital systems." Thesis, Brunel University, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.380169.
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MELE, Santino. "A SAT based test generation method for delay fault testing of macro based circuits." Doctoral thesis, Università degli studi di Ferrara, 2010. http://hdl.handle.net/11392/2388685.
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Delay fault testing and at-speed testing are widely used to verify the
timing of synchronous digital IC’s. The importance of these techniques is
still growing because of the relevant IC’s parameters uncertainties which
characterize the current technologies.
In order to drive this process, several fault models and test generation
techniques have been developed that target different trade-offs between accuracy
and efficiency.
The largest fraction of these approaches is based upon gate level descriptions
of the circuit. In case the basic building blocks are more complex
than logic gates and their implementation is not known, functional level approaches
have been proposed. For instance, this is the case for look-up tables
based Field Programmable Gate Arrays (FPGAs) and it may be a perspective
for deep submicron circuits that exploit logic bricks as basic building
blocks. This class of circuits has been referred to as macro or module based.
In this context, the main activities performed during the tree years of
my PhD are related to the timing failures problems in module-based CMOS
VLSI circuits.
The attention to module-based (or block-based) circuits follows the current
VLSI physical design trends that attempt to limit the parametric failures
due to the scaling of technology toward nanometric feature sizes. In
such technologies, in fact, the traditional design paradigms that are based on
small (i.e gate level) cells may produce high levels of variability, thus resulting
in parametric defects. The use of highly regular cell structures, called
logic bricks has been proposed to solve these problems thus increasing the
yield of VLSI circuits. A brick comprises a logic function created from a
small set of logic primitives that are mapped on to a micro-regular fabric.
Such logic function is typically more complex that those implemented in traditional VLSI libraries.
Field Programmable Gate Array (FPGA) technology also exploits a module
based design approach. Unlike logic bricks, FPGAs are completely programmable,
because they are based on look up tables (a n-bit LUT can
accomplish every n-bit function), but the drawback is related to the implementation
of the LUT, that is unknown to designer and not optimized for
regularity.
In this scenario, the delay fault testing became a big issue, since it is
very difficult to study a circuit built using modules whose implementation
in not known, either for technological and for intellectual property reasons.
Moreover, the aggressive timing policies used in today’s ICs make the need
for delay fault testing more relevant.
The main PhD activity, that will be explained in detail in this thesis, is
related to a new method that we propose to generate test vectors for path
delay faults in circuits based on modules.
In particular, we consider the single path delay fault model in combinational
circuits or in (enhanced) full-scan ones that are composed of functional
blocks whose implementation is not known. In such circuits a path fault is
detected by suitable conditions so that a test pair is able to propagate a
transition through the path under test, in order to detect a path delay fault.
In order to identify such conditions, we introduced a new signal representation
that enables the use of boolean differential calculus. Also, additional
conditions to prevent invalidation of tests by hazards have been identified.
We suppose that the dynamic behavior of the block is modeled using
input delays such as in the timing arc delay model. We target simple combinational
blocks such as logic bricks, that are expected to present up to
8-10 inputs and a low logic depth. The used method is scalable, to generate
conditions for path delay fault tests also at gate level.
In order to assess the feasibility of the proposed approach, I realized a
software, written in C/C++, that permits to find out robust and non-robust
test pairs, starting from the BLIF description of a module based circuit. Such
a software uses a BDD description of the blocks’ functions on which we apply
Boolean Differences to obtain local sensitization conditions at module level.
Since there are circuits whose BDD structure may be very large and it may
be inefficient (in some cases also infeasible) to treat it, we translate functions
obtained at macros level to a CNF description. After that, a SAT solver generates the test pairs at circuit level starting from the conjunction of all
the CNF functions.
The software tool was used to verify the proposed approach on a set of
benchmarks (both combinational or full-scan) from ITC’99 and ISCAS’85
sets. Such benchmarks allowed to show the feasibility of the proposed approach,
although they are not fully representative of the target circuits for
which the method was developed.
Another significant work, carried out during my PhD period, also deal
with testing of macro-based circuits, but it concerns specifically logic bricks.
In particular, a method for high quality functional fault simulation and
test generation for such circuits was conceived and a software tool that
implements it was developed.
For both the approaches, results showed the feasibility of them, but also
highlighted possibilities to improve and extend the work done.
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Safi-Harab, Mouna. "A time-based approach for multi-GHz embedded mixed-signal characterization and measurement /." Thesis, McGill University, 2006. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=103032.
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The increasingly more sophisticated systems that are nowadays implemented on a single chip are placing stringent requirements on the test industry. New test strategies, equipment, and methodologies need to be developed to sustain the constant increase in demand for consumer and communication electronics. Techniques for built-in-self-test (BIST) and design-for-test (DFT) strategies have been proven to offer more feasible and economical testing solutions.<br>Previous works have been conducted to perform on-chip testing, characterization, and measurement of signals and components. The current thesis advances those techniques on many levels. In terms of performance, an increase of more than an order of magnitude in speed is achieved. 70-GHz (effective sampling) on-chip oscilloscope is reported, compared to 4-GHz and 10-GHz ones in previous state-of-the-art implementations. Power dissipation is another area where the proposed work offer a superior solution compared to previous alternatives. All the proposed circuits do not exceed a few milliWatts of power dissipation, while performing multi-GHz high-speed signal capture at a medium resolution. Finally, and possibly most importantly, all the proposed circuits for test rely on a different form of signal processing; the time-based approach. It is believed that this approach paves the path to a lot of new techniques and circuit design skills that can be investigated more deeply. As an integral part of the time-based processing approach for GHz signal capture, this thesis verifies the advantages of using time amplification. The use of such amplification in the time domain is materialized with experimental results from three specific integrated circuits achieving different tasks in GHz high-speed in-situ signal measurement and characterization. Advantages of using such time-based approach techniques, when combined with the use of a front-end time amplifier, include noise immunity, the use of synthesizable digital cells, and circuit building blocks that track the technology scaling in terms of area and speed.
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Taillefer, Chris. "Reducing measurement uncertainty in a DSP-based mixed-signal test environment." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=84104.
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FFT-based tests (e.g. gain, distortion, SNR, etc.) from a device-under-test (DUT) exhibit normal distributions when the measurement is repeated many times. Hence, a statistical approach to evaluate the accuracy of these measurements is traditionally applied. The noise in a DSP-based mixed-signal test system severely limits its measurement accuracy. Moreover, in high-speed sampled-channel applications the jitter-induced noise from the DUT and test equipment can severely impede accurate measurements.<br>A new digitizer architecture and post-processing methodology is proposed to increase the measurement accuracy of the DUT and the test equipment. An optimal digitizer design is presented which removes any measurement bias due to noise and greatly improves measurement repeatability. Most importantly, the presented system improves accuracy in the same test time as any conventional test.<br>An integrated mixed-signal test core was implemented in TSMC's 0.18 mum mixed-signal process. Experimental results obtained from the mixed-signal integrated test core validate the proposed digitizer architecture and post processing technique. Bias errors were successfully removed and measurement variance was improved by a factor of 5.
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Sutton, Akil Khamisi. "Hardness assurance testing and radiation hardening by design techniques for silicon-germanium heterojunction bipolar transistors and digital logic circuits." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29778.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Cressler, John; Committee Member: Deo, Chaitanya; Committee Member: Doolittle, Alan; Committee Member: Keezer, David; Committee Member: May, Gary; Committee Member: Papapolymerou, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Yang, Dayu Dai Foster. "Frequency syntheses with delta-sigma modulations and their applications for mixed signal testing." Auburn, Ala., 2006. http://hdl.handle.net/10415/1294.
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Elbadri, Mohammed. "A reconfigurable processing unit for digital circuit testing using built-in self-test techniques." Thesis, University of Ottawa (Canada), 2007. http://hdl.handle.net/10393/27514.
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Digital circuit testing is presented in this thesis. This thesis introduces an architecture that accelerates benchmarked circuit testing. Traditionally, benchmark circuits are tested on software, because of the complexity in developing a generic hardware architecture capable of testing sequentially or concurrently. The testing is based on Built-in Self-Test (BIST) techniques. The circuit testing is accomplished by two hardware implementations, aimed at increasing execution time with respect to its counterpart, software. The implementation realized and executed in hardware, illustrates the advantages of utilizing hardware platforms for digital circuit testing and it gives a path to developing more complex benchmarked circuits; which would have higher fault coverage.
The novel architecture is targeted for digital circuit testing and adaptive embedded system applications. These applications vary in their constraints (i.e. hard and soft real-time constraints) and environmental conditions (i.e. unknown and unpredictable).
The novel architecture consists of a fixed hardware unit and a Reconfigurable Processor Unit (RPU). The RPU employs hardware functional blocks. These Hardware Blocks (HB) encompass logic that targets their respective applications. We realize and implement HBs that target digital circuit testing applications, by means of BIST techniques.
Experimental results are presented in this thesis. In simple terms, the speedup factors are as high as 1 x 104 for sequential testing.
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Harbour, Kenton Dean. "A data acquisition system with switched capacitor sample-and-hold." Thesis, Kansas State University, 1986. http://hdl.handle.net/2097/15269.
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Abas, Mohd Amir. "A new methodology of an on chip time measurement circuit for high speed digital testing applications." Thesis, University of Newcastle Upon Tyne, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.289263.
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Lee, Chris Y. "Full Custom VLSI Design of On-Line Stability Checkers." DigitalCommons@CalPoly, 2011. https://digitalcommons.calpoly.edu/theses/607.
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A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital system. The On-line stability checker operates concurrently with its associated circuit-under-test (CUT). This thesis describes the full custom very-large-scale integration (VLSI) design and testing process of On-Line Stability Checkers. The goals of this thesis are to construct and test Stability Checker designs, and to create a design template for future class projects in the EE 431 Computer-Aided Design (CAD) of VLSI Devices course at Cal Poly.
A method for concurrent fault testing called On-line Stability Checking was introduced by Franco and McCluskey [10] to detect reliability failures. Reliability failures initially manifest themselves as delay faults and transient glitching, which become progressively larger over time due to the wearout of conducting metal lines, eventually leading to functional faults. Stability checkers periodically detect reliability failures by monitoring CUT output signals for unstable and late input signals over a time period after the sampling clock edge.
The checkers are tested by applying variable delayed input test patterns to emulate reliability failures. Consequently, configurable delay chains were incorporated into the system to provide variable delays on the input signal lines. The system also includes external test signal ports.
Circuit and layout designs were implemented in the Electric VLSI Design tool [12] and simulated with LTSPICE [13]. Electric provides Design Rule Checking (DRC) and Layout-versus-Schematic (LVS) utilities for verification. Each module was designed in a bottom-up, hierarchical cell-based approach. Functional simulation, DRC and LVS checks were performed at every subsequent higher cell layer in the design hierarchy. The final chip layout was taped out for fabrication on November 29, 2010 and finished parts were received on July 7, 2011 after two manufacturing delays.
Finished packaged parts were successfully verified for functionality based on SPICE simulations. The stability checkers were tested for flip-flop operation, glitch detection and late signal arrival detection. Configurable delay chains were tested to determine delay resolution and uniformity. Actual delay resolution and range measurements show a 3 to 4 times difference compared to simulated values.
The Electric design template created from this project includes basic CMOS logic gates with uniform standard cell heights. The template contains a 40-pin pad ring cell along with the individual pad ring components. EE 431 students would be able to create custom chips that are compatible for fabrication via the MOSIS MEP service. In future work, the template design library can be expanded to include more logic gate variants of various inputs and drive strengths as well as more complex functional modules.
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Banerjee, Aritra. "Design of digitally assisted adaptive analog and RF circuits and systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/52919.
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With more and more integration of analog and RF circuits in scaled CMOS technologies, process variation is playing a critical role which makes it difficult to achieve all the performance specifications across all the process corners. Moreover, at scaled technology nodes, due to lower voltage and current handling capabilities of the devices, they suffer from reliability issues that reduce the overall lifetime of the system. Finally, traditional static style of designing analog and RF circuits does not result in optimal performance of the system. A new design paradigm is emerging toward digitally assisted analog and RF circuits and systems aiming to leverage digital correction and calibration techniques to detect and compensate for the manufacturing imperfections and improve the analog and RF performance offering a high level of integration. The objective of the proposed research is to design digital friendly and performance tunable adaptive analog/RF circuits and systems with digital enhancement techniques for higher performance, better process variation tolerance, and more reliable operation and developing strategy for testing the proposed adaptive systems. An adaptation framework is developed for process variation tolerant RF systems which has two parts – optimized test stimulus driven diagnosis of individual modules and power optimal system level tuning. Another direct tuning approach is developed and demonstrated on a carbon nanotube based analog circuit. An adaptive switched mode power amplifier is designed which is more digital-intensive in nature and has higher efficiency, improved reliability and better process resiliency. Finally, a testing strategy for adaptive RF systems is shown which reduces test time and test cost compared to traditional testing.
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Bilagi, Vedanth. "Experimental Study Of Fault Cones And Fault Aliasing." PDXScholar, 2012. https://pdxscholar.library.pdx.edu/open_access_etds/64.
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The test of digital integrated circuits compares the test pattern results for the device under test (DUT) to the expected test pattern results of a standard reference. The standard response is typically obtained from simulations. The test pattern and response are created and evaluated assuming ideal test conditions. The standard response is normally stored within automated test equipment (ATE). However the use of ATE is the major contributor to the test cost. This thesis explores an alternative strategy to the standard response. As an alternative to the stored standard response, the response is estimated by fault tolerant technique. The purpose of the fault tolerant technique is to eliminate the need of standard response and enable online/real-time testing. Fault tolerant techniques use redundancy and majority voting to estimate the standard response. Redundancy in the circuit leads to fault aliasing. Fault aliasing misleads the majority voter in estimating the standard response. The statistics and phenomenon of aliasing are analyzed for benchmark circuits. The impact of fault aliasing on test with respect to coverage, test escape and over-kill is analyzed. The results show that aliasing can be detected with additional test vectors and get 100% fault coverage.
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Seuring, Markus. "Output space compaction for testing and concurrent checking." Phd thesis, [S.l.] : [s.n.], 2000. http://pub.ub.uni-potsdam.de/2001/0004/seuring.ps.
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Majid, Ashraf Muhammad. "Methods for extending high-performance automated test equipment (ATE) using multi-gigahertz FPGA technologies." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39562.
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Methods for Extending High-Performance Automated Test Equipment (ATE) using
Multi-Gigahertz FPGA Technologies
Ashraf M. Majid
264 Pages
Directed by Dr. David Keezer
This thesis presents methods for developing multi-function, multi-GHz, FPGAbased
test modules designed to enhance the performance capabilities of automated test
equipment (ATE). The methods are used to develop a design approach that utilizes a test
module structure in two blocks. A core logic block is designed using a multi-GHz FPGA
that provides control functions. Another block called the â application specificâ logic
block includes components required for specific test functions. Six test functions are
demonstrated in this research: high-speed signal multiplexing, loopback testing, jitter
injection, amplitude adjustment, and timing adjustment. Furthermore, the test module is
designed to be compatible with existing ATE infrastructure, thus retaining full ATE
capabilities for standard tests. Experimental results produced by this research provide
evidence that the methods are sufficiently capable of enhancing the multi-GHz testing
capabilities of ATE and are extendable into future ATE development. The modular
approach employed by the methods in this thesis allow for flexibility and future
upgradability to even higher frequencies. Therefore the contributions made in this thesis
have the potential to be used into the foreseeable future for enhancements to
semiconductor test capabilities.
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Hedin, Alexander. "Testing and evaluation of the integratability of the Senior processor." Thesis, Linköpings universitet, Datorteknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71043.
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The first version of the Senior processor was created as part of a thesis projectin 2007. This processor was completed and used for educational purposes atLinköpings University. In 2008 several parts of the processor were optimized andthe processor expanded with additional functionality as part of another thesisproject. In 2009 an EU funded project called MULTI-BASE started, in which theComputer Division at the Department of Electrical Engineering participated in.For their part of the MULTI-BASE project, the Senior processor was selected tobe used. After continuous revision and development, this processor was sent formanufacturing. The assignment of this thesis project was to test and verify the different func-tions implemted in the Senior processor. To do this a PCB was developed fortesting the Senior processor together with a Virtex-4 FPGA. Extensive testingwas done on the most important functions of the Senior processor. These testsshowed that the manufactured Senior processor works as designed and that it alonecan perform larger calculations and use external hardware accelerators with thehelp of its various interfaces.<br>Den första versionen av Senior processorn skapades som en del i ett examensarbe-te under 2007, denna processor färdigställdes och användes i utbildningssyfte påLinköping Universitet. 2008 optimerades flera delar av processorn och utökadesmed extra funktionalitet som del av ytterligare ett examensarbete. 2009 startadeett EU finansierat projekt vid namn MULTI-BASE, som ISYs Datortekniks avdel-ning deltar i. Till deras del av MULTI-BASE projektet valdes Senior processorn attanvändas, efter ytterligare utveckling skickades denna processor för tillverkning. Detta examensarbete hade i uppgift att testa och verifiera de olika funktionernasom Senior processorn har implementerats med. För att göra detta tillverkades ettkretskort som ska användas för att testa Senior processorn tillsammans med enVirtex-4 FPGA. Utförliga tester gjordes på de viktigaste funktionerna hos Seniorprocessorn, dessa tester visade att den tillverkade Senior processorn fungerar somplanerat. Den kan på egen hand utföra större beräkningar och använda sig avexterna hårdvare acceleratorer med hjälp av sina olika gränssnitt.
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Micallef, Steven P. "Hierarchical testing of integrated circuits." Thesis, University of Oxford, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.291399.
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Ward, Derek. "Digital parametric testing." Thesis, University of Edinburgh, 1991. http://hdl.handle.net/1842/11514.
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As minimum geometries of VLSI processes continue to shrink there have been two main effects on the field of parametric test. Firstly, structures must be able to characterise these smaller geometries and secondly the space for test structures has become more limited due to the requirement for them to be located in the scribe channel. The work of this thesis investigates methods of increasing the efficiency of test structure implementation to alleviate these problems. This work has demonstrated SPICE parameter extraction from test transistors accessed via a digitally addressed multiplexer: firstly using test circuits, to analyse pass transistor effects, then on a test chip using multiplexed access. The technique allows SPICE parameters to be extracted from transistor arrays with a large saving in the number of probe pads and hence overall silicon area. Digital misalignment structures have been implemented for the characterisation of small geometry processes. Use of such structures is demonstrated in this thesis using both a shift register output and a novel 'diode vernier' scheme. One of the main drawbacks of using shift register structures has been the requirement for a large amount of functional circuitry. The diode vernier introduced in this thesis is a simply designed structure that can be easily tested with standard parametric test equipment and requires only one diode per test structure element. Finally, a digital process control chip has been fabricated to integrate the ideas presented in this thesis. This uses multiplexers to access both test transistors and diode vernier structures. It demonstrates the feasibility of using a digital approach to parametric test chip design which has the potential to significantly reduce the area required for test structures.
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Knight, Clinton D. "WWW-based testing of analog circuits." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/14863.
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Huang, Jeff Chen-Ho. "Exhaustive testing of acyclic sequential circuits." Thesis, Brunel University, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.319326.
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Bystrov, Alexandre. "Optimal testing of multilevel logic circuits." Thesis, Edinburgh Napier University, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.300327.
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Burgess, N. "Fault-oriented testing of MOS circuits." Thesis, University of Southampton, 1986. https://eprints.soton.ac.uk/256260/.
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El-Hage, Hassan M. "Digital triaxial testing system: Implementation of the digital triaxial testing system." Thesis, University of Ottawa (Canada), 1986. http://hdl.handle.net/10393/10673.
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Taber, Caleb N. "Conversion of Digital Circuits Labs." Digital Commons @ East Tennessee State University, 2016. https://dc.etsu.edu/honors/395.
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The engineering technology department at ETSU currently lacks a modern method to teach digital circuits. The aim of this thesis is to convert our current digital circuits labs to equivalent labs suited to run on the Basys 3. The Basys has several advantages over the aging NI Elvis boards (and now just breadboards) currently in use. The first advantage is that the Basys gives students a taste of FPGA programming without being overwhelmingly; like the systems currently in place for the digital signal processing class. The Basys is also a more modern system; our current integrated circuit and breadboard system is from the 70’s and has little to do with the modern world of electronics.
There are several major difficulties with moving towards the Basys 3. It requires several tweaks to the current computer security setting of the lab computers. The other issue to be solved is that very few people in the department have even an inkling of how to program in VHDL and most of them are outgoing students. This lack of skills could be a threat to the class but I have included an appendix and a few recommendations for books on the subject to ensure that system development can continue.
The other objective of this project was to see if there were ways to incorporate new educational techniques into the engineering technology curriculum. While there have been no actual tests on students, the groundwork has been laid to use some new ideas in the classroom. All of these new systems are designed to get students to think about how devices actually work and develop models to help them fully understand what is being taught.
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Nayeem, Noor Muhammed. "Synthesis and testing of reversible Toffoli circuits." Thesis, Lethbridge, Alta. : University of Lethbridge, Dept. of Mathematics and Computer Science, c2012, 2012. http://hdl.handle.net/10133/3309.
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Recently, researchers have been interested in reversible computing because of its ability to
dissipate nearly zero heat and because of its applications in quantum computing and low
power VLSI design. Synthesis and testing are two important areas of reversible logic. The
thesis first presents an approach for the synthesis of reversible circuits from the exclusive-
OR sum-of-products (ESOP) representation of functions, which makes better use of shared
functionality among multiple outputs, resulting in up to 75% minimization of quantum cost
compared to the previous approach. This thesis also investigates the previous work on constructing
the online testable circuits and points out some design issues. A simple approach
for online fault detection is proposed for a particular type of ESOP-based reversible circuit,
which is also extended for any type of Toffoli circuits. The proposed online testable designs
not only address the problems of the previous designs but also achieve significant improvements
of up to 78% and 99% in terms of quantum cost and garbage outputs, respectively.<br>xii, 82 leaves : ill. ; 29 cm
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Garth, S. C. J. "Electron beam testing of operating integrated circuits." Thesis, University of Cambridge, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.304338.
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PALANISWAMY, ASHOK KUMAR. "SYNTHESIS AND TESTING OF THRESHOLD LOGIC CIRCUITS." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/963.
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Threshold logic gates gaining more importance in recent years due to the significant development in the switching devices. This renewed the interest in synthesis and testing of circuits with threshold logic gates. Two important synthesis considerations of threshold logic circuits are addressed namely, threshold logic function identification and reducing the total number of threshold logic gates required to represent the given boolean circuit description. A fast method to identify the given Boolean function as a threshold logic function with weight assignment is introduced. It characterizes the threshold logic function based on the modified chows parameters which results in drastic reduction in time and complexity. Experiment results shown that the proposed method is at least 10 times faster for each input and around 20 times faster for 7 and 8 input, when comparing with the algorithmic based methods. Similarly, it is 100 times faster for 8 input, when comparing with asummable method. Existing threshold logic synthesis methods decompose the larger input functions into smaller input functions and perform synthesis for them. This results in increase in the number of threshold logic gates required to represent the given circuit description. The proposed implicit synthesis methods increase the size of the functions that can be handled by the synthesis algorithm, thus the number of threshold logic gates required to implement very large input function decreases. Experiment results shown that the reduction in the TLG count is 24% in the best case and 18% on average. An automatic test pattern generation approach for transition faults on a circuit consisting of current mode threshold logic gates is introduced. The generated pattern for each fault excites the maximum propagation delay at the gate (the fault site). This is a high quality ATPG. Since current mode threshold logic gate circuits are pipelined and the combinational depth at each pipeline stage is practically one. It is experimentally shown that the fault coverage for all benchmark circuits is approximately 97%. It is also shown that the proposed method is time efficient.
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Söderquist, Ingemar. "CMOS circuits for digital RF systems /." Linköping : Univ, 2002. http://www.bibl.liu.se/liupubl/disp/disp2002/tek775s.pdf.
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Shenoy, Sandeep P. (Sandeep Pundalika). "Switching activity in CMOS digital circuits." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=24071.
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In (48, 47) a pattern-independent method to estimate the switching activity of a CMOS circuit was presented. The technique relies on the use of abstract waveforms, described down to the level of individual transitions, which are propagated through the circuit. In order to improve the switching activity estimate so obtained, case analysis is undertaken on nodes with large fanout.<br>The objective of this thesis is to develop and implement a method to further improve upon the switching activity estimate through consideration of reconvergent fanout regions in the circuit. The idea is to impose functional consistency upon the waveforms at the nodes of a subset of the circuit to obtain an exact count of the number of transitions and potentially the exact waveforms which give rise to that. The result is the same as if an exact simulation was performed, but the novelty here is in the technique. An exact simulation would have exponential complexity as all possible waveforms on the PIs to the sub-circuit would have to be enumerated. Branch and bound techniques are used here instead to execute a progressively limited analysis which avoids exponential complexity. Furthermore heuristics are used to speed up the algorithm.<br>In addition a simple greedy algorithm has been developed and implemented to identify the sub-circuits where application of the above described technique would have the best results. The greedy algorithm represents only a preliminary step, and further work needs to be done on a more comprehensive circuit partitioning technique.
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Traiola, Marcello. "TEST TECHNIQUES FOR APPROXIMATE DIGITAL CIRCUITS." Thesis, Montpellier, 2019. http://www.theses.fr/2019MONTS060.
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Au cours des dernières décennies, la demande d’efficacité informatique n’a cessé de croître. L’affirmation d’applications de nouvelle génération consommatrices d’énergie d’un côté, et d’appareils portables basse consommation de l’autre, exige un nouveau paradigme informatique capable de faire face aux exigences concurrentes des défis technologiques actuels. Ces dernières années, plusieurs études sur les applications dites de "Recognition, Mining and Synthesis (RMS)" ont été menées. Une particularité très intéressante a été identifiée : la résilience intrinsèque de ces applications. Une telle propriété permet aux applications RMS d’être très tolérantes aux erreurs. Ceci est dû à différents facteurs, tels que les données bruyantes traitées par ces applications, les algorithmes non déterministes utilisés et les réponses non uniques possibles. Ces propriétés ont été exploitées par un nouveau paradigme informatique de plus en plus établi : le calcul approximé (AxC). L’AxC profite intelligemment de la résilience intrinsèque des applications RMS pour réaliser des gains en termes de consommation électrique, de temps de fonctionnement et/ou de surface de puce. En effet, en introduisant des assouplissants sélectifs des spécifications non critiques, certaines parties du système informatique cible peuvent être simplifiées, pour finalement atteindre l’objectif de l’AxC. De plus, l’AxC est capable de cibler différentes couches des systèmes informatiques, du matériel au logiciel. Dans cette thèse, nous nous concentrons sur les circuits intégrés approximés (AxICs) qui sont le résultat de l’application AxC au niveau matériel. En particulier, nous nous concentrons sur l’approximation fonctionnelle des circuits intégrés, utilisée au cours des dernières années afin de concevoir efficacement les AxICs. En raison de la pertinence croissante des AxICs, il devient important de relever les nouveaux défis pour tester de tels circuits. À cet égard, certains travaux ont attiré l’attention sur les défis que représente l’approximation fonctionnelle pour les procédures de test. En même temps, l’approximation fonctionnelle des circuits intégrés offre également des possibilités. Plus en détails - d’une part - le concept de circuit acceptable change : alors qu’un circuit est conventionnellement bon si ses réponses ne sont jamais différentes de celles attendues, dans le contexte AxIC certaines réponses inattendues peuvent encore être acceptables. Pour la même raison - d’autre part - certaines fautes acceptables peuvent ne pas être détectées, ce qui mène à un gain de rendement de production (c.-à-d., augmentation du pourcentage de circuits acceptables, parmi tous les circuits fabriqués). Pour mesurer l’erreur produite par un AxIC, plusieurs métriques d’erreur ont été proposées dans la littérature. Dans cette thèse, nous présentons un ensemble de techniques de test pour les circuits approximés. En particulier, nous nous concentrons sur trois phases fondamentales du déroulement du test. Premièrement, la classification des fautes AxIC en non-redundant et ax-redundant (c.-à-d. catastrophique et acceptable, respectivement) en fonction d’un seuil d’erreur (c.-à-d. la quantité maximale tolérable d’erreur). Cette classification permet d’obtenir deux listes de fautes (c.-à-d. nonredundant et ax-redundant). Ensuite, nous proposons une génération automatique de séquences de test qui soit “consciente de l’approximation”. Les tests obtenus préviennent les défaillances catastrophiques en détectant les fautes non-redundant. En même temps, ils minimisent la détection sur les ax-redundant. Enfin – puisque dans certains cas le gain de rendement obtenu ne correspond toujours pas à celui attendu, à cause de la structure propre des AxICs – nous proposons une technique pour classer correctement les AxICs dans les catégories “catastrophiquement défectueux” et “acceptablement défectueux”, après l’application du test<br>Despite great improvements of the semiconductor industry in terms of energy efficiency, the computer systems’ energy consumption is constantly growing. Many largely used applications – usually referred to as Recognition, Mining and Synthesis (RMS) applications – are more and more deployed as mobile applications and on Internet of Things (IoT) structures. Therefore, it is mandatory to improve the future silicon devices and architectures on which these applications will run. Inherent resiliency property of RMS applications has been thoroughly investigated over the last few years. This interesting property leads applications to be tolerant to errors, as long as their results remain close enough to the expected ones. Approximate Computing (AxC) , is an emerging computing paradigm which takes advantages of this property. AxC has gained increasing interest in the scientific community in last years. It is based on the intuitive observation that introducing selective relaxation of non-critical specifications may lead to efficiency gains in terms of power consumption, run time, and/or chip area. So far, AxC has been applied on the whole digital system stack, from hardware to application level. This work focuses on approximate integrated circuits (AxICs), which are the result of AxC application at hardware-level. Functional approximation has been successfully applied to integrated circuits (ICs) in order to efficiently design AxICs. Specifically, we focus on testing aspects of functionally approximate ICs. In fact – since approximation changes the functional behavior of ICs – techniques to test them have to be revisited. In fact, some previous works – have shown that circuit approximation brings along some challenges for testing procedures, but also some opportunities. In particular, approximation procedures intrinsically lead the circuit to produce errors, which have to be taken into account in test procedures. Error can be measured according to different error metrics. On the one hand, the occurrence of a defect in the circuit can lead it to produce unexpected catastrophic errors. On the other hand, some defects can be tolerated, when they do not induce errors over a certain threshold. This phenomenon could lead to a yield increase, if properly investigated and managed. To deal with such aspects, conventional test flow should be revisited. Therefore, we introduce Approximation-Aware testing (AxA testing). We identify three main AxA testing phases: (i) AxA fault classification, (ii) AxA test pattern generation and (iii) AxA test set application. Briefly, the first phase has to classify faults into catastrophic and acceptable; the test pattern generation has to produce test vectors able to cover all the catastrophic faults and, at the same time, to leave acceptable faults undetected; finally, the test set application needs to correctly classify AxICs under test into catastrophically faulty, acceptably faulty, fault-free. Only AxICs falling into the first group will be rejected. In this thesis, we thoroughly discuss the three phases of AxA testing, and we present a set of AxA test techniques for approximate circuits. Firstly, we work on the classification of AxIC faults into catastrophic and acceptable according to an error threshold (i.e. the maximum tolerable amount of error). This classification provides two lists of faults (i.e. catastrophic and acceptable). Then, we propose an approximation-aware (ax-aware) Automatic Test Pattern Generation. Obtained test patterns prevent catastrophic failures by detecting catastrophic defects. At the same time, they minimize the detection of acceptable ones. Finally – since the AxIC structure often leads to a yield gain lower than expected – we propose a technique to correctly classify AxICs into “catastrophically faulty”, “acceptably faulty”, “and fault-free”, after the test application. To evaluate the proposed techniques, we perform extensive experiments on state-ofthe-art AxICs
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GOLLAMUDI, CHAKRAPANI. "HIERARCHICAL EVOLUTION OF DIGITAL ARITHMETIC CIRCUITS." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin981480290.
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Chen, Daven 1959. "COMPARISON OF SCIRTSS EFFICIENCY WITH D-ALGORITHM APPLICATION TO ITERATIVE NETWORKS (TEST)." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/275572.
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