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Journal articles on the topic 'Testing of Digital Circuits'

Author: Grafiati

Published: 4 June 2025

Last updated: 15 July 2025

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1

Semerenko, Vasyl, and Oleksandr Roik. "Testing of digital circuits by cyclic codes." Computational Problems of Electrical Engineering 7, no. 2 (2017): 78–82. https://doi.org/10.23939/jcpee2017.02.078.

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The application of error correction coding theory to the tasks of technical diagnostics is considered. Known methods of testing based on signature analysis allow detecting only the faults in the digital circuit under test (CUT). The purpose of the research is to provide the possibility of an exact localization of the faults in logic subcircuits within the CUT. In the proposed method, a full test T for testing the CUT is subdivided into an input test T1 (supplied to the inputs of the CUT) and an output test T2 of the expected signatures (recorded into a memory block). Tests T1 and T2 are interpreted as a set of information words and a set of check words of the cyclic Hamming code respectively and are generated by the encoder. The decoder decodes words from both tests simultaneously and searches for errors only in the test T1. As a result, full burst errors in the information words of error correcting code are corrected, which is equivalent to the exact localization of the faults within the CUT.

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2

Falkowski, Bogdan J. "Spectral Testing of Digital Circuits." VLSI Design 14, no. 1 (2002): 83–105. http://dx.doi.org/10.1080/10655140290009828.

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Fault detection techniques using data compression methods have evolved during the last few years. Considerable work using individual Walsh spectral coefficients has been reported. In this paper, the application of spectral methods in testing of digital circuits with the emphasis on their usage for both input and output test compaction of digital circuits is described. Two closely related testing methods are discussed: syndrome testing and spectral testing as well as an overview of syndrome-testing and syndrome-testable design is presented. The necessary background and notation on Walsh spectral coefficients as well as their meaning in classical logic terms is shown.

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3

Bradshaw, GeorgeM, PeterL L. Desyllas, and Keit McLaren. "4566104 Testing digital electronic circuits." Microelectronics Reliability 26, no. 5 (1986): 998. http://dx.doi.org/10.1016/0026-2714(86)90248-9.

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4

Moussa, Mahmoud, and Atef Salama. "Digital Testing of Analog Circuits." Fayoum University Journal of Engineering 7, no. 2 (2024): 45–52. http://dx.doi.org/10.21608/fuje.2024.343764.

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5

Rajeswaran, N., T. Madhu, and M. Suryakalavathi. "Hardware Testable Design of Genetic Algorithm for VLSI Circuits." Applied Mechanics and Materials 367 (August 2013): 245–49. http://dx.doi.org/10.4028/www.scientific.net/amm.367.245.

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Accurate and fast testing of digital circuits is very much essential in real time applications. Hardware analysis of digital circuits, which is otherwise very tedious and time consuming, is attempted using the artificial intelligence technique: Genetic Algorithms (GA). GA is used to find an input sequence to a digital circuit for testing, as it reduces the hardware utilization, complexity and computational time of the circuits. All the GA processes are simulated and implemented by using Xilinx 10.1 and SPARTAN 3E.

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Mokhtarnia, Hossein, Shahram Etemadi Borujeni, and Mohammad Saeed Ehsani. "Automatic Test Pattern Generation Through Boolean Satisfiability for Testing Bridging Faults." Journal of Circuits, Systems and Computers 28, no. 14 (2019): 1950240. http://dx.doi.org/10.1142/s0218126619502402.

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Automatic test pattern generation (ATPG) is one of the important issues in testing digital circuits. Due to considerable advances made in the past two decades, the ATPG algorithms that are based on Boolean satisfiability have become an integral part of the digital circuits. In this paper, a new method for ATPG for testing bridging faults is introduced. First of all, the application of Boolean satisfiability to circuit modeling is explained. Afterwards, a new method of testing the nonfeedback bridging faults in the combinational circuits is proposed based on Boolean satisfiability. In the proposed method, the faulty circuit is obtained by injecting the faulty gate into the main circuit. Afterwards, the final differential circuit is prepared by using the fault-free and the faulty circuits. Finally, using the resulting differential circuit, the testability of the fault is assessed and the input pattern for detecting the fault in the main circuit is derived. The experimental results presented at the end of this paper indicate the effectiveness and usefulness of this method for testing the bridging faults.

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7

Gavrilenkov, Sergey I., Elizaveta O. Petrenko, and Evgeny V. Arbuzov. "A Digital Device for Automatic Checking of Homework Assignments in the Digital Circuits Course." ITM Web of Conferences 35 (2020): 04009. http://dx.doi.org/10.1051/itmconf/20203504009.

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This paper considers a digital device for automatic checking of homework assignments in the digital circuits course. The assignment is to make a digital circuit corresponding to a given logical expression; the circuit is comprised of elementary logic gates. The process of manual testing the built circuit is very labor-intensive because checking a circuit with N inputs variables requires checking the correctness of the output variable for 2N cases. We propose automating this pro-cess with a special digital device. The device is comprised of a microcontroller connected to the circuit tested. The microcontroller is connected to a personal computer with an application written in C# for executing the main operations of the testing process. During testing, the student chooses from a database or enters the logical expression corresponding to the circuit tested. For the expression, the software generates truth tables where actual and required responses of the circuit are given. Actual circuit responses are acquired by probing the circuit via the microcontroller, and the expected values are calculated from the logical expression. The truth tables are then presented to the student with a message of whether the circuit works correctly or not. The device was integrated into the process of checking homework assignments in the digital electronics course, and it significantly sped up the process of checking homework assignment circuits, resulting in better education quality.

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8

Litikov, I. P. "Ring-like testing of digital circuits." Measurement 4, no. 1 (1986): 2–6. http://dx.doi.org/10.1016/0263-2241(86)90023-0.

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9

El-Mahlawy, M., Sh Mahmoud, E. Gadallah, and E. El-Samahy. "New Digital Testing of Analogue Circuits." International Conference on Aerospace Sciences and Aviation Technology 16, AEROSPACE SCIENCES (2015): 1–24. http://dx.doi.org/10.21608/asat.2015.22880.

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10

Litikov, I. P. "Ring-like testing of digital circuits." Journal of Electronic Testing 1, no. 4 (1991): 301–4. http://dx.doi.org/10.1007/bf00136318.

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11

Saluja, K. K., R. Sharma, and C. R. Kime. "A concurrent testing technique for digital circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, no. 12 (1988): 1250–60. http://dx.doi.org/10.1109/43.16803.

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12

Boneh, A., and J. Savir. "Statistical resistance to detection (digital circuits testing)." IEEE Transactions on Computers 41, no. 1 (1992): 123–26. http://dx.doi.org/10.1109/12.123388.

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13

Assaf, Mansour, Leslie-Ann Moore, Sunil Das, Satyendra Biswas, and Scott Morton. "Low-level logic fault testing ASIC simulation environment." World Journal of Engineering 11, no. 3 (2014): 279–86. http://dx.doi.org/10.1260/1708-5284.11.3.279.

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A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.

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14

Jiang, Yu Chuan, Fang Quan Yang, and Bao Gang Sun. "Study on Fault Testing System of Photovoltaic Cells." Advanced Materials Research 1022 (August 2014): 151–54. http://dx.doi.org/10.4028/www.scientific.net/amr.1022.151.

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This paper designed a photovoltaic cell fault test system to study the design of wireless sensor networks and related technologies in this article, including the two main parts of the data collection and data aggregation node node design, through the design of the circuit to collect voltammetry data by DHT22 digital temperature and humidity sensors and related peripheral circuits to collect temperature, humidity and light intensity data presented content power circuit design serial communication circuit, and anti-jamming measures.

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15

Olaru, A. I., and G. Predusca. "Application Development on the Nexys 4 DDR Platform: Techniques And Implementations." Scientific Bulletin of Electrical Engineering Faculty 25, no. 1 (2025): 1–8. https://doi.org/10.2478/sbeef-2025-0001.

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Abstract The article explores the application of digital circuits, such as logic gates, logic functions, flip-flop, and automata, using the Nexys 4 DDR platform from Xilinx and the Vivado software. The Nexys 4 DDR, featuring the Artix-7 FPGA, provides a robust environment for designing and testing digital systems. It allows for efficient implementation of various digital functions through hardware programming and simulation. The use of Vivado software eases the creation, simulation, and deployment of custom digital circuits, highlighting the versatility and power of FPGA technology in real-world applications. This paper highlights key principles, practical implementations, and design considerations involved in using these tools for digital circuit applications.

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16

EJAZ AHMED, RANA. "Fault-detection in syndrome testing of digital circuits." International Journal of Electronics 75, no. 2 (1993): 345–48. http://dx.doi.org/10.1080/00207219308907113.

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17

Feofanovich, Berezkin. "One approach to compact testing of digital circuits." Journal of Applied Engineering Science 17, no. 1 (2019): 26–34. http://dx.doi.org/10.5937/jaes17-18539.

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18

Sharath, Kumar Y. N., and P. Dinesha. "TFI-FTS: An efficient transient fault injection and faulttolerant system for asynchronous circuits on FPGA platform." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 3 (2021): 2704–10. https://doi.org/10.11591/ijece.v11i3.pp2704-2710.

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Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, asynchronous circuits based on effective transient fault injection (TFI) and fault tolerant system (FTS) are modeled. The TFI system generates the faults based on BMA based LFSR with faulty logic insertion and one hot encoded register. The BMA based LFSR reduces the hardware complexity with less power consumption on-chip than standard LFSR method. The FTS uses triple mode redundancy (TMR) based majority voter logic (MVL) to tolerant the faults for asynchronous circuits. The benchmarked 74X-series circuits are considered as an asynchronous circuit for TMR logic. The TFI-FTS module is modeled using Verilog-HDL on Xilinx-ISE and synthesized on hardware platform. The Performance parameters are tabulated for TFI-FTS based asynchronous circuits. The performance of TFI-FTS module is analyzed with 100% fault coverage. The fault coverage is validated using functional simulation of each asynchronous circuit with fault injection in TFI-FTS module.

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19

Jadczak, Kamila, and Rafał Białek. "Laboratory Station for Reliability Testing of Digital Circuits Using Signature Analysis." Journal of KONBiN 45, no. 1 (2018): 165–82. http://dx.doi.org/10.2478/jok-2018-0009.

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Abstract The article presented a laboratory station for diagnosing the digital circuits and the test results on the basis of a selected example. The idea of a response compression technique, which is called an analysis of signatures, was demonstrated. The main element of the station includes 8-bit programme of an analyser of signatures, which was developed by the authors, and implemented in the LabVIEW environment with the use of NI 6008 data analysis module. The programme operation was tested on the selected digital circuit, and the obtained results were provided in the article.

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20

Y. N., Sharath Kumar, and Dinesha P. "TFI-FTS: An efficient transient fault injection and fault-tolerant system for asynchronous circuits on FPGA platform." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 3 (2021): 2704. http://dx.doi.org/10.11591/ijece.v11i3.pp2704-2710.

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Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the faults based on BMA based LFSR with faulty logic insertion and one hot encoded register. The BMA based LFSR reduces the hardware complexity with less power consumption on-chip than standard LFSR method. The FTS uses triple mode redundancy (TMR) based majority voter logic (MVL) to tolerant the faults for asynchronous circuits. The benchmarked 74X-series circuits are considered as an asynchronous circuit for TMR logic. The TFI-FTS module is modeled using Verilog-HDL on Xilinx-ISE and synthesized on hardware platform. The Performance parameters are tabulated for TFI-FTS based asynchronous circuits. The performance of TFI-FTS Module is analyzed with 100% fault coverage. The fault coverage is validated using functional simulation of each asynchronous circuit with fault injection in TFI-FTS Module.

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21

Zhang, Jin, Zhenghui Liu, Xiao Hu, Peixin Liu, Zhiling Hu, and Lidan Kuang. "FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs." Electronics 13, no. 9 (2024): 1667. http://dx.doi.org/10.3390/electronics13091667.

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The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.

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22

Alamgir, Arbab, Abu Khari A'ain, Norlina Paraman, and Usman Ullah Sheikh. "Adaptive random testing with total cartesian distance for black box circuit under test." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 2 (2020): 720–26. https://doi.org/10.11591/ijeecs.v20.i2.pp720-726.

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Testing and verification of digital circuits is of vital importance in electronics industry. Moreover, key designs require preservation of their intellectual property that might restrict access to the internal structure of circuit under test. Random testing is a classical solution to black box testing as it generates test patterns without using the structural implementation of the circuit under test. However, random testing ignores the importance of previously applied test patterns while generating subsequent test patterns. An improvement to random testing is Antirandom that diversifies every subsequent test pattern in the test sequence. Whereas, computational intensive process of distance calculation restricts its scalability for large input circuit under test. Fixed sized candidate set adaptive random testing uses predetermined number of patterns for distance calculations to avoid computational complexity. A combination of max-min distance with previously executed patterns is carried out for each test pattern candidate. However, the reduction in computational complexity reduces the effectiveness of test set in terms of fault coverage. This paper uses a total cartesian distance based approach on fixed sized candidate set to enhance diversity in test sequence. The proposed approach has a two way effect on the test pattern generation as it lowers the computational intensity along with enhancement in the fault coverage. Fault simulation results on ISCAS’85 and ISCAS’89 benchmark circuits show that fault coverage of the proposed method increases up to 20.22% compared to previous method.

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23

SEMENOV, Andriy, Maksym ANDREIENKOV, Anton KHLOBA, Mykhailo SHURKHAL, and Vladyslav OLKHOVYCH. "DEVELOPMENT OF A 150 W LINEAR LABORATORY POWER SUPPLY UNIT." MEASURING AND COMPUTING DEVICES IN TECHNOLOGICAL PROCESSES, no. 1 (March 28, 2024): 166–75. http://dx.doi.org/10.31891/2219-9365-2024-77-21.

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The laboratory power supply is an indispensable device for the manufacture, testing, adjustment and repair of electronic equipment. The object of research is the process of selecting and justifying the device circuit on a modern element base, developing a printed circuit board, manufacturing and testing the created device layout in practice. The toroidal transformer of the required power was also calculated. The test was carried out in the voltage and current stabilization mode, and the data obtained indicate the possibility of further improvement of the device's circuitry. To build a laboratory power supply, it is desirable to use a linear circuit, because of the small pulsations that are critical when powering electronic equipment. A switching power supply can be used as an additional source when working with high-power circuits. A universal option is a bipolar power supply built according to a linear circuit with an output voltage of 0...±30 V and a current of 0...5 A. This solution will allow the device to be used for operation with most radio electronic devices, including those sensitive to RF noise, whose power consumption does not exceed 150 W. Thanks to the use of a bipolar circuit, it is also possible to work with high-quality audio frequency amplifiers that require bipolar power supply, operational amplifiers and some digital equipment. The galvanic isolation of the channels will make it possible to adjust the output parameters independently for each arm, which may be necessary when repairing digital equipment. Equipping the laboratory power supply with a current stabilization unit will make it possible to use the power supply as a battery charger and help in finding short circuits in circuits. Short-circuit protection will save the power supply in the event of an emergency and, in some cases, save the connected load.

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24

Rubio, A., J. Figueras, and J. Segura. "Quiescent current sensor circuits in digital VLSI CMOS testing." Electronics Letters 26, no. 15 (1990): 1204. http://dx.doi.org/10.1049/el:19900779.

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25

Kobayashi, Haruo, and Anna Kuwana. "Study of analog-to-digital mixed integrated circuit configuration using number theory." Impact 2022, no. 3 (2022): 9–11. http://dx.doi.org/10.21820/23987073.2022.3.9.

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Electronic circuits form the basis of much of the technology we use today. Professor Haruo Kobayashi and Assistant Professor Anna Kuwana, Division of Electronics and Informatics, Gunma University, Japan, are utilising classical mathematics, including theorems such as number theory and control theory in their design of circuits that contain elements of analogue signalling. Analogue circuit planning is regarded as an art as these circuits are typically designed based on mature designers' intuition and experiences in a process that is less systematic for coming up with new architectures and more designing than digital circuit design and Kobayashi and Kuwana firmly believe that 'beautiful' mathematics can facilitate truly great circuit design. Additional mathematics techniques employed by Kobayashi and the team are statistics, coding theory, modulation and signal processing algorithms and pairing pure mathematics theorems with electrical engineering is a key feature of the researchers' work. The team utilises theoretical analysis and simulations such as the circuit simulator (SPICE) and system simulator (MATLAB) to test its work and collaborates with semiconductor companies and electronic measurement instrument companies in Japan for smart circuit design and effective circuit testing. So far, results include that using SAR ADC configurations with Fibonacci sequence weights can improve the speeds and reliability of the SAR ADC. Also several new DAC architecutures and waveform sampling methods are derived based on mathematics.

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Pujari, Arati, Yash Patil, Nazneen Mulani, Tejashri Bhale, and Ankita Jadhav. "Digital IC Tester For 74XX Series using PIC18F4550." Journal of Power Electronics and Devices 9, no. 3 (2023): 14–18. http://dx.doi.org/10.46610/joped.2023.v09i03.003.

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A microcontroller-based circuit known as a "digital IC tester" determines if an integrated circuit is in good operating order or not. Product testing is a costly and time-consuming procedure in industries. Testing is required before the system is fully operational to prevent mistakes and undesirable outcomes. Similar to this, in educational institutions, it is required to verify whether the IC is excellent or bad before doing experiments during practicals. Numerous minor IC flaws cause the system to operate erratically and generate incorrect outputs. Therefore, the purpose of this research is to use a PIC microcontroller to construct an IC tester that can test the majority of integrated circuits in the 74xx series logic gates. The main goal of this project is to simulate the features of a logic gate IC and use the truth table of that specific IC to verify the state of the gates in that IC. Several design philosophies were contrasted before one was ultimately put into practice. Following the successful completion of simulation and testing, they were combined to produce the final version.

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27

Ganji, Mona, Marampally Saikiran, Kushagra Bhatheja, and Degang Chen. "Digital-like built-in defect-oriented test for analog-mixed signal circuits." Design+ 1, no. 1 (2024): 4351. http://dx.doi.org/10.36922/dp.4351.

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In this paper, we present a novel digital-like defect-oriented built-in self-test (BIST) methodology for analog and mixed-signal (AMS) circuits. The core idea of this approach centers around the segmentation of complex AMS circuits into smaller, more manageable units for analysis. Emphasizing resource utilization efficiency, we highlight the necessity of employing purely digital circuits for both injectors and monitors within the BIST framework. We demonstrate the effectiveness of this approach through the development of a BIST system for a 12-bit successive approximation register analog-to-digital converter (SAR ADC). Notably, our methodology achieves 100% defect coverage without introducing additional BIST circuitry for subcircuit testing, relying solely on digital monitors for sampling switch evaluation. Furthermore, our proposed approach incurs minimal area overhead, resulting in a fast and comprehensive defect-oriented BIST solution. This versatile test method can be deployed post-manufacturing or in-field, offering flexibility in its application timing.

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28

Zhao, Sihan. "Design and implementation of a preset operational amplifier based on basic digital and analog hybrid circuit." Applied and Computational Engineering 38, no. 1 (2024): 112–20. http://dx.doi.org/10.54254/2755-2721/38/20230539.

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In the vast landscape of electronic engineering, the indispensable roles of both analog and digital circuits are unequivocally recognized. Analog circuits, with their foundational principles, are extensively harnessed in areas encompassing audio, video, power systems, and particularly, amplifiers. Conversely, digital circuits, integral to modern-day technological advancements, are dominantly present in computing platforms, telecommunication systems, control mechanisms, and data storage infrastructures. Amplifiers, a cornerstone in analog circuit designs, principally focus on magnifying the amplitude of input signals, whether it be in terms of voltage or current. This amplification process hinges on the strategic configuration of electronic elements such as transistors, resistors, and capacitors. This paper endeavors to marry the attributes of digital and analog circuits. Through the adept utilization of fundamental electronic components, an innovative amplifier design capable of preset amplification ratios is birthed. The practicality and efficacy of this amplifier are rigorously validated via its hands-on assembly and experimental testing in a laboratory setting. Results consistently underscore the amplifiers adeptness in delivering precise signal amplification, conforming to its predetermined ratios. Such a design, rooted in its simplicity yet offering profound versatility, beckons further exploration. It stands as a beacon for potential future adaptions, tailored to suit a gamut of applications, and is poised to seamlessly dovetail into more sophisticated circuit systems.

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29

Efanov, D. V., and T. S. Pogodina. "The specificity of error detection as part of computing testing in digital devices based on self-duality of Boolean functions." Dependability 24, no. 2 (2024): 24–37. http://dx.doi.org/10.21683/1729-2646-2024-24-2-24-37.

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Aim. To identify the specificity of error detection as part of self-dual calculations testing by automation devices, as well as to propose a method for organising calculations testing that would allow detecting any malfunctions from the defined model. Methods. The paper used methods of technical diagnostics of discrete systems, Boolean algebra, and combinatorics. Results. The specificity of error detection at the outputs of self-dual digital devices of combination type were analysed. The conditions for detecting and not detecting errors at the outputs of self-dual combinational circuits were formalised. In practice, the latter allow – by analysing potential errors at the outputs – creating fully self-checking circuits. At the same time, it is noted that if full coverage of all errors at the outputs of self-dual circuits cannot be achieved when computing-testing only on the basis of whether a function belongs to the self-dual class, then in some cases that can be made possible through additional checking of whether the generated code vectors belong to a pre-selected redundant code. It is established, what features of actual digital devices enable large numbers of errors compensated for by self-dual testing. It is theoretically determined that, in real practical applications with self-dual computing testing, the larger is the number of input variables, the higher is the probability of not detecting an error due to a larger number of combinations of distortions at the outputs. However, the greater is the number of functions implemented by a device, the higher is the probability of error detection. Nonetheless, in practice, each case of computations testing based on the self-duality of calculated functions should be treated individually for each digital device. The paper presents some experimental results that demonstrate the specificity of error detection at the outputs of self-dual combinational circuits using various circuit design methods based on compressing the signals received from the monitored facilities using modified Hamming codes (Hsiao codes). Conclusion. The conditions for detecting errors at the outputs of self-dual digital devices established in this paper allow practically synthesising self-checking computer systems with improved checkability as compared with conventional approaches to their implementation.

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30

Lewis, S. H., R. Ramachandran, and W. M. Snelgrove. "Indirect testing of digital-correction circuits in analog-to-digital converters with redundancy." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 42, no. 7 (1995): 437–45. http://dx.doi.org/10.1109/82.401166.

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31

Bhaskar Chatterjee, Manoj Sachdev, and A. Keshavarzi. "DFT for delay fault testing of high-performance digital circuits." IEEE Design and Test of Computers 21, no. 3 (2004): 248–58. http://dx.doi.org/10.1109/mdt.2004.10.

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32

Jaramaitis, A. A., and R. I. Šeinauskas. "Method to Determine Detecting Vector for Digital Circuits Random Testing." IFAC Proceedings Volumes 19, no. 5 (1986): 509–12. http://dx.doi.org/10.1016/s1474-6670(17)59852-3.

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33

Shaer, B., D. Landis, and A. Al-Arian. "Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8, no. 6 (2000): 750–54. http://dx.doi.org/10.1109/92.902271.

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34

Al-Qutayri, Mahmoud A., and Peter R. Shepherd. "Application of Dynamic Supply Current Monitoring to Testing Mixed-Signal Circuits." VLSI Design 5, no. 3 (1997): 223–40. http://dx.doi.org/10.1155/1997/47423.

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This paper applies the time-domain testing technique and compares the effectiveness of transient voltage and dynamic power supply current measurements in detecting faults in CMOS mixed-signal circuits. The voltage and supply current (iDDT) measurements are analyzed by three methods to detect the presence of a fault, and to establish which measurement achieves higher confidence in the detection. Catastrophic, soft and stuck-at single fault conditions were introduced to the circuit-under-test (CUT). The time-domain technique tests a mixed-signal CUT in a unified fashion, thereby eliminating the need to partition the CUT into separate analogue and digital modules.

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35

Danladi, A., and C. Nathan. "DESIGN CONSTRUCTION AND TESTING OF AN INCREMENTAL SHAFT ENCODER FOR MEASUREMENT OF ANGULAR VELOCITY OF A SHAFT." Continental J. Engineering Sciences 3 (July 22, 2008): 21–29. https://doi.org/10.5281/zenodo.833665.

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An incremental shaft encoder has been designed and developed for measuring angular velocity of a shaft. The construction of the circuit was achieved using disc of a plastic materials with fifteen slots. Infrared light emitting diode, comparator, photo transistor (sensor), 555 timer, encoder, decoder, differentiator (control logic) and display. Bubble resolver was also included in the circuits to eliminate ± 1 counting error which is inherent in most digital device. The incremental shaft encoder designed and developed was able to measure maximum speed of 2500rpm and the corresponding frequency of 625Hz of a 12V dc motor after proper calibration in laboratory and testing. The circuit designed and developed is a prototype of an industrial incremental shaft encoder, which replace the imported incremental shaft encoders because of its reliability.

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Flores, Maria da Glória, Marcelo Negreiros, Luigi Carro, and Altamiro Susin. "A Noise Generator for Embedded Circuits Testing." Journal of Integrated Circuits and Systems 1, no. 1 (2004): 38–43. http://dx.doi.org/10.29292/jics.v1i1.253.

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This paper describes the implementation of a white noise generator to be used as the input signal of a new method for testing analog-to-digital converters (ADCs) and linear filters. The main goal of this method is to avoid the comparison of the output signal with a known and very precise reference input. The proposed white noise generator is easily implemented, with less complexity than others excitation signals. The use of noise as the input signal avoids concerns about the inherent noise present in all electronic systems. The testing technique is based on the analysis of the spectral response of the CUT output. This paper covers the generation of the excitation signal, as well as simulation and practical results are presented to prove the efficiency of the test method.

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Muthukrishnan, Prathiba, and Sivanantham Sathasivam. "A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits." Applied Sciences 12, no. 18 (2022): 9103. http://dx.doi.org/10.3390/app12189103.

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As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when technology is downscaled. Small delay defects (SDDs) and hidden delay defects (HDDs) are of critical importance in industries today since they are the source of most test escapes and reliability problems. Improving test quality and creating new test methods, algorithms, and test designs requires a comprehensive study of these delay defects. This article reviews the effect and impact of SDD and HDD in logic circuits. It also analyzes the relevant fault models, automatic test pattern generation (ATPG) methods, faster-than-at-speed testing (FAST), cell-aware (CA) based delay tests, test quality metrics, diagnosis of SDDs and HDDs, and commercially available Electronic Design Automation (EDA) tools. Based on the analysis, the benefits and drawbacks of several accessible approaches are addressed.

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Kiruthika K, Bhumika K Ramesh, Vishal G, Vivek N, and Jyoti. "IC Tester Using MATLAB." International Research Journal on Advanced Engineering and Management (IRJAEM) 2, no. 09 (2024): 2925–28. http://dx.doi.org/10.47392/irjaem.2024.0432.

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Digital IC tester is a microcontroller grounded circuitry that tests rainfall the IC is in good working condition or bad condition. In diligence, testing of the product is a major and precious and time-consuming process. Before making the whole system work, testing is mandatorily performed to avoid crimes and uninvited results. also, in educational institutions, while performing practical it's necessary to check the ICs whether it's good or bad before performing trials. numerous a small fault at IC position makes system perform incorrectly and produce wrong labors. The proposed system gives a cheap, small, movable and easy to handle IC tester that tests the ICs belonging to introductory gate circuitry similar as mux, demux, encoder, introductory gates. A new system for the high- speed test and characterization of digital intertwined circuit prototypes has been developed. It utilizes a especially developed off- chip processor and supporting circuitry that's to be included on the prototype chip to grease the test and characterization process. The processor administers the stoner- defined test, receives and stores the test results. The test procedure and data is downloaded to the processor’s memory through a standard interface. The supporting circuitry receives the test data serially from the processor, applies it to the named circuit within the IC, collects and reformat the test results and shoot it to the processor. It also includes a high- frequence configurable timepiece creator to be used for performance characterization of the prototyped circuits.

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Holmes, Jim, A. Matthew Francis, Ian Getreu, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Journal of Microelectronics and Electronic Packaging 13, no. 4 (2016): 143–54. http://dx.doi.org/10.4071/imaps.527.

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In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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Francis, A. Matthew, Jim Holmes, Nick Chiolino, Matthew Barlow, Affan Abbasi, and H. Alan Mantooth. "High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, HiTEC (2016): 000242–48. http://dx.doi.org/10.4071/2016-hitec-242.

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Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

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El-Mahlawy, Mohamed, Ahmed Abd El-Wahab, and Al-Emam Ragab. "FPGA implementation of the portable automatic testing system for digital circuits." International Conference on Electrical Engineering 6, no. 6 (2008): 1–24. http://dx.doi.org/10.21608/iceeng.2008.34333.

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Shirol, Suhas B., and Rajashekar B. Shettar. "A Comparative Study of Low Power Testing Techniques for Digital Circuits." International Journal of Advanced Research in Computer Science and Software Engineering 7, no. 7 (2017): 412. http://dx.doi.org/10.23956/ijarcsse/v7i7/0180.

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In recent years, with fast growth of mobile communication and portable computing systems, design for low power has become the challenge in the field of Digital VLSI design. The main focus of the paper is to make a comparative study of low power Linear Feedback Shift Register (LFSR) architecture such as Built In Self Test (BIST), it has been often seen that during test mode process the power consumed is much higher, when compared to that of normal mode process test as there is high switching activity in the nodes of Circuit Under Test(CUT) during testing.

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43

Kurmas, Zachary. "Improving student performance using automated testing of simulated digital logic circuits." ACM SIGCSE Bulletin 40, no. 3 (2008): 265–70. http://dx.doi.org/10.1145/1597849.1384342.

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Matakias, Sotiris, Yiorgos Tsiatouhas, Angela Arapoyanni, and Themistoklis Haniotakis. "A current monitoring technique for I testing in digital integrated circuits." Integration 50 (June 2015): 48–60. http://dx.doi.org/10.1016/j.vlsi.2015.01.005.

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Rahardja, S., and B. J. Falkowski. "Application of linearly independent arithmetic transform in testing of digital circuits." Electronics Letters 35, no. 5 (1999): 363. http://dx.doi.org/10.1049/el:19990280.

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Pasquinelli, Rossan, and SestoS Giovanni. "4481628 Apparatus for testing dynamic noise immunity of digital integrated circuits." Microelectronics Reliability 25, no. 6 (1985): 1175–76. http://dx.doi.org/10.1016/0026-2714(85)90641-9.

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Ramakrishna S , Rajashekhar B Shettar, Suhas Shirol ,. "Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems." Journal of Electrical Systems 20, no. 2 (2024): 2747–62. http://dx.doi.org/10.52783/jes.2053.

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This paper presents a novel approach to optimizing power usage in scalable Built-In Self-Test (BIST) controllers. While BIST mechanisms are crucial for maintaining the reliability of digital circuits, they can be excessively power-hungry during testing phases, particularly in applications where energy consumption is a concern. We propose an innovative architecture incorporating reversible logic gates and circuits to overcome this challenge. Reversible logic is renowned for its low power consumption as it retains information. By integrating reversible logic into our architecture, we can significantly reduce power usage during test cycles, making it an ideal solution for scalable systems ranging from 8 to 32 bits. Our trials showed substantial power savings compared to traditional BIST approaches without sacrificing test coverage or efficiency. Our research provides new opportunities to develop energy-efficient testing methods for digital circuits, contributing to broader efforts in sustainable electronics design.

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Alamgir, Arbab, Abu Khari A’ain, Norlina Paraman, and Usman Ullah Sheikh. "Adaptive random testing with total cartesian distance for black box circuit under test." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 2 (2020): 720. http://dx.doi.org/10.11591/ijeecs.v20.i2.pp720-726.

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<p>Testing and verification of digital circuits is of vital importance in electronics industry. Moreover, key designs require preservation of their intellectual property that might restrict access to the internal structure of circuit under test. Random testing is a classical solution to black box testing as it generates test patterns without using the structural implementation of the circuit under test. However, random testing ignores the importance of previously applied test patterns while generating subsequent test patterns. An improvement to random testing is Antirandom that diversifies every subsequent test pattern in the test sequence. Whereas, computational intensive process of distance calculation restricts its scalability for large input circuit under test. Fixed sized candidate set adaptive random testing uses predetermined number of patterns for distance calculations to avoid computational complexity. A combination of max-min distance with previously executed patterns is carried out for each test pattern candidate. However, the reduction in computational complexity reduces the effectiveness of test set in terms of fault coverage. This paper uses a total cartesian distance based approach on fixed sized candidate set to enhance diversity in test sequence. The proposed approach has a two way effect on the test pattern generation as it lowers the computational intensity along with enhancement in the fault coverage. Fault simulation results on ISCAS’85 and ISCAS’89 benchmark circuits show that fault coverage of the proposed method increases up to 20.22% compared to previous method.</p>

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Efanov, Dmitry V., Tatiana S. Pogodina, Nazirjan M. Aripov, et al. "Combinational Circuits Testing Based on Hsiao Codes with Self-Dual Check Functions." Computation 13, no. 1 (2025): 15. https://doi.org/10.3390/computation13010015.

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This paper investigates the features of using modified Hamming codes, which are also known as Hsiao codes. Self-checking digital devices are proposed to be implemented with calculations testing using two diagnostic signs. These signs indicate that the functions (there are functions that describe check bits) belong to the class of self-dual Boolean functions and also belong to the codewords of Hsiao codes (these are codes with an odd column of weights). The authors have established that all check functions can be self-dual for a certain number of the Hsiao codes’ data symbols. Such codes can be used in the synthesis of concurrent error-detection circuits by two diagnostic signs. The paper describes the structure of an organization for a concurrent error-detection circuit based on Hsiao codes with self-dual check functions. Some experimental results are presented on the synthesis of self-checking devices using the proposed methodology. The controllability of the structure and the number of test combinations both increased. Hsiao codes can be effectively used with self-dual check functions in the synthesis of self-checking digital devices.

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Chen, Shiyu, Zhidong He, Suhwan Choi, and Igor V. Novosselov. "Characterization of Inkjet-Printed Digital Microfluidics Devices." Sensors 21, no. 9 (2021): 3064. http://dx.doi.org/10.3390/s21093064.

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Digital microfluidics (DMF) devices enable precise manipulation of small liquid volumes in point-of-care testing. A printed circuit board (PCB) substrate is commonly utilized to build DMF devices. However, inkjet printing can be used to fabricate DMF circuits, providing a less expensive alternative to PCB-based DMF designs while enabling more rapid design iteration cycles. We demonstrate the cleanroom-free fabrication process of a low-cost inkjet-printed DMF circuit. We compare Kapton and polymethyl methacrylate (PMMA) as dielectric coatings by measuring the minimal droplet actuation voltage for a range of actuation frequencies. A minimum actuation voltage of 5.6 V was required for droplet movement with the PMMA layer thickness of 0.2 μm and a hydrophobic layer of 0.17 μm. Significant issues with PMMA dielectric breakdown were observed at actuation voltages above 10 V. In comparison, devices that utilized Kapton were found to be more robust, even at an actuation voltage up to 100 V.

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