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Dissertations / Theses on the topic 'Thickness gage'

Author: Grafiati

Published: 30 May 2022

Last updated: 31 July 2025

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1

Десятниченко, Алексей Владимирович. "Электромагнитно-акустический толщиномер для контроля металлоизделий с диэлектрическими покрытиями". Thesis, НТУ "ХПИ", 2015. http://repository.kpi.kharkov.ua/handle/KhPI-Press/17117.

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Диссертация на соискание ученой степени кандидата технических наук по специальности 05.11.13 – приборы и методы контроля и определения состава веществ. – Национальный технический университет "Харьковский политехнический институт", Харьков, 2015. Диссертация посвящена решению важной научно-практической задачи обеспечения ультразвукового контроля толщины металлоизделий электромагнитно-акустическим методом при наличии диэлектрических покрытий (зазоров) толщиной до 10 мм. В работе выполнен анализ существующих акустических методов и устройств для измерения толщины, которые широко используются в от

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2

Десятніченко, Олексій Володимирович. "Електромагнітно-акустичний товщиномір для контролю металовиробів з діелектричними покриттями". Thesis, НТУ "ХПІ", 2015. http://repository.kpi.kharkov.ua/handle/KhPI-Press/17045.

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Дисертація на здобуття наукового ступеня кандидата технічних наук за спеціальністю 05.11.13 – прилади і методи контролю та визначення складу речовин. – Національний технічний університет "Харківський політехнічний інститут", Харків, 2015. Дисертація присвячена вирішенню важливої науково-практичної задачі, яка полягає у забезпеченні ультразвукового контролю товщини металовиробів електромагнітно-акустичним методом при наявності діелектричних покриттів (зазорів) товщиною до 10 мм. У роботі виконано аналіз існуючих акустичних методів і пристроїв для вимірювання товщини, розглянуті основні їх пер

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3

Bhuiya, Md Omar F. "DESIGN AND OPTIMIZATION OF A STRIPLINE RESONATOR SENSOR FOR MEASUREMENT OF RUBBER THICKNESS IN A MOVING WEB." University of Akron / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=akron1164650416.

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4

Berggren, Amanda. "Long-term results regarding healing andcomplications after 25-gauge pars planavitrectomy for large full-thickness macularholes." Thesis, Örebro universitet, Institutionen för medicinska vetenskaper, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:oru:diva-93339.

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Introduction A full-thickness macular hole (FTMH) is a round deformity in the fovea that involve alllayers of the neurosensory retina. The condition is usually symptomatic and is associatedwith a decreased visual acuity (VA). Large FTMHs are associated to a larger decrease in VA.To treat FTMH pars plana vitrectomy (PPV) is performed to repair the hole. There aredifferent dimensions of instruments in PPV but limited information on the outcome usingeach dimension. Aim This study aims to assess the healing rate of large FTMHs after 25-gauge vitrectomy. Methods The study is a retrospective record

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5

Rennie, Michael. "Characterisation of molecular nitrogen implanted silicon for multiple thicknesses of gate oxide in a 0.5μm CMOS process". Thesis, University of Edinburgh, 1996. http://hdl.handle.net/1842/11294.

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The continuing scaling of CMOS devices for performance advantages has resulted in an accompanying thinning of the gate oxide insulator and an increase in the level of hot carrier effects for a fixed power supply voltage. Nitrogen incorporated into the gate oxide through the nitridation of silicon oxide from a gas source has been extensively studied to improve the robustness of devices to hot carrier effects. Although reduced growth rates have been observed with nitrided oxides, there has not been a comprehensive study of MOS device performance utilising this mechanism to selectively grow gate

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6

Ghosh, Atanu. "Optical and biomechanical factors, associated with near work and myopia." Thesis, Queensland University of Technology, 2012. https://eprints.qut.edu.au/63341/5/Atanu_Ghosh_Thesis.pdf.

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Near work may play an important role in the development of myopia in the younger population. The prevalence of myopia has also been found to be higher in occupations that involve substantial near work tasks, for example in microscopists and textile workers. When nearwork is performed, it typically involves accommodation, convergence and downward gaze. A number of previous studies have examined the effects of accommodation and convergence on changes in the optics and biometrics of the eye in primary gaze. However, little is known about the influence of accommodation on the eye in downward gaze.

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7

Civín, Adam. "Stanovení zbytkové napjatosti metodou vrtání otvoru s využitím MKP." Master's thesis, Vysoké učení technické v Brně. Fakulta strojního inženýrství, 2008. http://www.nusl.cz/ntk/nusl-228325.

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Residual state of stress in structural materials affect positively or negatively behaviour of component parts. The goal of this scope is not to deal with possible process of creating residual stresses neither about elimination of residual stress, but is focused how to determine magnitude of residual stress by hole-drilling method. We need to know magnitude and direction (angular orientation) of principal stresses to determine how residual state of stress affects behaviour of specimen. The most widely used modern technique for measuring residual stresses is hole-drilling strain-gage method. Hol

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8

Hénaux, Stéphane. "Contribution à l'amélioration des méthodes de caractérisation électrique des matériaux Silicium Sur Isolant (SOI)." Université Joseph Fourier (Grenoble), 1998. http://www.theses.fr/1998GRE10116.

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L'essor actuel des technologies soi est lie a la production d'un materiau de depart de qualite, dont le juge final est le comportement electrique des circuits integres. Cette these decrit des ameliorations et de nouvelles idees pour l'evaluation des proprietes electriques des materiaux soi. Les methodes presentees sont appliquees en priorite au nouveau materiau unibond. Nous donnons d'abord une vue d'ensemble des technologies soi et des methodes de caracterisation disponibles. Nous exposons ensuite notre contribution en commencant par la mesure electrique d'epaisseur du film de silicium dans u

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9

Yen, Yuh-Ren, and 顏育仁. "Study on Thickness Uniformity of Rapid Thermal Thin Gate Oxide." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/49874845421521239969.

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碩士<br>國立臺灣大學<br>電機工程學研究所<br>89<br>Two main topics are discussed in this thesis. One is about the electrical characteristics of MOS capacitor with non-uniform gate oxide and the other is the uniformity improvement of gate oxide prepared by Rapid Thermal Processor(RTP). In order to investigate the influence of non-uniform gate oxide on the electrical characteristics of MOS capacitors, we intentionally grow a non-uniform thickness oxide by putting a quartz ring beneath the monitored wafer. A thinner oxide is grown on the regions contacted with the quartz ring since heat is conducted by

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10

Fan, Kung Ming, and 范恭鳴. "Multiple-gate-oxide-thickness Process Development by NH3 Plasma Nitridation." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/61329243704455919302.

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碩士<br>長庚大學<br>半導體研究所<br>90<br>Abstract According to the ITRS prediction, the equivalent oxide thickness (EOT) will be scale to 0.9-1.4nm in the 90nm technology node. As the oxide thickness less than 3nm, the gate leakage current and boron penetration through oxide are more seriously. Replace the SiO2 by High-k dielectric materials and nitrogen implant in the silicon surface or dielectrics are the most popular approaches to overcome these two issues. SOC is the current trend for the future CMOS processes, but it increases the process complexity, one of these challenges i

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Kun, Huang Tao, and 黃道坤. "The impact of poly gate sidewall oxide thickness on MOSFET’s gate-induced drain leakage behavior." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/12981841264445016012.

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碩士<br>長庚大學<br>電子工程研究所<br>93<br>The leakage in the drain region is a crucial issue for scaling of the MOSFET. The off-state gate-induced drain leakage (GIDL) current is one of the major contributors to the overall MOSFET leakage. GIDL is induced by band-to-band tunneling (BTBT) effect in the depletion region and generated in the gate to drain overlap region with high electric field. GIDL leakage is a function of many process parameters such as spacer material, spacer width, gate oxide thickness, doped concentration; anneal temperature, and poly re-oxidation conditions etc. Devices used in this

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12

Sharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ac.in/handle/2005/3489.

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Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally eﬃcient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, eﬃcient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide th

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Sharan, Neha. "Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry." Thesis, 2014. http://etd.iisc.ernet.in/2005/3489.

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Compact Models are the physically based accurate mathematical description of the cir-cuit elements, which are computationally eﬃcient enough to be incorporated in circuit simulators so that the outcome becomes useful for the circuit designers. As the multi-gate MOSFETs have appeared as replacements for bulk-MOSFETs in sub-32nm technology nodes, eﬃcient compact models for these new transistors are required for their successful utilization in integrated circuits. Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide th

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14

Chen, Hui-Yen, and 陳慧燕. "Improved the uniformity of Gate Oxide Thickness of High Voltage Devices." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/41002387735940640452.

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碩士<br>國立交通大學<br>工學院半導體材料與製程設備學程<br>101<br>The purpose of this study is to improve the uniformity of gate oxide thickness in 0.15μm high voltage device. Thermal oxidation process was used to fabricate this gate oxide. During oxidation process, gate oxide needs overcome the thermal stress distribution caused from the Si substrate. In this paper, the uniformity of gate oxide thickness was improved through investigation of the position of the wafer, oxidation method, annealing method and “sacrifice etching” of oxide layer. Change annealing method from RTA to furnace can improve this issue but

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15

Huang, Yao-De, and 黃耀德. "Study on the Relation Between Gate Thickness and Molding Parameters Using PVT Diagram." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/wstz2h.

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碩士<br>中原大學<br>機械工程研究所<br>106<br>Before the product enters actual mass production, a production tool trial is often required, because a brand new mold is difficult to produce the finished product of the required specifications directly. At this time, the molded product usually has some disparities with the expected size. Traditionally, these disparities are supplemented by factory’s experienced workers relying on their personal experience to adjust the molding parameters or modify the mold appropriately instead of regulating product quality in a standardized process and this process takes a lot

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16

Wu, Jiunn-Pey, and 吳俊沛. "Analysis on Gate-Oxide Thickness Dependence of Hot-Carrier- Induced Degradation in Submicrometer LDD nMOSFET's." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/44807502258254042698.

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碩士<br>國立交通大學<br>電子研究所<br>83<br>In this thesis, gate-oxide thickness dependecnce of hot- carrier-induced degradation is investigated for LDD nMOSFET' s. It is shown that a thinner gate oxide LDD nMOSFET's causes larger drain current degradation under the same bias stress condition. However, it has been reported that a thinner gate oxide conventional nMOSFET shows smaller degradation. Since the dominant degradation mechanism for the LDD device differ from the conventiona

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Yu, Li-Wei, and 游禮維. "A Study on Channel Thickness Effect of Double-Gate Polycrystalline-Silicon Junctionless Thin-Film Transistors." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/4j5mnq.

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碩士<br>國立中山大學<br>電機工程學系研究所<br>107<br>In this paper, the effect of different channel thickness on the Junctionless Thin Film Transistor is discussed, and also the upper gate and double gate are concerned. The channel thickness is divided into three channel thicknesses: 10nm, 8nm and 5nm. According to the measurement results, the thickness of the 10 nm channel is not controlled by upper gate, and it is necessary to use the double gate to improve. Therefore, the 8 nm and 5 nm channel thickness would be discussed subsequently in the later discussion. The on/off characteristics, the drain-induced ba

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Tan, Yu-De, and 談昱德. "Effect of Gate Metal Thickness on The 2-State Characteristics of MOS Structure with Ultrathin Oxide." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/59894679539440376075.

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碩士<br>國立臺灣大學<br>電機工程學研究所<br>103<br>In this work, we study the effect of the thickness of gate metal on the characteristics of Metal-Oxide-Semiconductor capacitor (MOSCAP) device with ultrathin oxide layer. The embedded Dynamic Random Access Memory (eDRAM) becomes more and more important in semiconductor industry with application of System on Chip (SoC) and Application Specific Integrated Circuit (ASIC). The pattern of the device is a long strap connected to a square contact pad in this work, which is designed for higher gate resistance with ultrathin gate metal. The device has two operation mo

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Lee, Jung-Ming, and 李榮明. "A optimization study of SiNx film thickness and uniformity for TFT-LCD isolation gate by Taguchi Method." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/42740817691997066339.

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碩士<br>國立高雄第一科技大學<br>機械與自動化工程研究所<br>102<br>Time of high-pixel , high-resolution of large-size LCD panel is coming . LCD process technology requires constant innovation , in order to achieve large output , low cost and product quality optimization . Taguchi method has been extensively improves the single product , quality optimization in this field . However , the influence factors of the product process are two or more than two quality characteristics , and the design parameter only relying on professional engineer’s experience of choosing the control factors . It is easy to cause uncertainty

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Chang, Po-Kai, and 張博凱. "Determination of Ultrathin Gate Oxide Thickness (＜2.0 nm) Using Low Dissipation Factor Regions of C－V Measurements." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/97235682268489213225.

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碩士<br>臺灣大學<br>電子工程學研究所<br>95<br>With the expeditious development of modern CMOS technology, the equivalent oxide thickness (EOT) of gate dielectric is systematically downscaled into the ultrathin range (＜2.0 nm) and becomes a key factor in the precise determination of many device parameters, such as electron/hole mobility, oxide charge density, interface trap density, breakdown field strength, etc. However, C－V curves of ultrathin oxides near the accumulation region show a disposition to roll off abruptly due to exponentially-increasing leakage current and series resistance; hence the two-f

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Yang, Deng-Wei, and 楊登偉. "Local Strain Effects on pMOSFETs by Different Gate Structures and Nitride Thicknesses." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/08928482545974405925.

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碩士<br>逢甲大學<br>產業研發碩士班<br>96<br>Strain is a kind of mobility enhancement technologies for device performance enhancement. It is considered as a simplest method to improve device characteristics and easy to integrated in modern process. We have investigated the local strain effects on pMOSFETs with the traditional poly-Si、poly-SiGe and the stack of poly-SiGe and amorphous Si (poly-stack) gates by different thicknesses of silicon nitride (SiN) capping. In this experiment, the traditional poly-Si gated pMOSFETs with SiN capping present the better performance. Introducing compressive strain by PECV

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Liang, Chia-Lin, and 梁佳琳. "Effects of Tiny Grain and Channel Thickness on the Performance Variation of the Vertical Gate SONOS Memory Cell." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/75226969442873966923.

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碩士<br>國立交通大學<br>電子工程學系電子研究所<br>104<br>Three-dimensional (3D) memory structure has been the main trend of NAND flash memory in industry. The grain size, grain number, and grain boundaries of the poly-Si channel may affects the memory characteristics. In this work, we fabricated the vertical gate thin film transistor SONOS (VG TFT SONOS) devices with different grain sizes and different channel thicknesses, and study their on the fresh state, Fowler-Nordeim (FN) programming and erasing speed, and the variations. In the previous research, we found that the grain boundary containing lots of trappi

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Teo, L. W., Van Tai Ho, M. S. Tay, et al. "Dependence of nanocrystal formation and charge storage/retention performance of a tri-layer memory structure on germanium concentration and tunnel oxide thickness." 2003. http://hdl.handle.net/1721.1/3799.

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The effect of germanium (Ge) concentration and the rapid thermal oxide (RTO) layer thickness on the nanocrystal formation and charge storage/retention capability of a trilayer metal-insulator-semiconductor device was studied. We found that the RTO and the capping oxide layers were not totally effective in confining the Ge nanocrystals in the middle layer when a pure Ge middle layer was used for the formation of nanocrystals. From the transmission electron microscopy and secondary ion mass spectroscopy results, a significant diffusion of Ge atoms through the RTO and into the silicon (Si) substr

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Chen, Chi-Chih, and 陳吉智. "The characteristics of n-channel lateral diffused metal-oxide-semiconductor (LDMOS) field effect transistors with different gate oxide thickness." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/85234330301321003481.

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碩士<br>國立成功大學<br>微電子工程研究所碩博士班<br>92<br>In this thesis, the characteristics of Lateral Diffused Metal-Oxide-Semi- conductor (LDMOS) field effect transistors based on 1.0μm technology with different gate oxide thickness are investigated. 　　The characteristics of LDMOS transistors with different gate oxide thicknesses are examined. The temperature dependence of device parameters is studied under elevated operating temperature. Constant voltage stress is performed on devices with different gate oxide thickness to see the impact of gate oxide thickness on parameter degradation. Different degradation

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Cheng, Chieh-Fang, and 鄭捷方. "Effect of Oxide Thickness on The Two-State haracteristics in MIS(p) Tunnel Diode with Ultra-thin Metal Surrounded Gate." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/upbe79.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>107<br>In this thesis, ultrathin metal surrounded gate Metal-Insulator-Semiconductor (UTMSG MIS) tunnel diodes with various oxide thicknesses were fabricated. The transient two-state characteristics of targeting devices can be magnified. In chapter 2, the electrical characteristics and transient two-state characteristics in the UTMSG MIS and the regular gate Metal-Insulator-Semiconductor (RG MIS) tunnel diodes with various oxide thickness were demonstrated that the UTMSG MIS devices can maintain larger two-state current window within appropriate oxide thicknesses ra

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Lin, Wen-yan, and 林文彥. "Study of Reliability in the Local Strained n-channel MOSFET by Different Thickness of Poly-Si Gate and Nitride Capping Layer." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/55965071158238051577.

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碩士<br>國立雲林科技大學<br>電子與資訊工程研究所<br>93<br>In this study, a local strained n-channel MOSFET has been fabricated by utilizing a heavy mechanical stress SiNx-capping layer, and further improves the carrier mobility to achieve the purpose of high operation speed. We investigate the local strained effects on nMOSFETs by different Poly-Si and nitride thicknesses. Therefore, the study focuses on the relation of reliability and strain. After hot carrier stress, the devices with 250-nm SiNx show the largest ΔVth shift and transconductance degradation whereas 170-nm devices show better reliability. As we su

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Lee, Kun-Yu, та 李昆育. "The Study of Sub-Nanometer Equivalent Oxide Thickness of MBE and ALD Grown High κ Gate Dielectrics on Silicon and In0.53Ga0.47As Substrates". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/32141202705303068548.

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博士<br>國立清華大學<br>材料科學工程學系<br>96<br>Metal oxide semiconductor (MOS) capacitors that incorporated high κ materials of HfO2 and Al2O3 are fabricated by Molecular beam epitaxy (MBE) and Atomic layer deposition (ALD) on Silicon and InGaAs substrates. The achievements in this work are to minimize the thickness of the interfacial layer at oxide/semiconductor and attain sub-nanometer equivalent oxide thickness (EOT) value in the MOS diodes. In Silicon phase, MBE grown high κ dielectrics of Al2O3 and HfO2 are employed as templates to suppress effectively the oxide/Si interfacial layer formation during t

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Wang, Jia-Yi, and 王家儀. "A Study on Channel Thickness Effect of Double-Gate Polycrystalline-Silicon Thin-Film Transistors for Application of Monolithic Three-Dimensional Integrated Circuits." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/vbmjke.

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碩士<br>國立中山大學<br>電機工程學系研究所<br>107<br>In this thesis, we successfully fabricated the double gate thin film transistors. In order to compare the device characteristic of single and double gate devices, we use different kinds of method to measure them. The double gate thin film transistors have better gate controllability than single gate devices. It can efficiently improve the on-state current, subthreshold swing, on/off ratio, and threshold voltage. And the different channel thickness devices of double gate have the relatively improved. The thinner channel thickness devices can have the off-stat

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LIN, WEN-CHIN, and 林文欽. "The Device Performance and Reliability Study on N-type Multi-Fin FinFET Structure by Adopting Metal Gate Multi Work Function Thickness Engineering." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/wyhsn6.

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Chen, Ying-ya, and 陳映雅. "The Investigation of Characteristic for N-Type FinFETs with Different Thicknesses of TaN Metal Gate and Different Fin Numbers." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/72275242059061517411.

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碩士<br>國立高雄大學<br>電機工程學系碩士班<br>103<br>With the scaling of device, FinFET has considered as one of the most promising options for future devices to replace planner MOSFETs. N-type tri-gate FinFETs were utilized in this work. The FinFET devices with various TaN thicknesses were used at first to study the influence on electric characteristics and reliability. It could be observed that the thick TaN device shows the larger threshold voltage, drain saturation current and better subthreshold swing for the flash device. After hot carrier injection, it could be found that the thicker TaN device shows la

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