Relevant bibliographies by topics / Thin Film Transistor (TFT)

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Academic literature on the topic 'Thin Film Transistor (TFT)'

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Published: 4 June 2021
Last updated: 13 June 2025

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Journal articles on the topic "Thin Film Transistor (TFT)"

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Pokharel, Peshal, and Lalita Shrestha. "Fabrication of Transparent Thin Film for Application of Thin Film Transistor (TFT) and Microelectronics." Himalayan Journal of Science and Technology 6, no. 1 (2022): 22–28. http://dx.doi.org/10.3126/hijost.v6i1.50645.

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A thin-film transistor (TFT) is a special type of metal-oxide-semiconductor field-effect transistor (MOSFET) made by coating an insulating substrate with layers of an active semiconductor layer, metallic contacts, and the dielectric layer. FET transistors consist of three main components: source, gate, and drain. The main objective of the work is to fabricate the channel component by growing the ZnO nanostructure on the glass substrate using spin coating and spray pyrolysis methods. Thin films of zinc oxide (ZnO) were deposited on glass substrates by spin coating techniques from a precursor solution containing zinc acetate, ethanol and hydroxide of ammonia. After deposition, the films were centrifuged and evaporated. The application of spray pyrolysis has been used to deposit a wide variety of thin films, which are used in a variety of devices, such as solar cells, sensors and solid oxide fuel cells. It has been observed that the properties of the deposited thin films often depend on the preparation conditions; concentration levels of the precursor solution, coating time, electrical and optical properties of the glass substrate, etc. The average resistance of the sheet of samples F1, F5, F52, and F57 was 8.7 Ω, 9.14 Ω, 8.9 Ω and 9.42 Ω and of the samples, F2, F29, F39, and F53 were 9.5 Ω, 9.3 Ω, 9.9 Ω, 10.0 Ω respectively, at a growth temperature of 3400C. The thin films of ZnO were found to be highly transparent between the visible and near-infrared regions of the electromagnetic spectrum and the transmission of each sample decreases with three layers of ZnO seed layer. The decrease in the transmission of the samples confirms the coating of the ZnO seed layer on it. This work has demonstrated that transparent thin films can be fabricated using local techniques developed from locally available materials using less harmful chemical reagents such as zinc acetate. Such fabricated films are optically absorptive and inherently transmissive, further suggesting that they can be used as a channel material in thin film transistors.
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Park, Hyun-Woo, Sera Kwon, Aeran Song, Dukhyun Choi, and Kwun-Bum Chung. "Dynamics of bias instability in the tungsten-indium-zinc oxide thin film transistor." Journal of Materials Chemistry C 7, no. 4 (2019): 1006–13. http://dx.doi.org/10.1039/c8tc03585g.

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The key to full understanding of the degradation mechanism of oxide thin film transistors (Ox-TFTs) by gate bias stress is to investigate dynamical changes of the electron trap site at the channel region while a real-time gate bias is applied to the actual thin film transistor (TFT) structure.
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Wager, John F. "(Invited) Thin-Film Transistor Accumulation-Mode Modeling." ECS Meeting Abstracts MA2022-02, no. 35 (2022): 1257. http://dx.doi.org/10.1149/ma2022-02351257mtgabs.

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Analytical equations are developed for electrostatic assessment of accumulation-mode thin-film transistors (TFTs) so that potential, electric field, and accumulation layer free electron concentration profiles may be generated. Additionally, equations are derived for plotting TFT trap density versus surface potential, based on accurate extraction of the channel mobility as a function of gate voltage. A key factor in formulating these device physics equations is distinguishing between a ‘long-base’ or ‘short-base’ channel thickness. A ‘long-base’ (‘short-base’) channel thickness is defined to occur when the accumulation layer thickness (as calculated in the normal manner) is less than (greater than) the physical thickness of the channel layer. The electrostatic equations derived herein are applied to the analysis of two amorphous oxide semiconductor (AOS) TFTs with differing channel layers, i.e., a 40 nm amorphous indium gallium zinc oxide (a-IGZO) or a 7 nm amorphous indium zinc oxide (a-IZO). Application of these equations suggests that optimal TFT performance is obtained when the channel layer thickness is chosen to be similar to its Debye length. Estimated trap densities of these two AOS TFTs are found to be quite similar. Therefore, the superior mobility performance of the a-IZO TFT compared to the a-IGZO TFT is ascribed to the smaller effective mass of a-IZO, assuming that the maximum (no trapping) drift mobility in the channel is established by the thermally-limited diffusive mobility.
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Kong, Jiaquan, Chuan Liu, Xiaojie Li, et al. "Characteristics of Offset Corbino Thin Film Transistor: A Physical Model." Electronics 12, no. 10 (2023): 2195. http://dx.doi.org/10.3390/electronics12102195.

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Offset Corbino thin film transistor is a good candidate for high voltage thin film transistor (HVTFT) due to the uniform drain electric field distribution benefiting from the circular structure. The physical model of offset Corbino thin film transistor characteristics has yet to be clarified. In this study, Equations are derived to describe the current–voltage relations of Corbino TFT with offset at the drain or source sides. The influence of offset position and parameters on the saturation voltage and the saturation current was described quantitatively. Three-dimensional Computer-Aided Design simulation and experiment results verify the theoretical physical model. Our physical model provides design rules for high voltage offset Corbino TFT when considering the voltage tolerance and saturation current balance.
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Kang, Tsung-Kuei, Yu-Yu Lin, Han-Wen Liu, et al. "Improvements of Electrical Characteristics in Poly-Si Nanowires Thin-Film Transistors with External Connection of a BiFeO3 Capacitor." Membranes 11, no. 10 (2021): 758. http://dx.doi.org/10.3390/membranes11100758.

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By a sol–gel method, a BiFeO3 (BFO) capacitor is fabricated and connected with the control thin film transistor (TFT). Compared with a control thin-film transistor, the proposed BFO TFT achieves 56% drive current enhancement and 7–28% subthreshold swing (SS) reduction. Moreover, the effect of the proposed BiFeO3 capacitor on IDS-VGS hysteresis in the BFO TFT is 0.1–0.2 V. Because dVint/dVGS > 1 is obtained at a wide range of VGS, it reveals that the incomplete dipole flipping is a major mechanism to obtain improved SS and a small hysteresis effect in the BFO TFT. Experimental results indicate that sol-gel BFO TFT is a potential candidate for digital application.
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Tang, Yalun, and Kenji Nomura. "(Digital Presentation) Liquid-Metal-Printed Ultra-Thin ITO-Thin-Film Transistor." ECS Meeting Abstracts MA2022-02, no. 38 (2022): 2557. http://dx.doi.org/10.1149/ma2022-02382557mtgabs.

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Indium oxide is one of the promising materials for the n-channel layer for high-mobility oxide-TFT because of its high electron mobility characteristics due to the nature of spatially spread-In 5s orbital. However, excess carrier electrons in In-based channels cancel field-effect gate modulation and causes the formation of a short depletion layer. Moreover, it is challenging to reduce the electron density without the degradation of electron transport. Therefore, developing fully-depletion operated TFT using an ultra-thin channel is a straightforward strategy to demonstrate the high potential of In-based materials for TFT applications. In this work, we developed an ultra-thin tin-doped Indium oxide (ITO) channel (~ 1.9 nm-thick.) and demonstrated a fully-depleted ITO-TFT exhibiting high mobility of 27 cm2/Vs. The ITO channel was grown by a cost-effective vacuum-free liquid-metal-printing route at the maximum process temperature of ~ 200 oC in an ambient atmosphere. Post-thermal annealing in air made significant improvement of device characteristics originating from the reduction of shallow acceptor-like in-gap defects in the ITO channels, and high-performance n-channel ITO-TFT with a large on/off-current ratio of 109 and a sharp threshold slope was achieved. By controlling air-annealing temperature, we also successfully fabricated both enhancement and depletion-mode devices and developed a full signal swinged-oxide-NMOS inverter composed of a depletion-load structure.
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Jiang, Shijie, Lurong Yang, Chenbo Huang, Qianqian Chen, Wei Zeng, and Xiaojian She. "Understanding Illumination Effect on Saturation Behavior of Thin Film Transistor." Photonics 10, no. 3 (2023): 309. http://dx.doi.org/10.3390/photonics10030309.

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Thin film transistor (TFT) has been a key device for planal drive display technology, and operating the TFT device in a saturation regime is particularly important for driving the light emission at a stable current. Considering the light emission reaches the TFT planal, it is thereby meaningful to understand the effect of illumination on TFT saturation behavior in order to improve the stability of light emission. Through experiments and simulations, our study shows that the drift current of photogenerated carriers can follow a saturation behavior when the channel conductance is dominated by charges induced by gate bias rather than the charges generated by photons, and vice versa. The obtained device physics insights are beneficial for developing TFT technologies that can drive light emission at a stable current.
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Gu, Guiru, Yunfeng Ling, Runyu Liu, et al. "All-Printed Thin-Film Transistor Based on Purified Single-Walled Carbon Nanotubes with Linear Response." Journal of Nanotechnology 2011 (2011): 1–4. http://dx.doi.org/10.1155/2011/823680.

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We report an all-printed thin-film transistor (TFT) on a polyimide substrate with linear transconductance response. The TFT is based on our purified single-walled carbon nanotube (SWCNT) solution that is primarily consists of semiconducting carbon nanotubes (CNTs) with low metal impurities. The all-printed TFT exhibits a high ON/OFF ratio of around 103and bias-independent transconductance over a certain gate bias range. Such bias-independent transconductance property is different from that of conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) due to the special band structure and the one-dimensional (1D) quantum confined density of state (DOS) of CNTs. The bias-independent transconductance promises modulation linearity for analog electronics.
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Wager, John F. "40‐1: Invited Paper: Thin‐Film Transistor Modeling." SID Symposium Digest of Technical Papers 54, no. 1 (2023): 569–72. http://dx.doi.org/10.1002/sdtp.16621.

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A fresh approach to thin‐film transistor (TFT) modeling is offered, involving use of the Enz, Krummenacher, Vittoz (EKV) compact model. Accurate TFT simulation requires precise modeling of the drift mobility. The utility of this model is demonstrated via simulation of single‐and dual‐layer amorphous oxide semiconductor TFTs.
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Shuib, Umar Faruk, Khairul Anuar Mohamad, Afishah Alias, Tamer A. Tabet, Bablu K. Gosh, and Ismail Saad. "Modelling and Simulation Approach for Organic Thin-Film Transistors Using MATLAB Simulation." Advanced Materials Research 1107 (June 2015): 514–19. http://dx.doi.org/10.4028/www.scientific.net/amr.1107.514.

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As organic transistors are preparing to make improvements towards flexible and low cost electronics applications, the analytical models and simulation methods were demanded to predict the optimized performance and circuit design. In this paper, we investigated the analytical model of an organic transistor device and simulate the output and transfer characteristics of the device using MATLAB tools for different channel length (L) of the organic transistor. In the simulation, the Pool-Frenkel mobility model was used to represent the conductive channel of organic transistor. The different channel length has been simulated with the value of 50 μm, 10 μm and 5 μm. This research paper analyses the performance of organic thin film transistor (TFT) for top contact bottom gate device. From the simulation, drain current of organic transistor was increased as the channel length decreased. Other extraction value such sub-threshold and current on/off ratio is 0.41 V and 21.1 respectively. Thus, the simulation provides significant extraction of information about the behaviour of the organic thin film transistor.
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Dissertations / Theses on the topic "Thin Film Transistor (TFT)"

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Nominanda, Helinda. "Amorphous silicon thin film transistor as nonvolatile device." Texas A&M University, 2008. http://hdl.handle.net/1969.1/86004.

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n-channel and p-channel amorphous-silicon thin-film transistors (a-Si:H TFTs) with copper electrodes prepared by a novel plasma etching process have been fabricated and studied. Their characteristics are similar to those of TFTs with molybdenum electrodes. The reliability was examined by extended high-temperature annealing and gate-bias stress. High-performance CMOS-type a-Si:H TFTs can be fabricated with this plasma etching method. Electrical characteristics of a-Si:H TFTs after Co-60 irradiation and at different experimental stages have been measured. The gamma-ray irradiation damaged bulk films and interfaces and caused the shift of the transfer characteristics to the positive voltage direction. The field effect mobility, on/off current ratio, and interface state density of the TFTs were deteriorated by the irradiation process. Thermal annealing almost restored the original state's characteristics. Floating gate n-channel a-Si:H TFT nonvolatile memory device with a thin a- Si:H layer embedded in the SiNx gate dielectric layer has been prepared and studied. The hysteresis of the TFT's transfer characteristics has been used to demonstrate its memory function. A steady threshold voltage change between the "0" and "1" states and a large charge retention time of > 3600 s with the "write" and "erase" gap of 0.5 V have been detected. Charge storage is related to properties of the embedded a-Si:H layer and its interfaces in the gate dielectric structure. Discharge efficiencies with various methods, i.e., thermal annealing, negative gate bias, and light exposure, separately, were investigated. The charge storage and discharge efficiency decrease with the increase of the drain voltage under a dynamic operation condition. Optimum operating temperatures are low temperature for storage and higher temperature for discharge. a-Si:H metal insulator semiconductor (MIS) capacitor with a thin a-Si:H film embedded in the silicon nitride gate dielectric stack has been characterized for memory functions. The hysteresis of the capacitor's current-voltage and capacitance-voltage curves showed strong charge trapping and detrapping phenomena. The 9 nm embedded a-Si:H layer had a charge storage capacity six times that of the capacitor without the embedded layer. The nonvolatile memory device has potential for low temperature circuit applications.
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Hein, Moritz. "Organic Thin-Film Transistors." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-167894.

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Organic thin film transistors (OTFT) are a key active devices of future organic electronic circuits. The biggest advantages of organic electronics are the potential for cheep production and the enabling of new applications for light, bendable or transparent devices. These benefits are offered by a wide spectrum of various molecules and polymers that are optimized for different purpose. In this work, several interesting organic semiconductors are compared as well as transistor geometries and processing steps. In a cooperation with an industrial partner, test series of transistors are produced that are intensively characterized and used as a basis for later device simulation. Therefore, among others 4-point-probe measurements are used for a potential mapping of the transistor channel and via transfer line method the contact resistance is measured in a temperature range between 173 and 353 K. From later comparison with the simulation models, it appears that the geometrical resistance is actually more important for the transistor performance than the resistance of charge-carrier injection at the electrodes. The charge-carrier mobility is detailed evaluated and discussed. Within the observed temperature range a Arrhenius-like thermal activation of the charge- carrier transport is determined with an activation energy of 170 meV. Furthermore, a dependence of the electric field-strength of a Poole-Frenkel type is found with a Poole-Frenkel factor of about 4.9 × 10E−4 (V/m) −0.5 that is especially important for transistors with small channel length. With these two considerations, already a good agreement between device simulation and measurement data is reached. In a detailed discussion of the dependence on the charge-carrier density and from comparison with established the charge-carrier mobility models, an exponential density of states could be estimated for the organic semiconductor. However, reliability of OTFTs remains one of the most challenging hurdles to be understood and resolved for broad commercial applications. In particular, bias-stress is identified as the key instability under operation for numerous OTFT devices and interfaces. In this work, a novel approach is presented that allows controlling and significantly alleviating the bias-stress effect by using molecular doping at low concentrations. For pentacene as semiconductor and SiO2 as gate oxide, we are able to reduce the time constant of degradation by three orders of magnitude. The effect of molecular doping on the bias-stress is explained in terms of the shift of Fermi level and, thus, exponentially reduced proton generation at the pentacene/oxide interface. For transistors prepared in cooperation with the industrial partner, a second effect is observed that can be explained by a model considering a ferroelectric process in the dielectric and counteracts the bias-stress behavior.
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Dong, Hanpeng. "Microcrystalline silicon based thin film transistors fabricated on flexible substrate." Thesis, Rennes 1, 2015. http://www.theses.fr/2015REN1S173/document.

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Le travail de cette thèse porte sur le développement de transistors en couche mince (Thin Film Transistors, TFTs) à base de silicium microcristallin fabriqués sur un substrat flexible à très basse température (T&lt; 180 °C). La première partie de ce travail a consisté à étudier la stabilité électrique de ces TFTs. L'étude de la stabilité électrique des TFTs de type N fabriqués sur verre a montré que ces TFTs sont assez stables, la tension de seuil VTH ne se décale que de 1.2 V au bout de 4 heures de stress sous une tension de grille VGSstress= +50V et à une température T=50 °C. L'instabilité électrique de ces TFTs est principalement causée par le piégeage des porteurs dans l'isolant de grille. La deuxième étape de ce travail s'est concentrée sur l'étude du comportement de ces TFTs sous déformation mécanique. Ces TFTs sont soumis à un stress mécanique en tension et en compression. Le rayon de courbure minimum que les TFTs pouvaient supporter est r=1.5 mm en tension et en compression. La limitation de la déformation mécanique de ces TFTs est principalement due à la contrainte mécanique du nitrure de silicium utilisé comme isolant de grille des TFTs. Autrement dit, ces TFTs sont mécaniquement fiables et présentes une faible variation du courant ION, de l'ordre de 1%, même après 200 cycles de déformation mécanique. Ces résultats obtenus laissent entrevoir la possibilité de concevoir une électronique flexible pouvant être pliée en 2. Enfin, les TFTs sont fabriqués avec différents isolants de grille afin d'augmenter la mobilité d'effet de champ. Malheureusement, aucun isolant de grille utilisé dans ces études n'a permis d'augmenter la mobilité d'effet de champ sans dégrader la stabilité électrique des TFTs. Des études plus détaillées et des optimisations complémentaires sur ces isolants de grille sont nécessaires<br>This work deals with the development of microcrystalline silicon thin film transistors (TFTs) fabricated on flexible substrate at low temperature (T=180 °C). The first step of this work consists in studying the electrical stability of TFTs. The N-type TFTs fabricated on glass substrate are electrically stable under gate bias stress VGStress= +50V at T=50 °C. The threshold voltage shift (ΔVTH) was only 1.2 V during 4 hours. This electrical instability of TFTs is mainly due to carrier trapping inside the silicon nitride gate insulator. The second step of this work lies in the study of the mechanical behavior of the TFTs. Both tensile and compressive strains were applied on TFTs. The minimum curvature radius is r=1.5 mm for both tension and compression. The main limitation of TFTs comes from the mechanical strain εlimit of silicon nitride used as gate insulator of TFTs. Also, these TFTs are mechanically reliable: the variation of ION current was only 1% after 200 cycles mechanical bending. These results obtained open the way to the development of flexible electronics that can be folded in half.Finally, TFTs have been fabricated using different gate insulators in order to improve the mobility. Unfortunately, all the gate insulators used couldn’t improve mobility without sacrificing electrical stability of TFT. More detailed studies and complementary optimization of these gate insulators are necessary
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Ho, Tsz Kin. "Design of TFT circuit and touchscreen electronics /." View abstract or full-text, 2009. http://library.ust.hk/cgi/db/thesis.pl?ECED%202009%20HO.

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Zhu, Lei. "Modeling of a-Si:H TFT I-V Characteristics in the Forward Subthreshold Operation." Thesis, University of Waterloo, 2005. http://hdl.handle.net/10012/868.

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The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used as switching elements in LCD displays and large area matrix addressed senor arrays. In recent years, a-Si:H TFTs have been used as analog active components in OLED displays. However, a-Si:H TFTs exhibit a bias induced metastability. This problem causes both threshold voltage and subthreshold slope to shift with time when a gate bias is applied. These instabilities jeopardize the long-term performance of a-Si:H TFT circuits. Nevertheless a-Si:H TFTs show an exponential transfer characteristic in the subthreshold region. Moreover, the typical power consumptions for TFTs in the subthreshold region are in the order of nano-watts, thus making them suitable for low power design. For these reasons, a-Si:H TFT I-V characteristics in the forward subthreshold operation are investigated. First, we have derived the static and dynamic models of a-Si:H TFT in the forward subthreshold region. Second, we have verified our theoretical models with experimental results. Third, we have proven that a-Si:H TFT experiences no subthreshold slope degradation or threshold voltage shift in the forward subthreshold operation. Finally, we have studied a-Si:H TFT current mirror circuit applications. Measurements regarding the fidelity of current matching in the forward subthreshold region have been performed, and results are shown.
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Cheng, Xiang. "TFTs circuit simulation models and analogue building block designs." Thesis, University of Cambridge, 2018. https://www.repository.cam.ac.uk/handle/1810/271853.

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Building functional thin-film-transistor (TFT) circuits is crucial for applications such as wearable, implantable and transparent electronics. Therefore, developing a compact model of an emerging semiconductor material for accurate circuit simulation is the most fundamental requirement for circuit design. Further, unique analogue building blocks are needed due to the specific properties and non-idealities of TFTs. This dissertation reviews the major developments in thin-film transistor (TFT) modelling for the computer-aided design (CAD) and simulation of circuits and systems. Following the progress in recent years on oxide TFTs, we have successfully developed a Verilog-AMS model called the CAMCAS model, which supports computer-aided circuit simulation of oxide-TFTs, with the potential to be extended to other types of TFT technology families. For analogue applications, an accurate small signal model for thin film transistors (TFTs) is presented taking into account non-idealities such as contact resistance, parasitic capacitance, and threshold voltage shift to exhibit higher accuracy in comparison with the adapted CMOS model. The model is used to extract the zeros and poles of the frequency response in analogue circuits. In particular, we consider the importance of device-circuit interactions (DCI) when designing thin film transistor circuits and systems and subsequently examine temperature- and process-induced variations and propose a way to evaluate the maximum achievable intrinsic performance of the TFT. This is aimed at determining when DCI becomes crucial for a specific application. Compensation methods are reviewed to show examples of how DCI is considered in the design of AMOLED displays. Based on these design considerations, analogue building blocks including voltage and current references and differential amplifier stages have been designed to expand the analogue library specifically for TFT circuit design. The $V_T$ shift problem has been compensated based on unique circuit structures. For a future generation of application, where ultra low power consumption is a critical requirement, we investigate the TFT’s subthreshold operation through examining several figures of merit including intrinsic gain ($A_i$), transconductance efficiency ($g_m/I_{DS}$) and cut-off frequency ($f_T$). Here, we consider design sensitivity for biasing circuitry and the impact of device variations on low power circuit behaviour.
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Noring, Martin. "To automatically estimate the surface area coverage of carbon nanotubes on thin film transistors with image analysis : Bachelor’s degree project report." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-157168.

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This report discuss the developement of a MATLAB-based tool for the analysis ofsurface area coverage of carbon nanotube networks from atomic force microscopyimages. The tool was compared with a manual method and the conclusion was that ithas, at least, the same accuracy as the manual mehtod, and it needs much less time forthe analysis. The tool couldn’t analyze images of carbon nanotube networks if theimages were to noisy or the networks to dense. The tool can help in the research ofthin-film transistors with carbon nanotube networks as the semiconducting channelmaterial.
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Rossi, Leonardo. "Flexible oxide thin film transistors: fabrication and photoresponse." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/14542/.

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Gli ossidi amorfi semiconduttori (AOS) sono nuovi candidati per l’elettronica flessibile e su grandi aree: grazie ai loro legami prevalentemente ionici hanno una mobilità relativamente alta (µ > 10cm^2/Vs) anche nella fase amorfa. Transistor a film sottile (TFT) basati sugli AOS saranno quindi più performanti di tecnologie a base di a-Si e più economici di quelle a base di silicio policristallino. Essendo amorfi, possono essere depositati a basse temperature e su substrati polimerici, caratteristica chiave per l’elettronica flessibile e su grandi aree. Per questa tesi, diversi TFT sono stati fabbricati e caratterizzati nei laboratori del CENIMAT all’Università Nova di Lisbona sotto la supervisione del Prof. P. Barquinha. Questi dispositivi sono composti di contatti in molibdeno, un canale semiconduttivo di ossido di zinco, gallio e indio (IGZO) e un dielettrico composto da 7 strati alternati di SiO2 e SiO2+Ta2O5. Tutti i dispositivi sono stati depositati mediante sputtering su sostrati flessibili (fogli di PEN). Le misure tensione-corrente mostrano che i dispositivi mantengono alte mobilità (decine di 10cm^2/Vs) anche quando fabbricati a temperature inferiori a 200°C. Si è analizzato il funzionamento dei dispositivi come fototransistor rilevando la risposta alla luce ultravioletta e in particolare la loro responsività e spostamento della tensione di soglia in funzione della lunghezza d’onda incidente. Questi risultati consentono di formulare ipotesi sul comportamento dei dispositivi alla scala microscopica. In particolare, indicano che i) la mobilità del canale non è influenzata dall’illuminazione, ii) sia l'IGZO sia il Ta2O5 contribuiscono al processo di fotoconduttività e iii) il processo di fotogenerazione non è adiabatico. La tesi contiene inoltre una descrizione del processo di ricombinazione e presenta un’applicazione pratica di tali dispositivi in un circuito per RFID. Infine, esplora la possibilità di migliorarne la flessibilità e le prestazioni.
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Fratelli, Ilaria. "Flexible oxide thin film transistors: device fabrication and kelvin probe force microscopy analysis." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2017. http://amslaurea.unibo.it/13538/.

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I transistor a film sottile basati su ossidi amorfi semiconduttori sono ottimi candidati nell'ambito dell'elettronica su larga scala. Al contrario delle tecnologie basate su a-Si:H a poly-Si, gli AOS presentano un'elevata mobilità elettrica (m > 10 cm^2/ Vs) nonostante la struttura amorfa. Inoltre, la possibilità di depositare AOS a basse temperature e su substrati polimerici, permette il loro impiego nel campo dell'elettronica flessibile. Al fine di migliorare questa tecnologia, numerosi TFT basati su AOS sono stati fabbricati durante 4 mesi di attività all'Università Nova di Lisbona. Tutti i transistor presentano un canale formato da a-GIZO, mentre il dielettrico è stato realizzato con due materiali differenti: Parylene (organico) e 7 strati alternati di SiO2 e SiO2 + Ta2O5. I dispositivi sono stati realizzati su substrati flessibili sviluppando una nuova tecnica per la laminazione e la delaminazione di fogli di PEN su supporto rigido. L'ottimizzazione del processo di fabbricazione ha permesso la realizzazione di dispositivi che presentano caratteristiche paragonabili a quelle previste per TFT costruiti su substrati rigidi (m = 35.7 cm^2/Vs; VON = -0.10 V; S = 0.084 V/dec). Al Dipartimento di Fisica dell'UNIBO, l'utilizzo del KPFM ha permesso lo studio a livello microscopico delle prestazioni presentate dai dispositivi analizzati. Grazie a questa tecnica di indagine, è stato possibile analizzare l'impatto delle resistenze di contatto sui dispositivi meno performanti e identificare l'esistenza di cariche intrappolate nei TFT basati su Parylene. Gli ottimi risultati ottenuti dall'analisi KPFM suggeriscono un futuro impiego di questa tecnica per lo studio del legame tra stress meccanico e degradazione elettrica dei dispositivi. Infatti, la comprensione dei fenomeni microscopici dovuti alla deformazione strutturale sarà un passaggio indispensabile per lo sviluppo dell'elettronica flessibile.
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Dosev, Dosi Konstantinov. "Fabrication, characterisation and modelling of nanocrystalline silicon thin-film transistors obtained by hot-wire chemical vapour deposition." Doctoral thesis, Universitat Politècnica de Catalunya, 2003. http://hdl.handle.net/10803/6324.

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Hot-wire chemical vapour deposition (HWCVD) is a promising technique that permits polycrystalline silicon films with grain size of nanometers to be obtained at high deposition rates and low substrate temperatures. This material is expected to have better electronic properties than the commonly used amorphous hydrogenated silicon (a-Si:H).<br/><br/>In this work, thin-film transistors (TFTs) were fabricated using nanocrystalline hydrogenated silicon film (nc-Si:H), deposited by HWCVD over thermally oxidized silicon wafer. The employed substrate temperature during the deposition process permits inexpensive materials as glasses or plastics to be used for various applications in large-area electronics. The deposition rate was about one order of magnitude higher than in other conventionally employed techniques. The deposited nc-Si:H films show good uniformity and reproducibility. The films consist of vertically grown columnar grains surrounded by amorphous phase. The columnar grains are thinner at the bottom (near the oxide interface) and thicker at the top of the film. Chromium layer was evaporated over the nc-Si:H in order to form drain and source contacts. Using photolithography techniques, two types of samples were fabricated. The first type (simplified) was with the chromium contacts directly deposited over the intrinsic nc-Si:H layer. No dry etching was involved in the fabrication process of this sample. The transistors on the wafer were not electrically separated from each other. Doped n+ layer was incorporated at the drain and source contacts in the second type of samples (complete samples). Dry etching was employed to eliminate the nc-Si:H between the TFTs and to isolate them electrically from each other.<br/><br/>The electrical characteristics of both types of nc-Si:H TFTs were similar to a-Si:H based TFTs. Nevertheless, some significant differences were observed in the characteristics of the two types of samples. The increasing of the off-current in the simplified structure was eliminated by the n+ layer in the second type of samples. This led to the improving of the on/off ratio. The n+ layer also eliminated current crowding of the output characteristics. On the other hand, the subthreshold slope, the threshold voltage and the density of states were slightly deteriorated in the samples with incorporated n+ layer. Surface states created by the dry etching could be a possible reason. Other cause could be a bad quality of the nc-Si:H/SiO2 interface. The TFTs with incorporated n+ contact layer and electrically separated on the wafer were used in the further studies of stability and device modelling.<br/><br/>The nc-Si:H TFTs were submitted under prolonged positive and negative gate bias stress in order to study their stability. We studied the influence of the stressing time and voltage on the transfer characteristics, threshold voltage, activation energy and density of states. The threshold voltage increased under positive gate bias stress and decreased under negative gate bias stress. After both positive and negative stresses, the threshold voltage recovered its initial values without annealing. This behaviour indicated that temporary charge trapping in the channel/gate insulator interface is the responsible process for the device performance under stress. Measurements of space-charge limited current confirmed that bulk states were not affected by the positive nor by negative stress.<br/>Analysis of the activation energy and the density of states gave more detailed information about the physical processes taking place during the stress. Typical drawback of the nc-Si:H films grown by HWCVD with tungsten (W) filament is the bad quality of the bottom, initially grown, interfacial layer. It is normally amorphous and porous. We assume that this property of the nc-Si:H film is determining for charge trapping and the consecutive temporary changes of the TFT's characteristics. On the other hand, the absence of defect-state creation during the gate bias stress demonstrates that the nc-Si:H films did not suffer degradation under the applied stress conditions. <br/><br/>The electrical characteristics and the operational regimes of the nc-Si:H TFTs were studied in details in order to obtain the best possible fit using the Spice models for a-Si:H and poly-Si TFTs existing until now. The analysis of the transconductance gm showed behaviour typical for a-Si:H TFTs at low gate voltages. In contrast, at high gate voltages unexpected increasing of gm was observed, as in poly-Si TFTs. Therefore, it was impossible to fit the transfer and output characteristics with the a-Si:H TFT model neither with poly-Si TFT model.<br/>We performed numerical simulations using the Silvaco's Atlas simulator of semiconductor devices in order to understand the physical parameters, responsible for the device behaviour. The simulations showed that the reason for this behaviour is the density of acceptor-like states, which situates the properties of nc-Si:H TFTs between the amorphous and the polycrystalline transistors. Taking into account this result, we performed analysis of the concentrations of the free and the trapped carriers in nc-Si:H layer. It was found that nc-Si:H operates in transitional regime between above-threshold and crystalline-like regimes. This transitional regime was predicted earlier, but not experimentally observed until now. Finally, we introduced new equations and three new parameters into the existing a-Si TFTs model in order to account for the transitional regime. The new proposed model permits the shapes of the transconductance, the transfer and the output characteristics to be modelled accurately.
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Books on the topic "Thin Film Transistor (TFT)"

1

Hakumaku toranjisuta gijutsu no subete: Kōzō, tokusei, seizō purosesu kara jisedai TFT made = Thin film transistor. Kōgyō Chōsakai, 2007.

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Tsukada, Toshihisa. TFT/LCD: Liquid-crystal displays addressed by thin-film transistors. Gordon and Breach, 1996.

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Aoki, Hitoshi. Dynamic characterization of a-Si TFT-LCD pixels. Hewlett-Packard Laboratories, Technical Publications Department, 1996.

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Tsukada, Toshihisa. TFT/LCD: Liquid-crystal displays addressed by thin-film transistors. Gordon and Breach, 1996.

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Taiwan de jing tan hao: Tai Ri Han TFT shi ji zhi zheng. Shi bao wen hua chu ban qi ye gu fen you xian gong si, 2004.

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Bo mo jing ti guan (TFT) zhen lie zhi zao ji shu. Fu dan da xue chu ban she, 2007.

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Maeda, Shigenobu. Teishōhi denryoku kōsoku MOSFET gijutsu: Takesshō shirikon TFT fukagata SRAM to SOI debaisu. Sipec, 2002.

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International Workshop on Active Matrix Liquid Crystal Displays (2001 Tokyo, Japan). AM-LCD 01: Digest of technical papers : 2001 International Workshop on Active Matrix Liquid Crystal Displays, TFT technologies and related materials, July 11-13, 2001, Kogakuin University, Tokyo, Japan. Japan Society of Applied Physics, 2001.

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International Workshop on Active Matrix Liquid Crystal Displays (1999 Tokyo, Japan). AM-LCD 99: Digest of technical papers :1999 International Workshop on Active Matrix Liquid Crystal Displays, TFT technologies and related materials, July 14-16, 1999, Kogakuin University, Tokyo, Japan. Japan Society of Applied Physics, 1999.

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Symposium, on Thin Film Transistor Technologies (8th 2006 Cancun Mexico). Thin film transistor technology 8. Electrochemical Society, 2006.

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Book chapters on the topic "Thin Film Transistor (TFT)"

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Ishihara, Ryoichi. "Poly-Si TFT Structures." In Thin Film Transistors. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_15.

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Choi, Byong-Deok, Inhwan Lee, and Oh-Kyong Kwon. "Poly-Si TFT Drivers." In Thin Film Transistors. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_22.

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Kuo, Yue. "a-Si:H TFT Structures." In Thin Film Transistors. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_4.

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Kuo, Yue. "Poly-Si TFT for non-LCD Applications." In Thin Film Transistors. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_24.

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Flewitt, Andrew J., and William I. Milne. "a-Si:H TFT Thin Film and Substrate Materials." In Thin Film Transistors. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_2.

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Higashi, Seiichiro. "Process Integration Issues for Poly-Si TFT Fabrication." In Thin Film Transistors. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_21.

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Kuo, Yue. "Plasma Etching in a-Si:H TFT Array Fabrication." In Thin Film Transistors. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_7.

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Matsumura, Hideki, Akira Izumi, and Atsushi Masuda. "Catalytic Chemical Vapor Deposition of a-Si:H TFT." In Thin Film Transistors. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_9.

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Brotherton, S. D. "Poly-Si TFT Performance." In Introduction to Thin Film Transistors. Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-00002-2_8.

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Kuo, Yue. "Deposition of Dielectric Thin Films for a-Si:H TFT." In Thin Film Transistors. Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_6.

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Conference papers on the topic "Thin Film Transistor (TFT)"

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Colli, A. "Thin film transistors on nanostructured layers prepared by nanowire lithography." In 2009 Compact Thin-Film Transistor Modeling for Circuit Simulation (TFT/CTFT). IEEE, 2009. http://dx.doi.org/10.1109/ctft.2009.5379875.

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Ahnood, Arman. "Effect of VT shift and contact resistance on mobility of TFTs." In 2009 Compact Thin-Film Transistor Modeling for Circuit Simulation (TFT/CTFT). IEEE, 2009. http://dx.doi.org/10.1109/ctft.2009.5379837.

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Hsieh, Chien-Wen. "Hybrid inorganic/organic semiconductors for high performance organic-based TFTs." In 2009 Compact Thin-Film Transistor Modeling for Circuit Simulation (TFT/CTFT). IEEE, 2009. http://dx.doi.org/10.1109/ctft.2009.5379839.

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Nassar, Christopher James, Joseph Revelli, Robert John Bowman, and Carlo Kosik Williams. "A charge based compact model for enhancement mode PMOSFETs." In 2009 Compact Thin-Film Transistor Modeling for Circuit Simulation (TFT/CTFT). IEEE, 2009. http://dx.doi.org/10.1109/ctft.2009.5379840.

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Su, J. S., and James B. Kuo. "Modeling the floating-body-effect-induced drain current behavior of PD SOI NMOS device via SPICE BJT/MOS model approach." In 2009 Compact Thin-Film Transistor Modeling for Circuit Simulation (TFT/CTFT). IEEE, 2009. http://dx.doi.org/10.1109/ctft.2009.5379842.

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"Organizing committee." In 2009 Compact Thin-Film Transistor Modeling for Circuit Simulation (TFT/CTFT). IEEE, 2009. http://dx.doi.org/10.1109/ctft.2009.5379861.

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Bauza, M. "Modeling of light and bias stress induced defects in nc-Si:H TFTs." In 2009 Compact Thin-Film Transistor Modeling for Circuit Simulation (TFT/CTFT). IEEE, 2009. http://dx.doi.org/10.1109/ctft.2009.5379863.

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"2009 second international workshop on compact thin-film transistor (TFT) modeling for circuit simulation." In 2009 Compact Thin-Film Transistor Modeling for Circuit Simulation (TFT/CTFT). IEEE, 2009. http://dx.doi.org/10.1109/ctft.2009.5379873.

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Rasheed, Iranmanesh, Li, Andrenko, and Wang. "Heart rate/impulse monitoring using autonomous PVDF-integrated dual-gate thin-film transistor." In 2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT). IEEE, 2016. http://dx.doi.org/10.1109/cad-tft.2016.7785041.

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Li, Iranmanesh, Rasheed, Ou, Chen, and Wang. "Subthreshold operation of PVDF-integrated dual- gate thin-film transistor for tactile sensing." In 2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT). IEEE, 2016. http://dx.doi.org/10.1109/cad-tft.2016.7785059.

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