Bibliographies: 'Threshold Inverter Quantization'

1

Zghoul, Fadi Nessir, Wafaa Migdadi, and Mamoun Al-Mistarihi. "Optimizing power consumption in novel electrical design for single ended comparator circuit." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 1 (2025): 208. http://dx.doi.org/10.11591/ijece.v15i1.pp208-223.

Full text

Abstract:

Contemporary society electronic technology has evolved into a pivotal component across various facets of our lives. Its indispensability is particularly evident in the advancement of medical, agricultural, industrial, and other sectors. As this technology continues to play a crucial role, optimizing its performance in terms of speed, accuracy, and energy consumption becomes paramount. This paper introduces a novel electrical design for the threshold inverter quantization comparator circuit aiming to meet the evolving demands of modern electronic applications. The proposed design enhances the classic threshold inverter quantization comparator’s performance by significantly reducing its power consumption. Through rigorous mathematical analysis and simulation results it is demonstrated that the proposed comparator design achieves a remarkable 50% reduction in power consumption compared to the conventional threshold inverter quantization comparator. Subsequently the newly devised design is applied to the construction of a 4-bit flash analog-to-digital converter using 0.35 μm complementary metal–oxide–semiconductor (CMOS) technology.

APA, Harvard, Vancouver, ISO, and other styles

2

Zghoul, Fadi Nessir, Wafaa Migdadi, and Mamoun Al-Mistarihi. "Optimizing power consumption in novel electrical design for single ended comparator circuit." International Journal of Electrical and Computer Engineering (IJECE) 15, no. 1 (2025): 208–23. https://doi.org/10.11591/ijece.v15i1.pp208-223.

Full text

Abstract:

Contemporary society electronic technology has evolved into a pivotalcomponent across various facets of our lives. Its indispensability isparticularly evident in the advancement of medical, agricultural, industrial,and other sectors. As this technology continues to play a crucial role,optimizing its performance in terms of speed, accuracy, and energyconsumption becomes paramount. This paper introduces a novel electricaldesign for the threshold inverter quantization comparator circuit aiming tomeet the evolving demands of modern electronic applications. The proposeddesign enhances the classic threshold inverter quantization comparator’sperformance by significantly reducing its power consumption. Throughrigorous mathematical analysis and simulation results it is demonstrated thatthe proposed comparator design achieves a remarkable 50% reduction inpower consumption compared to the conventional threshold inverterquantization comparator. Subsequently the newly devised design is appliedto the construction of a 4-bit flash analog-to-digital converter using 0.35 μmcomplementary metal–oxide–semiconductor (CMOS) technology.

APA, Harvard, Vancouver, ISO, and other styles

3

Gurjar, Mamta, and Shyam Akashe. "Design Low Power Encoder for Threshold Inverter Quantization Based Flash ADC Converter." International Journal of VLSI Design & Communication Systems 4, no. 2 (2013): 83–90. http://dx.doi.org/10.5121/vlsic.2013.4208.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Agrawal, Niket, та Roy Paily. "A threshold inverter quantization based folding and interpolation ADC in 0.18 μm CMOS". Analog Integrated Circuits and Signal Processing 63, № 2 (2009): 273–81. http://dx.doi.org/10.1007/s10470-009-9388-5.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Fang, Na, Jiabin Wang, Yong Jiang, and Wanyong Liang. "Design of Pseudorandom Signal Generator Based on a Dual Memristor Chaotic System." Journal of Physics: Conference Series 2747, no. 1 (2024): 012001. http://dx.doi.org/10.1088/1742-6596/2747/1/012001.

Full text

Abstract:

Abstract This paper constructs a pseudo-random signal generator based on a dual memristor chaotic system. Firstly, the chaotic characteristics of the dual memristor chaotic system were explored through theoretical analysis and MATLAB numerical simulation, and a MULTISIM simulation circuit for the dual memristor chaotic system was constructed. Then, based on the threshold decision quantization method, a pseudorandom signal generator quantization circuit is formed by connecting an inverter amplifier and a hysteresis comparator on the output side of the analog circuit. Finally, the randomness of the pseudorandom sequence is discussed by NIST test and correlation analysis. The analysis results show that the pseudorandom sequence generated by the pseudo-random signal generator based on the dual memristor chaotic system exhibits good randomness.

APA, Harvard, Vancouver, ISO, and other styles

6

Bhatia, Veepsa, Neeta Pandey, and Asok Bhattacharyya. "Modelling and Design of Inverter Threshold Quantization based Current Comparator using Artificial Neural Networks." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 1 (2016): 320. http://dx.doi.org/10.11591/ijece.v6i1.8700.

Full text

Abstract:

<p>Performance of a MOS based circuit is highly influenced by the transistor dimensions chosen for that circuit. Thus, proper dimensioning of the transistors plays a key role in determining its overall performance. While choosing the dimension is critical, it is equally difficult, primarily due to complex mathematical formulations that come into play when moving into the submicron level. The drain current is the most affected parameter which in turn affects all other parameters. Thus, there is a constant quest to come up with techniques and procedure to simplify the dimensioning process while still keeping the parameters under check. This study presents one such novel technique to estimate the transistor dimensions for a current comparator structure, using the artificial neural networks approach. The approach uses Multilayer perceptrons as the artificial neural network architectures. The technique involves a two step process. In the first step, training and test data are obtained by doing SPICE simulations of modelled circuit using 0.18μm TSMC CMOS technology parameters. In the second step, this training and test data is applied to the developed neural network architecture using MATLAB R2007b.</p>

APA, Harvard, Vancouver, ISO, and other styles

7

Bhatia, Veepsa, Neeta Pandey, and Asok Bhattacharyya. "Modelling and Design of Inverter Threshold Quantization based Current Comparator using Artificial Neural Networks." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 1 (2016): 320. http://dx.doi.org/10.11591/ijece.v6i1.pp320-329.

Full text

Abstract:

<p>Performance of a MOS based circuit is highly influenced by the transistor dimensions chosen for that circuit. Thus, proper dimensioning of the transistors plays a key role in determining its overall performance. While choosing the dimension is critical, it is equally difficult, primarily due to complex mathematical formulations that come into play when moving into the submicron level. The drain current is the most affected parameter which in turn affects all other parameters. Thus, there is a constant quest to come up with techniques and procedure to simplify the dimensioning process while still keeping the parameters under check. This study presents one such novel technique to estimate the transistor dimensions for a current comparator structure, using the artificial neural networks approach. The approach uses Multilayer perceptrons as the artificial neural network architectures. The technique involves a two step process. In the first step, training and test data are obtained by doing SPICE simulations of modelled circuit using 0.18μm TSMC CMOS technology parameters. In the second step, this training and test data is applied to the developed neural network architecture using MATLAB R2007b.</p>

APA, Harvard, Vancouver, ISO, and other styles

8

Sankar, P. A. Gowri, and G. Sathiyabama. "A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application." International Journal of Engineering Research in Africa 19 (October 2015): 19–36. http://dx.doi.org/10.4028/www.scientific.net/jera.19.19.

Full text

Abstract:

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

APA, Harvard, Vancouver, ISO, and other styles

9

Saman, B., R. H. Gudlavalleti, R. Mays, J. Chandy, Evan Heller, and F. Jain. "3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs." International Journal of High Speed Electronics and Systems 29, no. 01n04 (2020): 2040014. http://dx.doi.org/10.1142/s0129156420400145.

Full text

Abstract:

Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.

APA, Harvard, Vancouver, ISO, and other styles

10

Thai, Hong-Hai, Cong-Kha Pham, and Duc-Hung Le. "Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process." Sensors 23, no. 1 (2022): 76. http://dx.doi.org/10.3390/s23010076.

Full text

Abstract:

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.

APA, Harvard, Vancouver, ISO, and other styles

Contents

Academic literature on the topic 'Threshold Inverter Quantization'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Journal articles on the topic "Threshold Inverter Quantization"

Conference papers on the topic "Threshold Inverter Quantization"