Relevant bibliographies by topics / Through silicon via, airgap interconnects

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Conference papers

Academic literature on the topic 'Through silicon via, airgap interconnects'

Author: Grafiati
Published: 4 June 2021
Last updated: 3 February 2022

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Through silicon via, airgap interconnects.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Through silicon via, airgap interconnects"

1

Zhu, Jian, Yuanwei Yu, Fang Hou, and Chen Chen. "Through-silicon via technologies for interconnects in RF MEMS." Microsystem Technologies 16, no. 7 (January 7, 2010): 1045–49. http://dx.doi.org/10.1007/s00542-009-1013-0.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Kamto, A., Y. Liu, L. Schaper, and S. L. Burkett. "Reliability study of through-silicon via (TSV) copper filled interconnects." Thin Solid Films 518, no. 5 (December 2009): 1614–19. http://dx.doi.org/10.1016/j.tsf.2009.07.151.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Wang, Teng, Kejll Jeppson, Lilei Ye, and Johan Liu. "Carbon-Nanotube Through-Silicon Via Interconnects for Three-Dimensional Integration." Small 7, no. 16 (June 21, 2011): 2313–17. http://dx.doi.org/10.1002/smll.201100615.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Tiwari, Chandra S. "Conformal EL Ni Fill in Through-Silicon-Via for 3D Interconnects." ECS Transactions 41, no. 43 (December 16, 2019): 73–80. http://dx.doi.org/10.1149/1.4717505.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Jiang, Di, Wei Mu, Si Chen, Yifeng Fu, Kjell Jeppson, and Johan Liu. "Vertically Stacked Carbon Nanotube-Based Interconnects for Through Silicon Via Application." IEEE Electron Device Letters 36, no. 5 (May 2015): 499–501. http://dx.doi.org/10.1109/led.2015.2415198.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Shin, Young-min, Yong-Kweon Kim, Seung-Ki Lee, Hyogeun Shin, Il-Joo Cho, and Jae-Hyoung Park. "Microprobe electrode array with individual interconnects through substrate using silicon through-glass via." Sensors and Actuators B: Chemical 290 (July 2019): 336–46. http://dx.doi.org/10.1016/j.snb.2019.03.143.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Leib, Jüergen, Florian Bieck, Ulli Hansen, Kok-Kheong Looi, Ha-Duong Ngo, Volker Seidemann, Dzafir Shariff, et al. "Tapered Through-Silicon-Via Interconnects for Wafer-Level Packaging of Sensor Devices." IEEE Transactions on Advanced Packaging 33, no. 3 (August 2010): 713–21. http://dx.doi.org/10.1109/tadvp.2009.2026950.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Hernandez, George A., Daniel Martinez, Stephen Patenaude, Charles Ellis, Michael Palmer, and Michael Hamilton. "Through Si Vias Using Liquid Metal Conductors for Re-workable 3D Electronics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (January 1, 2013): 001343–57. http://dx.doi.org/10.4071/2013dpc-wp13.

Full text
Abstract:
This paper describes the design and fabrication of liquid metal interconnects (vias) for 2.5D and 3D integration. The liquid metal is gallium indium eutectic with a melting temperature of approximately 15.7°C that is introduced into via openings of a silicon interposer. This liquid interconnect technology can be integrated with existing interposer technologies, such as capacitors and traditional (solid metal) through-silicon vias (TSVs). In addition, liquid metal interconnects can better accommodate thermal stresses and provide re-workability in case of chip failure. Our research efforts are focused on the integration of multi-chip modules using liquid metal interconnects. Our study encompasses Direct Current (D.C.) measurements and failure analysis using snake and comb structures at low temperature (10 degrees Kelvin) to slightly above room temperature (300 degrees Kelvin). The snake and comb structure allows us to measure electrical shorts and opens, as well as provide estimates of via yield and allows additional information for determination of possible failure mechanisms. In order to make electrical contact to the liquid metal interconnect interposer from both the top and bottom, test coupons have been fabricated with arrays of large numbers of vias. The interposer structure consists of a thin (200 um thick) silicon wafer with via holes filled with liquid metal. The test coupon consists of bottom and top silicon die with a thickness of 500 um. The bottom wafer incorporates a 2 um-thick daisy-chain metallization and 100 um copper tall vias, which are electrically isolated from each other and the underlying Si by patterned AL-X dielectric. The top wafer incorporates an array of 80 um tall, electroplated copper pillars and top daisy-chain metallization. Liquid metal containment mechanisms and structures have also been investigated. In our presentation we will describe the design, fabrication and characterization of this re-workable interposer with liquid metal interconnects. We will present D.C. resistance and X-ray imagery of the liquid metal filled via. In addition, we will provide failure analysis of via yield per chip.
APA, Harvard, Vancouver, ISO, and other styles
9

Sun, Shuangxi, Wei Mu, Michael Edwards, Davide Mencarelli, Luca Pierantoni, Yifeng Fu, Kjell Jeppson, and Johan Liu. "Vertically aligned CNT-Cu nano-composite material for stacked through-silicon-via interconnects." Nanotechnology 27, no. 33 (July 7, 2016): 335705. http://dx.doi.org/10.1088/0957-4484/27/33/335705.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Nageswara Rao, K., G. Veerendra Nath, and K. Hari Kishore. "Crosstalk noise minimization in novel through silicon via structures." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 56. http://dx.doi.org/10.14419/ijet.v7i2.8.10325.

Full text
Abstract:
In recent trends, through silicon via (TSV) is essential Technologies for 3-D IC integration because of its short interconnects length and high interconnect density. Beyond the existing structure of TSV, this paper provides a novel structure to investigate the crosstalk effect and same is simulated by using a SPICE simulator and 3-D field solver. The structure of the TSV comprises of copper surrounding by insulating liner, and silicon substrate. In existing structures, silicon dioxide (Sio2) is used as insulating liner because of its material compatibility with silicon substrate. Several researches provide the problem of using Sio2 is due to its high dielectric constant; as a consequence delay will increase. Therefore, Sio2 is not appropriate for high performance applications. In this work, a novel TSV structure is reported to improve the TSV performance which uses poly-propylene polymer liner instead of oxide liner. Signal TSV is enclosed by using a poly-propylene liner and amid the analysis with doping region is created around the ground TSV. For comparison purposes, conventional and proposed TSV structures are simulated. The proposed TSV’s structure simulation results in 30% decrease in crosstalk over existing TSV structures.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Through silicon via, airgap interconnects"

1

Kumar, Vachan. "Modeling and optimization approaches for benchmarking emerging on-chip and off-chip interconnect technologies." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/54280.

Full text
Abstract:
Modeling approaches are developed to optimize emerging on-chip and off-chip electrical interconnect technologies and benchmark them against conventional technologies. While transistor scaling results in an improvement in power and performance, interconnect scaling results in a degradation in performance and electromigration reliability. Although graphene potentially has superior transport properties compared to copper, it is shown that several technology improvements like smooth edges, edge doping, good contacts, and good substrates are essential for graphene to outperform copper in high performance on-chip interconnect applications. However, for low power applications, the low capacitance of graphene results in 31\% energy savings compared to copper interconnects, for a fixed performance. Further, for characterization of the circuit parameters of multi-layer graphene, multi-conductor transmission line models that account for an alignment margin and finite width of the contact are developed. Although it is essential to push for an improvement in chip performance by improving on-chip interconnects, devices, and architectures, the system level performance can get severely limited by the bandwidth of off-chip interconnects. As a result, three dimensional integration and airgap interconnects are studied as potential replacements for conventional off-chip interconnects. The key parameters that limit the performance of a 3D IC are identified as the Through Silicon Via (TSV) capacitance, driver resistance, and on-chip wire resistance on the driver side. Further, the impact of on-chip wires on the performance of 3D ICs is shown to be more pronounced at advanced technology nodes and when the TSV diameter is scaled down. Airgap interconnects are shown to improve aggregate bandwidth by 3x to 5x for backplane and Printed Circuit Board (PCB) links, and by 2x for silicon interposer links, at comparable energy consumption.
APA, Harvard, Vancouver, ISO, and other styles
2

Asimakopoulos, Panagiotis. "Optimizing the integration and energy efficiency of through silicon via-based 3D interconnects." Thesis, University of Newcastle upon Tyne, 2011. http://hdl.handle.net/10443/1328.

Full text
Abstract:
The aggressive scaling of CMOS process technology has been driving the rapid growth of the semiconductor industry for more than three decades. In recent years, the performance gains enabled by CMOS scaling have been increasingly challenged by highlyparasitic on-chip interconnects as wire parasitics do not scale at the same pace. Emerging 3D integration technologies based on vertical through-silicon vias (TSVs) promise a solution to the interconnect performance bottleneck, along with reduced fabrication cost and heterogeneous integration. As TSVs are a relatively recent interconnect technology, innovative test structures are required to evaluate and optimise the process, as well as extract parameters for the generation of design rules and models. From the circuit designer’s perspective, critical TSV characteristics are its parasitic capacitance, and thermomechanical stress distribution. This work proposes new test structures for extracting these characteristics. The structures were fabricated on a 65nm 3D process and used for the evaluation of that technology. Furthermore, as TSVs are implemented in large, densely interconnected 3D-system-on-chips (SoCs), the TSV parasitic capacitance may become an important source of energy dissipation. Typical low-power techniques based on voltage scaling can be used, though this represents a technical challenge in modern technology nodes. In this work, a novel TSV interconnection scheme is proposed based on reversible computing, which shows frequencydependent energy dissipation. The scheme is analysed using theoretical modelling, while a demonstrator IC was designed based on the developed theory and fabricated on a 130nm 3D process.
APA, Harvard, Vancouver, ISO, and other styles
3

Thadesar, Paragkumar A. "Interposer platforms featuring polymer-enhanced through silicon vias for microelectronic systems." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53572.

Full text
Abstract:
Novel polymer-enhanced photodefined through-silicon via (TSV) and passive technologies have been demonstrated for silicon interposers to obtain compact heterogeneous computing and mixed-signal systems. These technologies include: (1) Polymer-clad TSVs with thick (~20 µm) liners to help reduce TSV losses and stress, and obtain optical TSVs in parallel for interposer-to-interposer long-distance communication; (2) Polymer-embedded vias with copper vias embedded in polymer wells to significantly reduce the TSV losses; (3) Coaxial vias in polymer wells to reduce the TSV losses with controlled impedance; (4) Antennas over polymer wells to attain a high radiation efficiency; and (5) High-Q inductors over polymer wells. Cleanroom fabrication and characterization of the technologies have been demonstrated. For the fabricated polymer-clad TSVs, resistance and synchrotron x-ray diffraction (XRD) measurements have been demonstrated. High-frequency measurements up to 170 GHz and time-domain measurements up to 10 Gbps have been demonstrated for the fabricated polymer-embedded vias. For the fabricated coaxial vias and inductors, high-frequency measurements up to 50 GHz have been demonstrated. Lastly, for the fabricated antennas, measurements in the W-band have been demonstrated.
APA, Harvard, Vancouver, ISO, and other styles
4

Kim, Dae Hyun. "Through-silicon-via-aware prediction and physical design for multi-granularity 3D integrated circuits." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/43642.

Full text
Abstract:
The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.
APA, Harvard, Vancouver, ISO, and other styles
5

Jiang, Tengfei, Laura Spinella, Jay Im, Rui Huang, and Paul S. Ho. "Processing Effect on Via Extrusion for Through-Silicon Vias (TSVs) in 3D Interconnects: A Comparative Study of Two TSV Structures." Universitätsbibliothek Chemnitz, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-207262.

Full text
Abstract:
In this paper, processing effects of electroplating and post- plating annealing on via extrusion are investigated. The study is based on two TSV structures with identical geometry but different processing conditions. Via extrusion, stress and material behaviors of the TSV structures were first compared. Electron backscatter diffraction (EBSD) and time-of-flight secondary ion mass spectroscopy (TOF-SIMS) were used to characterize the microstructure of TSVs and the additives incorporated during electroplating. Based on the results, processing effects on via extrusion and its mechanism are discussed, including grain growth, local plasticity, and diffusional creep.
APA, Harvard, Vancouver, ISO, and other styles
6

Zaveri, Jesal. "Electrical and fluidic interconnect design and technology for 3D ICS." Thesis, Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39550.

Full text
Abstract:
For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.
APA, Harvard, Vancouver, ISO, and other styles
7

Han, Ki Jin. "Electromagnetic modeling of interconnections in three-dimensional integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29642.

Full text
Abstract:
Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Madhavan Swaminathan; Committee Member: Andrew E. Peterson; Committee Member: Emmanouil M. Tentzeris; Committee Member: Hao-Min Zhou; Committee Member: Saibal Mukhopadhyay. Part of the SMARTech Electronic Thesis and Dissertation Collection.
APA, Harvard, Vancouver, ISO, and other styles
8

Weerasekera, Roshan. "System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits." Doctoral thesis, Stockholm : Informations- och kommunikationsteknik, Kungliga Tekniska högskolan, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-9586.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Knechtel, Johann. "Interconnect Planning for Physical Design of 3D Integrated Circuits." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-143635.

Full text
Abstract:
Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation
Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich
APA, Harvard, Vancouver, ISO, and other styles
10

林佳漢. "A Study of Fast Filling Through Silicon Via Interconnects Using Solder Reflow Technology." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/10398012608912908435.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Through silicon via, airgap interconnects"

1

Wang, Xiao-Peng, Wen-sheng Zhao, and Wen-Yan Yin. "Electrothermal modelling of through silicon via (TSV) interconnects." In 2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS). IEEE, 2010. http://dx.doi.org/10.1109/edaps.2010.5683011.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Marcoux, By Phil. "Title: Through Silicon Via (TSV) technology creates electro-optical interfaces." In 2012 IEEE Optical Interconnects Conference. IEEE, 2012. http://dx.doi.org/10.1109/oic.2012.6224436.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Zhaohui Chen, Zhicheng Lv, XueFang Wang, and Yong. "Modeling of electromigration of the through silicon via interconnects." In High Density Packaging (ICEPT-HDP). IEEE, 2010. http://dx.doi.org/10.1109/icept.2010.5582771.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Civale, Yann, Stefaan Van Huylenbroeck, Augusto Redolfi, Wei Guo, Khashayar Babaei Gavan, Patrick Jaenen, Antonio La Manna, Gerald Beyer, Bart Swinnen, and Eric Beyne. "Via-middle through-silicon via with integrated airgap to zero TSV-induced stress impact on device performance." In 2013 IEEE 63rd Electronic Components and Technology Conference (ECTC). IEEE, 2013. http://dx.doi.org/10.1109/ectc.2013.6575759.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Cui, Jiang-Peng, Xiao-Long Xu, and Wen-Yan Yin. "Electrothermal investigation on through silicon multi-walled carbon nanotube via interconnects." In 2010 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS). IEEE, 2010. http://dx.doi.org/10.1109/edaps.2010.5682991.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Xu, Dongfang, and Zheyao Wang. "Structure design of through silicon via interconnects and growth of carbon nanotubes." In 2015 16th International Conference on Electronic Packaging Technology (ICEPT). IEEE, 2015. http://dx.doi.org/10.1109/icept.2015.7236774.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Wen-Sheng Zhao, Jun Hu, and Wen-Yan Yin. "Sensitivity analysis of through-silicon via (TSV) interconnects for 3-D ICs." In 2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS). IEEE, 2011. http://dx.doi.org/10.1109/edaps.2011.6213744.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Han, Ki Jin, and Madhavan Swaminathan. "Polarization mode basis functions for modeling insulator-coated through-silicon via (TSV) interconnections." In 2009 IEEE Workshop on Signal Propagation on Interconnects (SPI). IEEE, 2009. http://dx.doi.org/10.1109/spi.2009.5089849.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Kitada, Hideki, Hiroko Tashiro, Shoichi Miyahara, Aki Dote, Shinji Tadaki, and Seiki Sakuyama. "Thermal stress reliability of copper through silicon via interconnects for 3D logic devices." In 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC). IEEE, 2016. http://dx.doi.org/10.1109/eptc.2016.7861455.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Weerasekera, R., M. Grange, D. Pamunuwa, and H. Tenhunen. "On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits." In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). IEEE, 2010. http://dx.doi.org/10.1109/date.2010.5457013.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Through silicon via, airgap interconnects' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography