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Zhu, Jian, Yuanwei Yu, Fang Hou, and Chen Chen. "Through-silicon via technologies for interconnects in RF MEMS." Microsystem Technologies 16, no. 7 (January 7, 2010): 1045–49. http://dx.doi.org/10.1007/s00542-009-1013-0.
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Kamto, A., Y. Liu, L. Schaper, and S. L. Burkett. "Reliability study of through-silicon via (TSV) copper filled interconnects." Thin Solid Films 518, no. 5 (December 2009): 1614–19. http://dx.doi.org/10.1016/j.tsf.2009.07.151.
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Wang, Teng, Kejll Jeppson, Lilei Ye, and Johan Liu. "Carbon-Nanotube Through-Silicon Via Interconnects for Three-Dimensional Integration." Small 7, no. 16 (June 21, 2011): 2313–17. http://dx.doi.org/10.1002/smll.201100615.
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Tiwari, Chandra S. "Conformal EL Ni Fill in Through-Silicon-Via for 3D Interconnects." ECS Transactions 41, no. 43 (December 16, 2019): 73–80. http://dx.doi.org/10.1149/1.4717505.
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Jiang, Di, Wei Mu, Si Chen, Yifeng Fu, Kjell Jeppson, and Johan Liu. "Vertically Stacked Carbon Nanotube-Based Interconnects for Through Silicon Via Application." IEEE Electron Device Letters 36, no. 5 (May 2015): 499–501. http://dx.doi.org/10.1109/led.2015.2415198.
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Shin, Young-min, Yong-Kweon Kim, Seung-Ki Lee, Hyogeun Shin, Il-Joo Cho, and Jae-Hyoung Park. "Microprobe electrode array with individual interconnects through substrate using silicon through-glass via." Sensors and Actuators B: Chemical 290 (July 2019): 336–46. http://dx.doi.org/10.1016/j.snb.2019.03.143.
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Leib, Jüergen, Florian Bieck, Ulli Hansen, Kok-Kheong Looi, Ha-Duong Ngo, Volker Seidemann, Dzafir Shariff, et al. "Tapered Through-Silicon-Via Interconnects for Wafer-Level Packaging of Sensor Devices." IEEE Transactions on Advanced Packaging 33, no. 3 (August 2010): 713–21. http://dx.doi.org/10.1109/tadvp.2009.2026950.
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Hernandez, George A., Daniel Martinez, Stephen Patenaude, Charles Ellis, Michael Palmer, and Michael Hamilton. "Through Si Vias Using Liquid Metal Conductors for Re-workable 3D Electronics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (January 1, 2013): 001343–57. http://dx.doi.org/10.4071/2013dpc-wp13.
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This paper describes the design and fabrication of liquid metal interconnects (vias) for 2.5D and 3D integration. The liquid metal is gallium indium eutectic with a melting temperature of approximately 15.7°C that is introduced into via openings of a silicon interposer. This liquid interconnect technology can be integrated with existing interposer technologies, such as capacitors and traditional (solid metal) through-silicon vias (TSVs). In addition, liquid metal interconnects can better accommodate thermal stresses and provide re-workability in case of chip failure. Our research efforts are focused on the integration of multi-chip modules using liquid metal interconnects. Our study encompasses Direct Current (D.C.) measurements and failure analysis using snake and comb structures at low temperature (10 degrees Kelvin) to slightly above room temperature (300 degrees Kelvin). The snake and comb structure allows us to measure electrical shorts and opens, as well as provide estimates of via yield and allows additional information for determination of possible failure mechanisms. In order to make electrical contact to the liquid metal interconnect interposer from both the top and bottom, test coupons have been fabricated with arrays of large numbers of vias. The interposer structure consists of a thin (200 um thick) silicon wafer with via holes filled with liquid metal. The test coupon consists of bottom and top silicon die with a thickness of 500 um. The bottom wafer incorporates a 2 um-thick daisy-chain metallization and 100 um copper tall vias, which are electrically isolated from each other and the underlying Si by patterned AL-X dielectric. The top wafer incorporates an array of 80 um tall, electroplated copper pillars and top daisy-chain metallization. Liquid metal containment mechanisms and structures have also been investigated. In our presentation we will describe the design, fabrication and characterization of this re-workable interposer with liquid metal interconnects. We will present D.C. resistance and X-ray imagery of the liquid metal filled via. In addition, we will provide failure analysis of via yield per chip.
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Sun, Shuangxi, Wei Mu, Michael Edwards, Davide Mencarelli, Luca Pierantoni, Yifeng Fu, Kjell Jeppson, and Johan Liu. "Vertically aligned CNT-Cu nano-composite material for stacked through-silicon-via interconnects." Nanotechnology 27, no. 33 (July 7, 2016): 335705. http://dx.doi.org/10.1088/0957-4484/27/33/335705.
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Nageswara Rao, K., G. Veerendra Nath, and K. Hari Kishore. "Crosstalk noise minimization in novel through silicon via structures." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 56. http://dx.doi.org/10.14419/ijet.v7i2.8.10325.
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In recent trends, through silicon via (TSV) is essential Technologies for 3-D IC integration because of its short interconnects length and high interconnect density. Beyond the existing structure of TSV, this paper provides a novel structure to investigate the crosstalk effect and same is simulated by using a SPICE simulator and 3-D field solver. The structure of the TSV comprises of copper surrounding by insulating liner, and silicon substrate. In existing structures, silicon dioxide (Sio2) is used as insulating liner because of its material compatibility with silicon substrate. Several researches provide the problem of using Sio2 is due to its high dielectric constant; as a consequence delay will increase. Therefore, Sio2 is not appropriate for high performance applications. In this work, a novel TSV structure is reported to improve the TSV performance which uses poly-propylene polymer liner instead of oxide liner. Signal TSV is enclosed by using a poly-propylene liner and amid the analysis with doping region is created around the ground TSV. For comparison purposes, conventional and proposed TSV structures are simulated. The proposed TSV’s structure simulation results in 30% decrease in crosstalk over existing TSV structures.
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Nakatsuka, Osamu, Hideki Kitada, Youngsuk Kim, Yoriko Mizushima, Tomoji Nakamura, Takayuki Ohba, and Shigeaki Zaima. "Characterization of Local Strain around Through-Silicon Via Interconnects by Using X-ray Microdiffraction." Japanese Journal of Applied Physics 50, no. 5S1 (May 1, 2011): 05ED03. http://dx.doi.org/10.7567/jjap.50.05ed03.
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Nakatsuka, Osamu, Hideki Kitada, Youngsuk Kim, Yoriko Mizushima, Tomoji Nakamura, Takayuki Ohba, and Shigeaki Zaima. "Characterization of Local Strain around Through-Silicon Via Interconnects by Using X-ray Microdiffraction." Japanese Journal of Applied Physics 50, no. 5 (May 20, 2011): 05ED03. http://dx.doi.org/10.1143/jjap.50.05ed03.
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Engin, A. Ege. "Passive Multiport RC Model Extraction for Through Silicon Via Interconnects in 3-D ICs." IEEE Transactions on Electromagnetic Compatibility 56, no. 3 (June 2014): 646–52. http://dx.doi.org/10.1109/temc.2013.2295049.
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WANG, Tao, Jian CAI, Qian WANG, Hao ZHANG, and Zheyao WANG. "Design and Fabrication of WLP Compatible Miniaturized Pressure Sensor System with Through Silicon Via (TSV) Interconnects." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000033–43. http://dx.doi.org/10.4071/isom-2011-ta1-paper5.
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In this paper, a Wafer Level Packaging (WLP) compatible pressure sensor system enabled with Through Silicon Via (TSV) and Au-Sn inter-chip micro-bump bonding is designed and fabricated in lab, in which TSV transmits electrical signal from piezoresistive circuit to processing circuit vertically. The pressure sensor system includes TSV integrated piezoresistive pressure sensor chip and Read-Out Integrated Chip (ROIC) in which TSV also incorporated. Two CMOS compatible fabrication process flows for pressure sensor system are demonstrated. And, flip chip bonding structure of TSV integrated pressure sensor with a ROIC are realized using one of these two process flows. Inter-chip interconnects enabled with TSV and micro-bump bonding is obtained.
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Spinella, Laura, Jang-Hi Im, Paul S. Ho, and Tengfei Jiang. "Correlation of Through-silicon Via (TSV) Dimension Scaling to TSV Stress and Reliability for 3D Interconnects." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000160–64. http://dx.doi.org/10.4071/isom-2016-wa22.
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Abstract Through-silicon vias (TSVs) are a crucial technology for enabling full three dimensional integration, yet they pose unique reliability risks, including thermal stress buildup due to the mismatch in the coefficient of thermal expansion between the silicon and the copper and the via extrusion phenomena. These effects can degrade device performance and it has been proposed that smaller TSV dimensions will reduce these reliability risks. In this paper, the correlation of shrinking dimensions to TSV stress and reliability is investigated, focusing on the effect of the microstructure on the plasticity and extrusion for 10, 5, and 2 μm diameter copper vias. Synchrotron x-ray microdiffraction revealed local plasticity concentrated in the tops of the vias of all diameters, and showed that the TSV stress behavior seemed to depend on the variations in the grain structure. Electron backscatter diffraction quantified the microstructure to show a tight distribution of grain sizes after the post-plating anneal, but further annealing to 400°C causes considerable data scatter for vias of all diameters. This result is consistent with the observed via extrusion statistics, in which the absolute values and variations in the extrusion heights increased significantly with further annealing. The wafer curvature technique is also used to observe the TSV stress relaxation behavior. Overall, these results suggest that scaling down TSV dimensions may not improve the stress and reliability behavior, particularly after further annealing at 400°C. Since such annealing processes are required for via-middle fabrication, it seems that via reliability will continue to be a challenge as TSV scaling continues.
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Feng, Ying, and Susan L. Burkett. "Fabrication and electrical performance of through silicon via interconnects filled with a copper/carbon nanotube composite." Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 33, no. 2 (March 2015): 022004. http://dx.doi.org/10.1116/1.4907417.
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Siblerud, Paul, Rozalia Beica, Bioh Kim, and Erik Young. "Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 000425–45. http://dx.doi.org/10.4071/2010dpc-ta11.
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The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.
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de Orio, R. L., H. Ceric, and S. Selberherr. "Analysis of Resistance Change Development Due to Voiding in Copper Interconnects Ended by A Through Silicon Via." ECS Transactions 49, no. 1 (August 30, 2012): 273–80. http://dx.doi.org/10.1149/04901.0273ecst.
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Arunasalam, Parthiban, Harold D. Ackler, and Bahgat G. Sammakia. "Microfabrication of ultrahigh density wafer-level thin film compliant interconnects for through-silicon-via based chip stacks." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 24, no. 4 (2006): 1780. http://dx.doi.org/10.1116/1.2210003.
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Li, Ji, Thomas Wasley, Duong Ta, John Shephard, Jonathan Stringer, Patrick J. Smith, Emre Esenturk, Colm Connaughton, Russell Harris, and Robert Kay. "Micro electronic systems via multifunctional additive manufacturing." Rapid Prototyping Journal 24, no. 4 (May 14, 2018): 752–63. http://dx.doi.org/10.1108/rpj-02-2017-0033.
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Purpose This paper aims to demonstrate the improved functionality of additive manufacturing technology provided by combining multiple processes for the fabrication of packaged electronics. Design/methodology/approach This research is focused on the improvement in resolution of conductor deposition methods through experimentation with build parameters. Material dispensing with two different low temperature curing isotropic conductive adhesive materials was characterised for their application in printing each of three different conductor designs, traces, z-axis connections and fine pitch flip chip interconnects. Once optimised, demonstrator size can be minimised within the limitations of the chosen processes and materials. Findings The proposed method of printing z-axis through layer connections was successful with pillars 2 mm in height and 550 µm in width produced. Dispensing characterisation also resulted in tracks 134 µm in width and 38 µm in height allowing surface mount assembly of 0603 components and thin-shrink small outline packaged integrated circuits. Small 149-µm flip chip interconnects deposited at a 457-µm pitch have also been used for packaging silicon bare die. Originality/value This paper presents an improved multifunctional additive manufacturing method to produce fully packaged multilayer electronic systems. It discusses the development of new 3D printed, through layer z-axis connections and the use of a single electrically conductive adhesive material to produce all conductors. This facilitates the surface mount assembly of components directly onto these conductors before stereolithography is used to fully package multiple layers of circuitry in a photopolymer.
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Jiang, Tengfei, Chenglin Wu, Jay Im, Rui Huang, and Paul S. Ho. "Impact of Grain Structure and Material Properties on Via Extrusion in 3D Interconnects." Journal of Microelectronics and Electronic Packaging 12, no. 3 (July 1, 2015): 118–22. http://dx.doi.org/10.4071/imaps.456.
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In this article, the effects of Cu microstructure on the mechanical properties and extrusion of through-silicon vias (TSVs) were studied based on two types of TSVs with different microstructure. A direct correlation was found between the grain size and the mechanical properties of the vias. Both an analytical model and finite element analysis (FEA) were used to establish the relationship between the mechanical properties and via extrusion. The effect of via/Si interface on extrusion was also studied by FEA. The results suggest small and uniform grains in the Cu vias, as well as stronger interfaces between the via and Si led to smaller via extrusion, and are thus preferable for reduced via extrusion failure and improved TSV reliability.
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Mangal, Nivesh, Jeroen Missinne, Joris Van Campenhout, Bradley Snyder, and Geert Van Steenberge. "Ball Lens Embedded Through-Package Via To Enable Backside Coupling Between Silicon Photonics Interposer and Board-Level Interconnects." Journal of Lightwave Technology 38, no. 8 (April 15, 2020): 2360–69. http://dx.doi.org/10.1109/jlt.2020.2966446.
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Banijamali, Bahareh, Suresh Ramalingam, and Raghunandan Chaware. "Advanced Thermal Study of Very High Power TSV Interposer and Interconnects for 28nm Technology FPGA." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000665–68. http://dx.doi.org/10.4071/isom-2011-wp1-paper2.
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TSV interposer has emerged as a good solution to provide high wiring density interconnections and improved electrical performance due to shorter interconnection from the die to substrate. Furthermore, silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. This paper presents the thermal study of TSV interposer technology for a high-performance 28nm logic die that is mounted on a large silicon interposer with Cu through silicon via. A representative silicon interposer test chip with thousands of micro-bumps at 45um pitch has been fabricated. The silicon interposer is 100um thick, and is mounted on a 42.5mmx42.5mm substrate through 180um pitch C4 bumps. 3D thermal modeling and simulation for the packaged device with TSV interposer have been performed. Several DOEs have been constructed to optimize thermal interface material selection and to study the effect of high power and hot spots on underfill and solder bump material properties as well as the effect of bump pitch and underfill properties on the die junction temperatures. Furthermore, thermal behavior of 28nm technology monolithic FPGA was compared to the 3D TSV interposer FPGA package. Optimized passive thermal solution was recommended for this high power FPGA in order to cool down up to 100 Watt power.
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Nguyen, Anh, Kevin Fealey, Peter Reilly, Gyanaranjan Pattanaik, Alison Gracias, Fred Wafula, Michael Flynn, and Jack Enloe. "Impact of Bath Stability on Electroplated Cu for Through-Silicon-Vias (TSV) in a Controlled Manufacturing Environment." International Symposium on Microelectronics 2014, no. 1 (October 1, 2014): 000013–18. http://dx.doi.org/10.4071/isom-ta13.
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This study addresses the impact of bath stability on electroplated copper for through silicon via (TSV) in a controlled manufacturing environment. Microstructure, impurities and other properties of the copper produced were characterized using an array of techniques, including Electron Backscatter Diffraction Analysis (EBSD), Focused Ion Beam – Secondary Electron Microscope (FIB-SEM) and Time of Flight - Secondary Ion Mass Spectrometry (ToF-SIMS). Chemical analyses of the plating baths throughout their lives indicates that the process can be controlled. Overall, a manufacturing process was demonstrated that can create high quality TSV Cu fill interconnects for 3D IC over the life of the bath. The process has enabled further development work at State University of New York Polytechnic Institute (SUNY Poly) for downstream processes such as chemical mechanical planarization (CMP) and Cu-Cu bonding.
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Shelton, Doug, and Tomii Kume. "Lithography Process Challenges for 3D and 2.5D Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (January 1, 2013): 000398–424. http://dx.doi.org/10.4071/2013dpc-ta14.
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Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon will continue its discussion of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications.
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Shelton, Doug, and Tomii Kume. "Lithography Process Optimization for 3D and 2.5D Applications." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000790–93. http://dx.doi.org/10.4071/isom-2013-thp11.
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Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon continues its investigation of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications also preliminary data illustrating 450 mm wafer process challenges.
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Katkar, Rajesh, Zhijun Zhao, Ron Zhang, Rey Co, and Laura Mirkarimi. "Ultra-fine pitch Package on Package solution for high bandwidth mobile applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (January 1, 2013): 001870–93. http://dx.doi.org/10.4071/2013dpc-tha14.
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Existing Package-on-Package (PoP) solutions are rapidly approaching the logic memory bandwidth capacity in the multi-core mobile processor packages. Package on Package stack using the conventional solder balls has a serious pitch limitation below 400um. The through mold via interconnects may reduce the pitch to 300um; however, this technology is believed to reach a limitation below 300 um. Other approaches including the use of PCB interposers between the Logic and the memory face similar challenges; however, they are cumbersome in the assembly process and expensive. Although Through Silicon Via stacking is expected to achieve the ultimate high bandwidth required to support multi-core mobile processors, the technology must overcome the challenges in process, infrastructure, supply chain and cost. Bond Via Array (BVA) technology addresses all of these issues while enabling high bandwidth PoP stacking of more than 1000 high aspect ratio interconnects at less than 200um within the standard package footprint. BVA is a cost effective, ultra-fine pitch, high density PoP stacking solution that will assist in driving high logic-memory bandwidth applications with standard assembly equipment and processes. This is achieved by encapsulating the logic package after forming free-standing wire bonds along the periphery of its flip chip substrate. The wire protrusions formed above the mold cap at the top of the package are then connected to the BGA at the bottom of the memory package during a standard reflow operation. In this work, the initial evaluation test vehicle with 432 PoP interconnects at 240um pitch within a standard 14 x 14mm package foot print is demonstrated. The important technological challenges we overcame to fabricate the first prototypes will be discussed. The reliability performance describing the temperature cycling, high temperature storage, autoclave and drop testing will be discussed. Finite element analysis modeling used to optimize the package structure will be presented.
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Banijamali, Bahareh, Raghunandan Chaware, Suresh Ramalingam, and Myongseob Kim. "Quality and Reliability of 3D TSV Interposer and Fine Pitch Solder Micro-bumps for 28nm Technology." International Symposium on Microelectronics 2011, no. 1 (January 1, 2011): 000189–92. http://dx.doi.org/10.4071/isom-2011-tp1-paper1.
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Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting significant industry attention. High density three dimensional (3D) interconnects formed by high aspect ratio through silicon via (TSV) and fine pitch solder micro bumps are presented in this paper. Different design/material related factors are evaluated during this study in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. Quality and reliability of copper TSV and micro-bumps are monitored in-situ during the process. This paper presents some of the quality and reliability results as well as micro-bump and TSV resistance data. Furthermore, bake and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA.
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Renn, Michael J., Bruce H. King, Michael O'Reilly, Jeff S. Leal, and Suzette K. Pangrle. "Aerosol Jet® Printing of High Density, 3-D Interconnects for Multi-Chip Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 002131–52. http://dx.doi.org/10.4071/2010dpc-tha15.
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Optomec's patented Aerosol Jet technology is a maskless, non-contact material deposition system used to enable 3-dimensional semiconductor packaging. This presentation highlights results of printing high density, 3-D interconnects on stacked die modules which incorporate video, communication and memory chips. Such packages are critical for meeting the increasing functional requirements of SmartPhones, personal entertainment, and other mobile devices. The Aerosol Jet system is used to deposit silver nanoparticle ink connections along the staircase sidewall of staggered multi-chip die stacks. High aspect ratio interconnects with 30-micron line width and greater than 10-micron line height are demonstrated at a pitch of 61-microns. After printing, the silver inks are cured at ~200°C for ~30 minutes, which gives interconnect resistances below one-Ohm (< 5 micron Ohm*cm). The stacks can include up to 8 die, with a total stack height below 1 mm. The printing system has a working distance of several mm which means that no Z-height adjustments are required for the interconnect printing. Multiplexed print nozzles are used to achieve production throughputs of greater than two interconnects per second per nozzle. Based on cost and functional advantages, the Aerosol Jet process is emerging as an effective alternative to traditional wire bond and through-silicon-via (TSV) technologies.
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Zohni, Wael, Rajesh Katkar, Rey Co, and Rizza Cizek. "Manufacturing Readiness of BVA(TM) Technology for Fine-Pitch Package-on-Package." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (January 1, 2014): 000930–59. http://dx.doi.org/10.4071/2014dpc-tp26.
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Package-on-Package (PoP) has become common for packaging the processor and memory subunit in today's smartphones and tablets. Today's PoPs provide only about 300 interconnects between the base and top packages due to physical limitations posed by existing manufacturing methods. As a result, memory data bandwidth is limited to 25.6 GB/s at 1600 MHz DDR signal speeds. With a trend towards System-on-Chip (SoC) mobile processors with multi-core CPU, memory bandwidth requirements are sharply increasing. To meet these needs, a wide IO memory industry standard has emerged to specify 512 memory data interconnects. This standard provides about 4 times current bandwidths (>100 GB/s) even at lower 800 MHz DDR signal speeds. For memory devices to offer 512 data lines, a total of about 1000 interconnects are needed to include the accompanying address, control, power and ground signals required for operation. No current PoP technology can offer 1000 interconnects, due to limited fine-pitch capability within the standard 14mm x 14mm package outline. Although industry expectation is for Through-Silicon-Via (TSV) technology to eventually offer a high-bandwidth solution, TSV manufacturing is still being developed and not expected to be widely available for a number of years. A new high-performance PoP interconnect technology called Bond-Via-Array (BVA [TM]) has been developed to provide high-bandwidth interconnect capability today. A BVA test vehicle package demonstrating 1020 processor to memory interconnects at 0.24mm pitch has been assembled inside the industry-standard 14mm x 14mm package outline. These fine pitch vertical interconnects are achieved utilizing well established wirebond equipment and process. As a result, BVA provides a cost-effective and reliable path to high-performance PoP. This paper details equipment and process developments related to high-volume-manufacturing (HVM) readiness of BVA technology. In addition to assembly process and equipment, test hardware that can accommodate fine pitch wire-tip interconnects needs to be demonstrated for manufacturing readiness. Socket and test hardware development and verification studies utilizing the latest 0.24mm pitch test vehicle are underway in cooperation with a 3rd party test hardware supplier. Goals include demonstrating feasibility of the fine-pitch PoP test approach as well as establishing sources for such hardware. In summary, BVA PoP technology enables 1000+ interconnects in a standard PoP outline while taking advantage of existing materials and infrastructure. To ensure manufacturing readiness, package assembly and test demonstrations are being carried out with third party vendors. Results indicate that with proper design and process optimization, high yield assembly and test is possible, and this technology is ready for high volume manufacturing.
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Dudley, Russ, Matt Wilson, and Rajiv Roy. "Metrology and Inspection for New Interconnects in Advanced Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (January 1, 2014): 001536–52. http://dx.doi.org/10.4071/2014dpc-wp16.
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Interconnects for Advanced Packaging are getting smaller and come in a variety of sizes, shapes, and materials. The height, diameter, shape, and the absence/presence of these interconnects are critical and must be monitored across the device and wafer to ensure reliable connections during the bonding process. Solder bump technologies have been utilized in the past, but cannot support the high density interconnects that are required. New interconnect technologies being utilized for wafer level packaging (WLP) and through silicon via (TSV) packages include copper pillar posts and TSV posts. These new interconnect technologies provide higher density, improved reliability, and better electrical performance. This paper will highlight the critical metrology and inspection requirements for these new interconnect technologies and demonstrate the capability of a single platform to support these new interconnects for high volume manufacturing (HVM). The single platform includes 3D metrology performed using a proprietary interferometric sensor technology that can measure the height of the post and the thickness of the surrounding polymer at the same time to optimize the measurement performance and system throughput. The platform also provides the ability to inspect for surface defects, irregular posts, missing posts, and a variety of other inspections typically performed on bumped wafers or substrates. Both the metrology and inspection results from the single platform are output to a proprietary analysis package using industry standard Rudolph Result Files (RRF). The analysis will demonstrate the value these results provide for process control and the defect analysis, ultimately leading to improved yields and equipment utilization.
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Vignes, Justin, Fred Haring, Syed Sajid Ahmad, Kaycie Gerstner, and Aaron Reinholz. "Laser Patterning and Via Drilling of Sapphire Wafers and Die." International Symposium on Microelectronics 2010, no. 1 (January 1, 2010): 000513–20. http://dx.doi.org/10.4071/isom-2010-wa5-paper3.
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As proliferation of handheld devices drives 3D packaging to achieve densification, embedding increased functionality into a chip is a natural complementary advancement in miniaturization. Ever increasing complexity of microelectronic design and functionality leads to the use of multiple surfaces for circuit development on wafers or individual die. Through-silicon vias, stacked die and stacked wafers, along with circuitry deposited on multiple surfaces and irregular shaped structures are some examples of 3D packaging. Laser patterning and via drilling on sapphire wafers and die with a 532 nm green laser has shown significant capabilities to make micro-features on and in the sapphire. Current structures include vias for die and wafer level interconnects, and patterned grooves for circuitry and antenna patterns. Other possibilities include pocket or trench patterning for adding passive components to the back of die or wafers. Backside patterning may be used for nano-imprinting of inks and other liquids. These grooves may also be used as micro-mixing or dispensing channels for use with nano-materials or liquids. All of these techniques may be applied to 3D die or wafer assembly and packaging.
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Nguyen, Anh, Kevin Fealey, Peter Reilly, Gyanaranjan Pattanaik, Alison Gracias, Fred Wafula, Michael Flynn, and Jack Enloe. "Impact of Bath Stability on Electroplated Cu for TSVs in a Controlled Environment." Journal of Microelectronics and Electronic Packaging 12, no. 1 (January 1, 2015): 43–48. http://dx.doi.org/10.4071/imaps.448.
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This study addresses the impact of bath stability on electroplated copper for through-silicon via (TSV) in a controlled manufacturing environment. Microstructure, impurities, and other properties of the copper produced were characterized using an array of techniques, including electron backscatter diffraction analysis, focused ion beam–secondary electron microscope, and time of flight–secondary ion mass spectrometry. Chemical analyses of the plating baths throughout their lives indicates that the process can be controlled. Overall, a manufacturing process was demonstrated that can create high-quality, TSV Cu fill interconnects for 3-D IC over the life of the bath. The process has enabled further development work at State University of New York Polytechnic Institute for downstream processes such as chemical mechanical planarization and Cu-Cu bonding.
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Soussan, Philippe, Kristof Vaesen, Bart Vereecke, and Jian Zhu. "Towards 200mm 3D RF interposer technology." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000055–61. http://dx.doi.org/10.4071/isom-2015-tp25.
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With the advent of modern and autonomous electronics, applications using RF (radio frequencies) up to millimeter waves and beyond are proliferating. The systems integration becomes increasingly challenging due to variety of devices and passives that typically compose such RF modules, and careful choices of materials are needed for low loss interconnects. One way to minimize RF losses is to integrate the module with high performance interconnect using Si technology, where the different device are mounted on the interposer and the passive are integrated into the silicon. Thanks to the TSV (Through Silicon Via) technology and use of High Resistivity Si substrate, it is possible to have small form factor modules. Such integration approach allows to benefit from the well-established base of 200mm foundries together with the recent progress made in High Resistivity substrate manufacturing. In this work, the process development of a 3D RF interposer technology based on a 200mm process line is reported. The build-up contains 2 levels of metals processed by Cu damascene technology, including a thick 2μm top metal for the lower frequencies applications, an integrated MIM (Metal Insulator Metal) capacitor and use trough silicon via in 5kOhm high resistivity 85μm thick substrate. The TSV are 20μm diameter and 85μm deep made in via first manner with via reveal using temporary carrier handling. Various RF passivation techniques for the silicon have been investigated and a comparison to quartz based on similar test structure is discussed.. Variety of passive devices, transmission line and filter have been processed and characterized. The technology yields 1μm pitch interconnect routing layer, a line loss of 0.34 dB/mm at 40 GHz, and high quality factors inductors larger than 30.
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Nabil, A., J. Bernardo, A. Rangel, M. Shaker, M. Abouelatta, L. Fakri-Bouchet, and C. Gontrand. "Towards a Description Synthesis of the Entanglement of the Substrate with the Interconnection Network, for Fast Modeling of 3D RF circuits." Transactions on Networks and Communications 9, no. 3 (May 28, 2021): 36–54. http://dx.doi.org/10.14738/tnc.93.10196.
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3D chip stacking is considered known to overcome conventional 2D-IC issues, using Trough Silicon Via (TSVs) to ensure vertical signal transmission between data. If the electrical behaviour of 3D interconnections (redistribution metal lines and through silicon vias) used in 3D IC stack technologies are to be explored in this paper, the substrate itself is of interest, via Green Kernels by solving Poisson's equation analytically. Using this technique, the substrate coupling and loss in IC's can be analysed. We implement our algorithms in MATLAB. This method has been already used; but, it permits to extract impedances for a stacked uniform layers substrate. We have extended for any numbers of embedded contacts, of any shape. On a second hand, we grasp the background noise between any two points, in the bulk, or at the surface, from a transfer impedance extraction technique. With an analog algorithm, a strength of this work, we calculate unsteady solutions of the heat equation, using a spreading resistance concept. This method has been adapted to stacked layers. With this general tool of impedance field, we investigate on the problems encountered by interconnects, especially the vias, the substrate, and their entanglement. A calculation of thermal mechanical stresses and their effects on substrate crack (max and min stresses), devices (i.e: transistors) and hotspots, are made to track the performance. But, to well understand the interconnection incidence on 3D system performances, it is important to consider the whole electrical context; it seems relevant to consider the possible couplings between vias, not only by the electromagnetic field, but also by any possible energy transfer between interconnects; more generally, one of actual problem is to determine where the energy is really confined in such 3D circuits, before find solutions to limit pollutions coming from electro-magneto -thermal phenomena or background noises.
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Afripin, M. A. A., N. A. Fadil, and M. Nasir Tamin. "Deformation mechanics of sputtered copper layers during nanoindentation tests." Journal of Mechanical Engineering and Sciences 14, no. 1 (March 23, 2020): 6504–13. http://dx.doi.org/10.15282/jmes.14.1.2020.25.0510.
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The mechanical properties of the thin sputtered copper layer on the SiO2-coated silicon substrate is needed as part of the requirements in quantifying the reliability of the Through-Silicon Via (TSV) interconnects. In this respect, two different Cu coating layers, each from the different sputtering process, are examined. A series of nanoindentation tests are performed on the Cu coating layer samples with indenter speeds ranging from 80 to 400 nm/s, and the indentation depths of 320 nm. The properties of elastic modulus, hardness and the hardening behavior of the Cu coating layers have been quantified. Results show that the coating with higher contamination of C at 8.41 wt. % displays a significant hardening and a peak load level, as reflected in the measured nanoindentation load-displacement curves. However, insignificant effect of the applied probe displacement speeds up to 400 nm/s on the resulting properties of the coating is registered. The Johnson-Cook constitutive equation adequately describes the strain rate-dependent hardening behavior of the Cu coating layer.
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Arunasalam, Parthiban, Harold D. Ackler, and Bahgat G. Sammakia. "Erratum: “Microfabrication of ultrahigh density wafer-level thin film compliant interconnects for through-silicon-via based chip stacks” [J. Vac. Sci. Technol. B 24, 1780 (2006)]." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 25, no. 1 (2007): 292. http://dx.doi.org/10.1116/1.2434021.
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Mobley, Tim, and Vern Stygar. "Through Glass Via (TGV) Solutions for Wafer and Chip level Interposers and RF Integration Methods for High Frequency Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, DPC (January 1, 2012): 001895–919. http://dx.doi.org/10.4071/2012dpc-wp25.
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This presentation will discuss TGV market trends and a low cost solution using new glass and synthetic fused quartz materials, TCE matched Cu metalizations, and designs for high density interconnect. The glass substrate or wafer combined with the low cost Cu metalization offers the market a solution that it has not yet seen. Applications are MEMS devices, Signal processing devices, memory storage devices, where hermeticity and high reliability are required, but the real challenge is how to achieve this at low cost. TGV technology offers significant advantages over Through Silicon Via (TSV) techniques, in that the glass can be assembled with the Si wafer or as a die with several highly reliable bonding techniques, which will be discussed. Technology continues to evolve requiring form factors that are smaller and smaller while still maintaining high frequency performance and long battery life; which are driving more interconnects from single IC's. Glass Interposers offer a high aspect ratio of wafer/substrate thickness to via diameter, and this paper will demonstrate 25–50micron vias in 10–15mil thick glass or synthetic fused quartz using low cost methods of production. While this method may be disruption to the current TSV supply chain to IC Device manufacturers, it will offer them a low cost, highly reliable solution they seek. The solution is enabled by an AGC manufactured Synthetic Quartz using a patented process that facilitates low impurities levels which results in an insertion loss previously unavailable at in both polymeric substrates and ceramic substrates.
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Wang, Yue Chun, Xiu Hua Chen, Wen Hui Ma, Xue Mei Liu, Yu Ping Li, Ping Bi, and Fu Wei Xiang. "Electroless Deposition of NiMoB Diffusion Barrier Layer Film for ULSI-Cu Metallization." Key Engineering Materials 727 (January 2017): 900–906. http://dx.doi.org/10.4028/www.scientific.net/kem.727.900.
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NiMoB alloy films were deposited on silicon substrate by electroless deposition for diffusion barrier application in copper interconnects technology. NiMoB(40nm)/SiO2/Si and NiMoB(20nm)/Cu (40nm)/NiMoB(40nm)/SiO2/Si samples were prepared and annealed at temperatures ranging from 400◦C to 600◦C. Samples were characterized by X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), Four Point Probes (FPP) and Atomic Force Microscopy (AFM) to investigate the phases, composition, sheet resistance and surface morphology. The results showed that electroless deposited NiMoB film can be used as an effective Cu diffusion barrier layer until 500◦C. And the failure mechanism is that NiMoB crystallized and grains grew after annealing at high temperature, a large number of Cu grains passed through NiMoB film via grain boundaries and then reacted with Si substrate and oxygen, causing the generation of highly resistive Cu4Si and CuO.
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Johnson, Donald W., and Bin-Hong Tsai. "SUEX Laminates for Fan-In, Fan-Out and eWLB Development." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2011, DPC (January 1, 2011): 000635–65. http://dx.doi.org/10.4071/2011dpc-ta31.
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The focus of this presentation is on the use of SUEX epoxy Thick Dry Film Sheets (TDFS) as a photoimagable dielectric layer in fan-in, fan-out and e-WLP applications. The sheets can be laminated over severe topography from under 2 μm to over 200 μm in height yielding void free coatings with 100% planarization over the entire substrate. The TDFS are available in a range of thicknesses and wafer or panel sizes. This new material is prepared under a highly controlled solvent-less process, which provides uniform coatings between two throw-away layers of protective polyester film. SUEX sheets of 100 μm thickness have been vacuum laminated in an isothermal process at 60–80°C over 180 μm high, 2mm X 2mm device chips mounted onto a silicon carrier wafer. Process optimization studies were run to determine the desired chamber vacuum, chuck temperature, lamination pressure and lamination time for optimal performance. The entire lamination process has a cycle time of about 10min. Using a vacuum laminator we have been able to obtain totally void-free coatings over 2 to 5 μm high bonding pads and buss lines at the silicon surface with a resist thickness of 205 μm over the trench and 25 μm thickness over the back of the chip with 100% planarization over the surface interface. Exposures on a contact aligner have yielded nominal 50 μm diameter via holes through the resist film to the contact pads at the bottom of the trench. Excellent adhesion to all surfaces on both the carrier wafer and the device chip has been obtained without any delamination or crack formation. Additional work to be presented will demonstrate the filling of the vias with electroplated copper to form interconnects the interconnects to for connection to bonding pads on the fan-out package surface.
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Tezcan, Deniz Sabuncuoglu, Bivragh Majeed, Yann Civale, Philippe Soussan, and Eric Beyne. "Via Last using Polymer Liners and their Reliability." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 000831–58. http://dx.doi.org/10.4071/2010dpc-tp15.
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This paper discusses the use of polymer dielectrics as insulating liner for realizing two types of 3D-WLP through Si vias (TSV's) in Si wafers with a thickness of respectively 50 and 100μm. These TSV technologies are based on thinning first, via last approach where 3D interconnects are implemented on the backside of thinned IC fabricated device wafers. Key aspects of the TSV processes are: i) fabricating the TSV from the backside of the wafer and contacting to BEOL M1, hence it is independent of the BEOL interconnect stack. ii) use of thick polymer as via isolation is a differentiator from most classical approaches using thin CVD oxide or nitride. The result is a significantly reduced capacitance, and hence, improvement of electrical performance. Another advantage of using thick polymer is that it can absorb some of the stress induced by CTE mismatch between the Cu in via and surrounding Si. This paper presents IMEC's 3D-WLP TSV flavors developed using spin-on dielectric polymers as isolation layer and the reliability of these TSVs' while undergoing thermal cycle tests. For each wafer thickness a 3-mask process sequence is implemented to fabricate the TSVs. Different process flows are used for the different Si thicknesses. For the 100μm thick substrate, a low aspect ratio TSV is used. A Si-via is etched from the wafer backside with a bottom diameter of about 70μm. The top side of the via is chamfered and has a top diameter of about 100μm. As a dielectric liner, a photo-sensitive spin-on polymer is conformally coated on the wafer. At the via bottom, a contact hole with approximately 30μm diameter is realized by photo patterning. Next, conformal Cu plating is used as TSV metallization. For the 50μm thick substrates, a different approach is used enabling a higher aspect ratio TSV. First, a 5μm wide ring trench is etched in the Si. Subsequently, these trenches are filled with a spin-on polymer. After filling the ring trenches, the central Si pillar is etched out of the via (second litho step) and the oxide at the via bottom is removed to provide access to the lowest chip metal level. Next, bottom-up Cu via fill is used to form the TSV metallization. This via has a Cu TSV diameter of 25μm, and an overall diameter with isolation of 35μm [1]. All processes employed in the fabrication of the TSVs are performed at low temperature (<200°C) for maximum post CMOS compatibility The test vehicle used to develop the TSV technologies include TSV daisy chains of various lengths connecting different number of vias to determine the TSV yield and resistance. For both TSV approaches, yielding electrical measurements are done on fabricated TSV wafers. For 50μm thick silicon, up to 95% electrical yield is achieved and the single TSV resistance is measured to be ~10–15mΩ on bonded stacks through Kelvin structures. Thermal cycling from −40 to +125°C of TSV dies are also done, and after 1000 thermal cycles no electrical failure is observed. For 100μm thick silicon TSV approach, single TSV resistance is measured to be ~4–20mΩ with good yield. Test die are subjected to 1000 thermal cycles and results show limited yield loss.
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Wang, Mengcheng, Shenglin Ma, Yufeng Jin, Wei Wang, Jing Chen, Liulin Hu, and Shuwei He. "A RF Redundant TSV Interconnection for High Resistance Si Interposer." Micromachines 12, no. 2 (February 8, 2021): 169. http://dx.doi.org/10.3390/mi12020169.
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Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) substrates. This paper presents a redundant TSV interconnect design for high resistivity Si interposers for millimeter-wave applications. To verify its feasibility, a set of test structures capable of working at millimeter waves are designed, which are composed of three pieces of CPW (coplanar waveguide) lines connected by single TSV, dual redundant TSV, and quad redundant TSV interconnects. First, HFSS software is used for modeling and simulation, then, a modified equivalent circuit model is established to analysis the effect of the redundant TSVs on the high-frequency transmission performance to solidify the HFSS based simulation. At the same time, a failure simulation was carried out and results prove that redundant TSV can still work normally at 44 GHz frequency when failure occurs. Using the developed TSV process, the sample is then fabricated and tested. Using L-2L de-embedding method to extract S-parameters of the TSV interconnection. The insertion loss of dual and quad redundant TSVs are 0.19 dB and 0.46 dB at 40 GHz, respectively.
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Ha, Dohyuk, Tse-Yu Lin, Byung Guk Kim, Pedro P. Irazoqui, and William J. Chappell. "Advanced 3D Packaging of Miniature Biomedical Sensors." International Symposium on Microelectronics 2010, no. 1 (January 1, 2010): 000543–47. http://dx.doi.org/10.4071/isom-2010-wp1-paper2.
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In this paper, a novel 3D packaging technique for miniature implantable wireless biomedical sensors for intraocular pressure (IOP) sensing in mice is introduced. Due to the limited size of a mouse eye, the packaging of the sensor and control integrated circuit (IC) is very challenging. The overall size of the packaged sensor must be less than 12 mils cubed. In order to achieve the desired thickness, a magnetically aligned Z-axis anisotropic conductive adhesive (ACA) is used to create the vertical interconnects and micro-vias in the packaging material to distribute signals vertically to limit the eventual area of the device. The first step is to demonstrate the layer-to-layer interconnection between a silicon IC and a liquid crystal polymer (LCP) layer using the Z-axis ACA. The total thickness of the IC and the packaging layer is less than 6 mils. The measured resistance through vertical interconnection is 1.15 ohms on average for 3 mil × 3 mil pads. The second step is to demonstrate 3D transitions through 0.8 mil via holes in a LCP layer. A transition from an antenna layer through the LCP to a rectifier circuit on the above layer is demonstrated. RF power received by a loop antenna on the bottom LCP layer is rectified and generates 5 volts of DC voltage. This miniature 3D packaging technique enables extremely tight integration of all the sensor's components in a small form factor package, which can be implanted into mice eyes for wireless monitoring of the intraocular pressure.
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Peic, Antun, Thorsten Matthias, Johanna Bartl, and Paul Lindner. "Enabling Resist Processing Technologies for Advanced Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (January 1, 2014): 000830–62. http://dx.doi.org/10.4071/2014dpc-tp22.
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The increasing adoption of advanced wafer-level packaging (WLP) technologies and high density interposer concepts clearly reflect the permanent need for form factor reduction, smaller process geometries and higher-count I/O on ICs. Currently, several strategies are being pursued to achieve these goals. The most promising approaches are summarized under the concept of three-dimensional integrated circuits (3D-IC) and three-dimensional wafer level packaging (3D-WLP) technology. A key component for 3D device integration schemes is the requirement of vertical through-silicon-via (TSV) interconnections that enables electrical through-chip communication through stacks of vertically integrated layers on the wafer scale. Ultimately, the use of TSVs also enables higher performance and smaller package sizes. In order to realize TSV connections, a series of process steps is required such as the thinning and bonding of the wafer to a carrier prior to the formation of through-wafer vias, followed by the passivation and metallization of the vias. Despite the potential benefits associated with the integration of TSVs also significant challenges have to be overcome. One of the greatest challenges for present and even more for upcoming TSV design strategies still remains the processing of photoresist and other functional polymers at and within TSV geometries. To this day, it is still very difficult to achieve a conformal polymer coating in deep cavities, along steep side walls and especially within the extreme aspect ratios of TSV. Mainly this is due to the fact that standard surface coating methods such as spin coating were just not developed to meet the requirements posed by these high aspect ratio microstructures. New and innovative approaches are needed to meet these new challenges. Spray coating is one of the most promising technologies to overcome current barriers. However, even most of the available spray deposition equipment is facing its limits with steadily decreasing via diameters and increasing aspect ratios on the other hand. Successively, the multitude of these challenging technological developments in the 3D-IC and wafer-level packaging area has created the demand for innovative manufacturing approaches, new equipment and related tools. Herein we present our new EVG ®NanoSprayTM coating technology with unique capabilities to overcome the present limits of conformal resist coating over extreme topography. We demonstrate one particularly promising application for conformal polymer coatings; as an annular lining at the interface between the conducting metal filling in the TSV and the silicon wafer. The intrinsic properties of the polymer allow a TSV design solution that is more forgiving on coefficient of thermal expansion (CTE) mismatch-induced stress between the silicon substrate and the interfacing metal. Consequently, this new type of polymer buffered TSV interconnect design promises to significantly reduce thermal stress-induced TSV delamination as one of the dominant failure modes for 3-D interconnects. We further demonstrate the application of EVG ®NanoSprayTM as enabling coating technology for llithographic processing of conformal coated TSVs. The patterning of thin photoresist layers at the bottom of vias and along the steep sidewalls of deep cavities allows for more degrees of freedom in electrical contact formation. The presented EVG ®NanoSprayTM coating technology opens new dimensions in advanced wafer level packaging and provokes reconsidering prevailing limitations in interconnect design.
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Awad, Ibrahim, and Leila Ladani. "Multiscale Modeling of Novel Carbon Nanotube/Copper-Composite Material Used in Microelectronics." Journal of Multiscale Modelling 07, no. 02 (June 2016): 1650001. http://dx.doi.org/10.1142/s1756973716500013.
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Current carrying capacity is one of the elements that hinders further miniaturization of Copper (Cu) interconnects. Therefore, there is a need to propose new materials with higher ampacity (current carrying capacity) that have the potential to replace Cu. Experimental observations have shown that Carbon Nanotube (CNT)/Cu-composite material has a hundredfold ampacity of Cu, which makes it a good candidate to replace Cu. However, sufficient information about the mechanical behavior of the novel CNT/Cu-composite is not available. In the current paper, the CNT/Cu-composite is utilized to construct Through Silicon Via (TSV). The mechanical behavior, specifically the fatigue life, of the CNT/Cu–TSV is evaluated by applying a multiscale modeling approach. Molecular Dynamics (MD) simulations are conducted to evaluate the tensile strength and the coefficient of thermal expansion of CNTs. MD simulation is also used to determine the interface behavior between CNTs and Cu. MD simulation results are integrated into Finite Element analysis at the micro-level to estimate the fatigue life of the CNT/Cu–TSV. A comparison is made with base material; Cu. CNTs addition has redistributed the plastic deformation in Cu to occur at two different locations (Si/Cu interface and Cu/CNT interface) instead of only one location (Si/Cu interface) in the case of Cu-only-TSV. Thus, the maximum equivalent plastic strain has been alleviated in the CNT/Cu–TSV. Accordingly, CNT/Cu–TSV has shown a threefold increase in the fatigue life. This is a solid indication of the improvement in the fatigue life that is attributed to the addition of CNTs.
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CHAN, PHILIP C. "DESIGN AUTOMATION FOR MULTICHIP MODULE — ISSUES AND STATUS." International Journal of High Speed Electronics and Systems 02, no. 04 (December 1991): 263–85. http://dx.doi.org/10.1142/s0129156491000132.
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In this paper we will review the current state of commercial electronic design automation (EDA) tools for the design of multichip modules. MCM can be classified in terms of its substrate technology. The choice of substrate technology has important implications for the selection of design automation tools. A PCB EDA system seems more appropriate for MCMs with stacked via substrate which closely resembles the through-hole printed circuit board (PCB). A chip layout system may be more appropriate for MCMs with low-cost thin-film silicon substrate which typically uses staircase vias. The cofired ceramic substrate MCM which evolved from the hybrid integrated circuit technology may use the specialized hybrid EDA software packages available for the designing of hybrid integrated circuits. Historically, printed circuit board and integrated circuit design automation software evolved separately. There exists a boundary between the printed circuit board and integrated circuit design automation tools in the physical design hierarchy. This boundary can be an important limitation for the repartitioning of the physical design hierarchy within the MCM. We shall discuss in detail the impact of MCM on various aspects of EDA. In the area of physical design, we must face the traditional placement and routing problem for any high speed design. Problems such as system clock skew and tight timing requirements must be considered. As one push clock frequency higher, one also must consider discontinuities due to vias and bends besides the classical transmission line effect due to long wires. Other traditional physical design problems such as ground and power plane generation, physical design verification and mask tooling must be revisited in the context of various MCM substrate technologies. The thermal aspects of MCM design are strongly influenced by the placement of chips on the MCM substrate. Thermal design is especially important for high density MCMs using the flip-chip mounting technology. Here, the heat must be dissipated through the back of the substrate via thermal pillars or bumps. We still need to deal with the traditional coupled transmission line problems. Due to the small cross section, high performance MCM substrate interconnects are resistive and the transmission lines they form are lossy. Noise is another main problem for MCM design. For high speed MCM with many CMOS buffers, the ground bouncing noise resulting from simultaneous switching of a large number of CMOS drivers must be controlled through proper substrate and package design. We will conclude the paper by comparing existing VLSI and PCB EDA tools for MCM design.
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Flemming, Jeb, Kyle McWethy, Tim Mezel, Luis Chenoweth, and Carrie Schmidt. "Photosensitive Glass-Ceramics for Heterogeneous Integration." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000880–907. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_036.
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The push for heterogeneous integration requires very unique material properties with respect to processing, material constants, and integration capabilities with other materials (such as copper, III–V, magnetics, etc.). Current common circuit board materials such as ceramics and laminates, as well as silicon substrates, suffer from a variety of limitations. For ceramics and laminates, these constraints include: (1) the inability to produce narrow line widths <100 m with narrow gaps between lines <100 m; (2) high surface roughness (on the order of 2μm RMS); (3) layer-to-layer misalignments; and (4) lack of high-quality integrated passives. For silicon, these constraints include: (1) high cost; (2) long design/production lead times; and (3) electrical properties of standard doped silicon are not suitable for millimeter-wave applications. A significant drawback of ceramics and laminates is that they cannot be 3D structured with micron-scale precision which is necessary for advanced interconnects for millimeter-wave IC packaging integration (e.g. transistor-to-board interconnects). These characteristics lead to devices with limited integration options, large footprints, and higher power consumption. To overcome the above limitations, 3D Glass Solutions (3DGS) has developed a photo-sensitive glass ceramics as a board-level system substrate. Compared to ceramics, laminates, and silicon, photo-sensitive glass ceramic materials offer higher interconnect densities, lower processing cost, better spatial resolution, as well as improved electrical properties for both RF and millimeter-wave frequencies. Photo-sensitive glass ceramics are ideal systems-level materials for heterogeneous integration programs as they overcome many of the limitations of legacy materials such as ceramics and laminates for broadband applications (DC – 100GHz). Furthermore, the advanced manufacturing ability of photo-sensitive glass ceramics enable a broad category of IP Blocks. The innovations of the 3DGS technology and research effort include:Low loss and low dispersion: photosensitive glass material has a measured loss tangent of 0.008 at GHz frequencies. Furthermore, the thick and highly-conductive metallization layers allow for low-loss transmission lines.High current and power handling: the metallization processes enable lines with a range of thicknesses (<50m) and widths (>2m), which result in both low resistive loss and high current handling. Additionally, the RF power handling is high due to the high breakdown voltage of glass (10kV/100m) and the possibility of coaxial line integration.Thermal management: high-density metal-filled via arrays generate up to 100W/mK thermal transfer in the 3DGS process and provide an additional thermal path for chips that are not mounted directly on a heterogeneous interface heat spreader.Built-in filtering: when a variety of chiplets with unknown design parameters and with signals of varying time constants are interconnected, EMI becomes a significant problem. The 3DGS approach allows for high-quality filtering, coupling and self-assessment functions to be directly integrated within the 2.5D interposer system as IPDs eliminating wire bonding and providing seamless integration with low loss.Scalability: the glass interconnect plane can be fabricated with footprints up to 40mm × 40mm with integrated air cavities for chip placement, through glass vias for I/Os and redistribution metal. In this presentation, 3DGS will present on three Heterogeneous Integration attributes: (1) design considerations, (2) integration of passive devices, and (3) millimeter wave integration. Design Considerations 3DGS is developing an IP Block library with 11 distinct categories. These categories include: (1) metal filled I/Os, (2) copper redistribution layers, (3) thermal management blocks, (4) cavities, (5) metal filled through glass structures, (6) phased array antenna, (7) conductor undercuts, (8) magnetic core devices, (9) capacitors, (10) inductors, and (11) grounding. While each of these unique IP Blocks contributes their own advantages for analog performance, they can all be integrated into a single chip. Integration of Passives Devices The foundation of the work done by 3DGS is on developing a volume manufacturing approach for high uniformity through glass vias (TGVs). All TGVs for I/O applications are 100% copper filled for low-loss, high power, electrical connections. Two major building blocks of 3DGS' Heterogeneous technology are High Quality Factor inductors and capacitors. 3DGS has developed a broad library of inductor components ranging from 0.5 – 200nH. Footprints are determined by inductance sizes but may be as small as 01005. Capacitors are built by placing two slots inside of the glass material, filling the slots with copper, and using the glass' natural Dk to form a capacitor. The benefit of these capacitors include high breakdown voltage (>1,000V), small footprint, high reliability, and Quality factors between 200–300. Inductors and capacitors can be integrated into a single monolithic RF package called an Integrated Passive Device (IPD). The benefits of the IPD include the elimination of RF losses associated with PCB Interconnects, long metal redistribution line lengths, bond pads, solder balls, and inconsistent assembly. This leads to the production of RF devices, capable of operating in the MHz – GHz frequency range with higher overall system Quality Factors, lower ripple, and lower losses. Furthermore, IPDs can be directly integrated into more complex System-in-Package (SiP) architectures. This approach has been used to build an RF ZigBee module in APEX® Glass [1]. The glass SiP module consisted of 35+ SMT components and was itself soldered to a PCB board. The full RF module was then subjected full complement of reliability tests and met the customer's stringent performance goals. Millimeter Wave Integration A major benefit of glass is the ability to produce low loss structures for millimeter wave applications. 3DGS has been designing and producing a variety of millimeter wave band pass filters with a variety of bandwidths ranging from 5–40%. These bandpass filters are compact, fully shielded and low loss (<2.0dB) with high attenuation (>50dB).
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NGUYEN, Anh Phuong, Ulrike Lüders, and Frederic Voiron. "Impact of electrical and thermal stresses on TSV radiofrequency performance." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (January 1, 2016): 000342–66. http://dx.doi.org/10.4071/2016dpc-ta14.
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This paper presents a study of the propagation parameters (impedance and propagation constant) for interconnection structures implementing interconnection lines (wafer front and backside) combined with Through Silicon Via (TSV). Lifetime acceleration experiments are conducted on these structures and indicate a significant variation of the propagation parameters across lifespan. The underlying physical mechanism is demonstrated and an activation model for the prediction of the line parameter variation is proposed. TSV-last processes have been considered by industry for the implementation of 3D interconnects into various kind of silicon substrates already functionalized on the front side. This is possible thanks to a TSV process with a low temperature budget (<200°C), guaranteeing the compatibility with most of the pre-existing MOS and passive technologies. IPDiA is offering this type of TSV technology in combination with the PICS passive platform (Passive Integrated Connecting Substrate). Several test vehicles have been implemented and excellent performances have been observed in the small signal/RF domains; electrical models have been extracted from test silicon and are showing a good agreement with simulation results and earlier literature. Application domains with permanent bias have also been considered and non-linear effects related to the semiconductor nature of the substrate have been reported (i.e. drift-diffusion). However, the effect of electrical and thermal stress that might arise from severe applications or long lifespan, and their impacts on TSV electrical stability, have not yet been reported in the literature. This works concentrates on the study of the instability modes that are related to the TSV dielectric aging under permanent bias accelerated by temperature. To avoid effects from other mechanisms (like, for example, copper diffusion in the oxide) under the selected acceleration conditions (Efield<10MV/cm, temperature <100°C), specific test structures (planar CPW) are designed. It consists of an AlSi (0.5%) metallization, which is isolated from the P type HR (High Resistivity) substrate by TSV isolation dielectric. Four different flavors of dielectric are proposed: PECVD oxide deposited at 150°C/200°C combined/not with a thermal oxide liner. When implemented, the liner is intended to enhance the dielectric/silicon interface, thus allowing to differentiate the effects of fixed charges, mobile charges, and interface states density. A strong correlation is found between charge density within the dielectric and the CPW loss and characteristic impedance. While line loss increases with charge density, the opposite behavior is observed for the characteristic impedance. Furthermore, under CVS (constant voltage stress) at 7.5 MV/cm under 100°C, a displacement of mobile charges into the dielectric is observed, that correlates to the variation of the CPW performances. FTIR analysis indicates that the mobile charges are related to the presence of silanol/hydroxide ions resulting from moisture absorption in the oxide. Similar effects are observed on real 3D TSV structures. An activation model is derived from previous results, which allows predicting the evolution of the CPW characteristics as a function of thermos-electrical stress.
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Ivankovic, Andrej, Thibault Buisson, Amandine Pizzagalli, Dave Towne, and Rozalia Beica. "2.5D / 3D IC Landscape: Market and Technology Trends." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (January 1, 2016): 000260–305. http://dx.doi.org/10.4071/2016dpc-ta11.
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The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain and continue to be investigated, the spotlight is turning to advanced packages. Emerging packages such as fan-out wafer level packages and 2.5D / 3D IC solutions together with upgraded flip chip BGAs aim to revive the cost/performance curve and extend both scaling and functionality roadmaps. Future packages need to tackle the explosion in information exchange translating to high number of I/Os and be able to support heterogeneous integration. This puts particular pressure on die to board interconnects. Technologies to fill the void created in diverging PCB versus IC feature sizes are constantly under development. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect, considered today the most advanced technology, is one emerging option that aims to enable heterogeneous integration. Such a technology is not limited to CMOS scaling in itself, it is rather based on bringing more functionality by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive components…) while reducing the package form factor. This functional diversification is also known as More-than-Moore. This work focuses on the analysis of recent developments and future trends of the 2.5D / 3D IC landscape. What's new since last year? TSV technology has already been utilized for several years within the MEMS and CMOS image sensor (CIS) market, but the news is that it finally seems to be happening within the logic and memory domain. Latest products such as AMD Radeon R9 Fury with its 2.5D configuration including HBM stacks and Samsung 3D TSV stacked DRAM, among others, aim for high volume. Fueled by consumer applications such as smartphones and tablets, the MEMS and CIS markets are expected to exhibit continuous growth over the next several years, while in the high-end market, driven by the need for further performance increase, volatile memory and especially DRAM are finally opening the doors of 2.5D / 3D IC commercial adoption. This analysis will cover 2.5D interposer & 3DIC platforms as well as MEMS and CIS TSV packaging. Market forecasts in terms of wafer starts, market revenue, application segments and end-products will be presented. Furthermore, supply chain activities and major player interactions will be analyzed and 3D integration technology roadmaps will be reviewed. In conclusion, this study will aim at providing comprehensive insight into 2.5D / 3D IC market and technology trends.
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Majeed, Bivragh, Marc Van Cauwenberghe, Deniz Sabuncuoglu Tezcan, and Philippe Soussan. "Failure Analysis and Process Improvement for Through Silicon Via Interconnects." MRS Proceedings 1156 (2009). http://dx.doi.org/10.1557/proc-1156-d08-04-f06-04.
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AbstractThis paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.