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Relevant bibliographies by topics / Time-delay phase locked loop

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Academic literature on the topic 'Time-delay phase locked loop'

Author: Grafiati

Published: 5 June 2025

Last updated: 15 July 2025

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Journal articles on the topic "Time-delay phase locked loop"

1

Bassam, Harb, Qudah Mohammad, Ghareeb Ibrahim, and Harb Ahmad. "Chaos and bifurcation in time delayed third order phase-locked loop." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 1431–38. https://doi.org/10.11591/ijece.v11i2.pp1431-1438.

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In this paper, the modern nonlinear theory is applied to a third order phase locked loop (PLL) with a feedback time delay. Due to this delay, different behaviors that are not accounted for in a conventional PLL model are identified, namely, oscillatory instability, periodic doubling and chaos. Firstly, a Pade approximation is used to model the time delay where it is utilized in deriving the state space representation of the PLL under investigation. The PLL under consideration is simulated with and without time delay. It is shown that for certain loop gain (control parameter) and time delay val

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Spalvieri, A., and M. Magarini. "Wiener's Analysis of the Discrete-Time Phase-Locked Loop With Loop Delay." IEEE Transactions on Circuits and Systems II: Express Briefs 55, no. 6 (2008): 596–600. http://dx.doi.org/10.1109/tcsii.2007.916861.

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Harb, Bassam, Mohammad Qudah, Ibrahim Ghareeb, and Ahmad Harb. "Chaos and bifurcation in time delayed third order phase-locked loop." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 1431. http://dx.doi.org/10.11591/ijece.v11i2.pp1431-1438.

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In this paper, the modern nonlinear theory is applied to a third order phase locked loop (PLL) with a feedback time delay. Due to this delay, different behaviors that are not accounted for in a conventional PLL model are identified, namely, oscillatory instability, periodic doubling and chaos. Firstly, a Pade approximation is used to model the time delay where it is utilized in deriving the state space representation of the PLL under investigation. The PLL under consideration is simulated with and without time delay. It is shown that for certain loop gain (control parameter) and time delay val

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4

Subhash, Patel *. Abhishek Vaghela Bhavin Gajjar. "DESIGN OF PHASE LOCKED LOOP." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 5 (2017): 312–20. https://doi.org/10.5281/zenodo.573512.

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In this work, we have designed CDR-PLL for 1GHz frequency. The design is carried out in the 180nm CMOS technology. We have use Hogge phase detector with the Kim-Lee delay cell based VCO. The designed CDR-PLL is tested by applying the 8B-10B encoded data and the simulation results are represented. The obtained results show that the clock is recovered successfully.

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Radwan, Eyad, Khalil Salih, Emad Awada, and Mutasim Nour. "Modified phase locked loop for grid connected single phase inverter." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (2019): 3934. http://dx.doi.org/10.11591/ijece.v9i5.pp3934-3943.

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Connecting a single-phase or three-phase inverter to the grid in distributed generation applications requires synchronization with the grid. Synchronization of an inverter-connected distributed generation units in its basic form necessitates accurate information about the frequency and phase angle of the utility grid. Phase Locked Loop (PLL) circuit is usually used for the purpose of synchronization. However, deviation in the grid frequency from nominal value will cause errors in the PLL estimated outputs, and that’s a major drawback. Moreover, if the grid is heavily distorted with low order h

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Eyad, Radwan, Salih Khalil, Awada Emad, and Nour Mutasim. "Modified phase locked loop for grid connected single phase inverter." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (2019): 3934–43. https://doi.org/10.11591/ijece.v9i5.pp3934-3943.

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Connecting a single-phase or three-phase inverter to the grid in distributed generation applications requires synchronization with the grid. Synchronization of an inverter-connected distributed generation units in its basic form necessitates accurate information about the frequency and phase angle of the utility grid. Phase Locked Loop (PLL) circuit is usually used for the purpose of synchronization. However, deviation in the grid frequency from nominal value will cause errors in the PLL estimated outputs, and that’s a major drawback. Moreover, if the grid is heavily distorted with low o

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Zhou, Duo, Jin Yi Zhang, and Bo Ye. "An Implementation of Wide-Range Digital Delay Locked Loop." Advanced Materials Research 945-949 (June 2014): 2226–29. http://dx.doi.org/10.4028/www.scientific.net/amr.945-949.2226.

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This paper presents an all digital delay-locked loop (DLL) to achieve wide range operation, fast lock and process immunity. To keep track of any potential phase problem caused by environmental variations, a delay compensation mechanism is employed. Utilizing the delay compensation controller (DCC), the proposed DLL can overcome the false-lock problem in conventional designs. It is fast locking because the DLL’s initial state can be detected by the delay compensation controller and the initial large phase difference can be eliminated. The proposed DLL is implemented in a 0.13μm CMOS process. Th

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D Patel, Nilesh, and Amisha P Naik. "PHASE LOCKED LOOP USING SUB HARMONIC INJECTION TECHNIQUE WITH AUTO ADJUSTED DELAY LOCKED LOOP." ICTACT Journal on Microelectronics 6, no. 3 (2020): 959–63. https://doi.org/10.21917/ijme.2020.0166.

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For high speed communication applications; jitter, phase noise and power consumption are most critical parameters required to be considered for PLL designs. A sub harmonically injection locking concept can be used in PLL to reduce jitter and phase noise. Such design is very effective for high frequency applications. This article presents design for low jitter, phase noise, power dissipation for 7.5 GHz Phase locked loop using sub harmonic injection technique with auto adjusted Delay locked loop in 180-nm CMOS technology. The measured phase noise at 1 MHz reference offset frequency is 122.31 dB

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Goodberlet, J., J. Ferrera, and H. I. Smith. "Analogue delay-locked loop for spatial-phase locking." Electronics Letters 33, no. 15 (1997): 1269. http://dx.doi.org/10.1049/el:19970858.

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Goodberlet, J. "Spatial-phase-locked electron-beam lithography with a delay-locked loop." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 15, no. 6 (1997): 2293. http://dx.doi.org/10.1116/1.589632.

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Dissertations / Theses on the topic "Time-delay phase locked loop"

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Thayaparan, Subramaniam. "Delay-locked loop techniques in direct sequence spread-spectrum receivers." Thesis, Hong Kong : University of Hong Kong, 1999. http://sunzi.lib.hku.hk/hkuto/record.jsp?B21904108.

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Jia, Cheng. "A Delay-Locked Loop for Multiple Clock Phases/Delays Generation." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7470.

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A Delay-Locked Loop (DLL) for the generation of multiple clock phases/delays is proposed. Several new techniques are used to help enhance the DLLs performance, specifically, to achieve wide lock range, short locking time, and reduced jitter. The DLL can be used for a variety of applications which require precise time intervals or phase shifts. The phase detector (PD), charge pump (CP), and voltage-controlled delay line (VCDL) are the three most important blocks in a DLL. In our research, we have proposed a novel structure which integrates the functionality of both the PD and CP. By using

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Kippenberger, Roger Miles. "On Real Time Digital Phase Locked Loop Implementation with Application to Timing Recovery." Thesis, University of Canterbury. Electrical and Computer Engineering, 2006. http://hdl.handle.net/10092/1146.

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In digital communication systems symbol timing recovery is of fundamental importance. The accuracy in estimation of symbol timing has a direct effect on received data error rates. The primary objective of this thesis is to implement a practical Digital Phase Locked Loop capable of accurate synchronisation of symbols suffering channel corruption typical of modern mobile communications. This thesis describes an all-software implementation of a Digital Phase Locked in a real-time system. A timing error detection (TED) algorithms optimally implemented into a Digital Signal Processor. A real-time

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Chuai, Kun. "High order phase-locked loop design and test for time-mode signal processing applications." Thesis, McGill University, 2010. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=95015.

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This thesis first presents a pole-zero placement algorithm for the systematic design of high-order phase-locked loops (PLL) serving as anti-imaging and anti-aliasing filters for time-mode signal processing applications. A 6th order PLL is designed and fabricated on a printed circuit board and is interfaced to a production mixed-signal tester. The correct filtering operation and large-signal transfer characteristic of the PLL are verified with an all-digital DFT solution. The digital test input is driven by a single clock, which can be programmed directly from an ATE high-speed digital pattern

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Prakasha, Prarthana. "A Study of Injection Locking in Optoelectronic Oscillator." Thesis, Université d'Ottawa / University of Ottawa, 2020. http://hdl.handle.net/10393/41147.

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The random fluctuations of signal phase of an oscillator limit the precision of time and frequency measurements. The noise and long-term stability of the system’s oscillator or clock is of major importance in applications such as optical and wireless communications, high-speed digital electronics, radar, and astronomy. The Optoelectronic Oscillator (OE Oscillator), a new class of time delay oscillator with promise as a low-phase noise source of microwave carriers, was introduced by Steve Yao and Lute Malek in 1996. The OE Oscillator combines into a closed loop an RF photonic link and an RF cha

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Reilly, Nicholas James. "Cmos Programmable Time Control Circuit Design For Phased Array Uwb Ground Penetrating Radar Antenna Beamforming." ScholarWorks @ UVM, 2017. http://scholarworks.uvm.edu/graddis/687.

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Phased array radar systems employ multiple antennas to create a radar beam that can be steered electronically. By manipulating the relative phase values of feeding signals among different antennas, the effective radiation pattern of the array can be synthesized to enhance the main lobe in a desired direction while suppressing the undesired side lobes in other directions. Hence the radar scanning angles can be electronically controlled without employing the bulky mechanical gimbal structure, which can significantly reduce radar system size, weight and power consumption. In recent years, phased

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Wali, Naveen, and Balamurali Radhakrishnan. "Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106744.

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An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. The all-digital phase locked loop replaces the traditional charge pumpbased analog phase locked loop. The digital nature of the all-digital phase lockedloop system makes it superior to the analog counterpart.There are four main partswhich constitutes the all-digital phase locked loop. The time-to-digital converteris one of the important block in all-digital phase locked loop. Several time-to-digital converter architectures were stud

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Lee, Min Jae. "A low noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution." Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1679290771&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.

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Lucas, de Peslouan Pierre-Olivier. "Conception orientée délai : étude, développement et réalisation d’une boucle à verrouillage de phase large bande stabilisée par une boucle à verrouillage de délai." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14265/document.

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L’explosion du marché des télécommunications a donné lieu, lors de ces dernières années, à la multiplication des standards de radiocommunication. De nos jours, l’ensemble de ces moyens de communication utilisés pour le transfert de voix et de données doit être intégré dans les terminaux mobiles. Cependant, cette tendance s’oppose aux contraintes de faible coût qui tendent à diminuer la taille de l’électronique embarquée dans un terminal mobile, mais aussi aux contraintes de diminution de la consommation pour une plus grande autonomie des objets sans fils. C’est donc autour de ces verrous techn

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Moberg, Caroline. "Development of measurement algorithm in an industrial PLC : An evaluation of DSOGI-PLL for real time measurements." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-388490.

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The aim of this project was to devise an algorithm for three phase AC power grid measurements that could be utilized in an excitation system for controlling generators. This application requires fast and accurate measurements even when the voltages in the power grid are characterized by unbalanced three-phase, frequency variations and harmonic distortions. Phase locked loop algorithms are used in grid synchronization techniques and are developed to withstand disturbances in the power grid. A DSOGI-PLL was implemented on a PLC and then evaluated. The DSOGI-PLL was tested with input voltages gen

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Books on the topic "Time-delay phase locked loop"

1

Al-Araji, Saleh R., Zahir M. Hussain, and Mahmoud A. Al-Qutayri. Digital Phase Lock Loops: Architectures and Applications. Springer, 2010.

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Al-Araji, Saleh R., Zahir M. Hussain, and Mahmoud A. Al-Qutayri. Digital Phase Lock Loops: Architectures and Applications. Springer London, Limited, 2007.

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Analysis and Design of CMOS Clocking Circuits for Low Phase Noise. Institution of Engineering & Technology, 2020.

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Phase-Locked Frequency Generation and Clocking: Architectures and Circuits for Modern Wireless and Wireline Systems. Institution of Engineering & Technology, 2020.

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Book chapters on the topic "Time-delay phase locked loop"

1

Banerjee, Tanmoy, and B. C. Sarkar. "Application of Time-Delayed Feedback Control Techniques in Digital Phase-Locked Loop." In Advances and Applications in Nonlinear Control Systems. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-30169-3_18.

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Koval, V. V., V. P. Lysenko, D. O. Kalian, O. L. Osinskyi, and O. V. Samkov. "Improving Efficiency of the Phase-Locked Loop for Reference Oscillator of the Multichannel System for Time Synchronization Signals Telemonitoring." In Current Trends in Communication and Information Technologies. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-76343-5_4.

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Bertulessi, Luca. "Frequency Synthesizers Based on Fast-Locking Bang-Bang PLL for Cellular Applications." In Special Topics in Information Technology. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-62476-7_3.

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AbstractThe fractional-N frequency synthesis based on Digital Phase Locked Loop (DPLLs) has become a conventional design approach for the new radio wireless applications. The advantage of the digitally-intensive design style is the possibility to implement low-power and very accurate digital calibration techniques. Most of these algorithms run in the background tracking PVT variations and either relax or, in some cases, completely remove the performance limitations due to analog impairments. Moreover, the digital loop filter area is practically negligible with respect to the one in analog PLLs. These benefits become even more relevant in the scaled CMOS technology nodes. This chapter identifies the design parameters of a standard DPLL architecture and proposes a novel locking scheme to overcome the intrinsic limitations of the digital frequency synthesizers approach. To prove this new scheme a sub-6 GHz fractional-N synthesizer has been implemented in 65 nm CMOS. The synthesizer has an output frequency from 3.59 GHz to 4.05 GHz. The integrated output jitter is 182fs and the power consumption of 5.28 mW from 1.2 V power supply leads to a FoM of −247.5 dB. This topology exploits a novel locking technique that guarantee a locking time of 5.6 s, for a frequency step of 364 MHz, despite the use of a single bit phase detector.

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Luo, Gang, and Xianjun Zeng. "A Static-Error-Less Phase Detector for Delay Locked Loops." In Advances in Intelligent and Soft Computing. Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-27948-5_40.

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Koll, Lisa-Marie, Tobias Witting, and Marc J. J. Vrakking. "Control of Photoelectron-Ion Entanglement in Attosecond Laser-Induced Photoionization of H2." In Springer Proceedings in Physics. Springer International Publishing, 2024. http://dx.doi.org/10.1007/978-3-031-47938-0_15.

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AbstractWe report experiments where vibrational wave packets are produced in H2+ by the ionization of neutral H2 by a sequence of two phase-locked attosecond pulse trains (APTs) with a variable time delay. Changes in the degree of vibrational coherence in the H2+ cation with the XUV-XUV time delay can be explained in terms of the dependence of the degree of ion+photoelectron entanglement on the two-pulse delay.

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"The Time-delay Digital Tanlock Loop in Noise." In Digital Phase Lock Loops. Springer US, 2006. http://dx.doi.org/10.1007/978-0-387-32864-5_5.

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"Project 6: Phase-Locked Loop." In Real-Time Digital Signal Processing from MATLAB to C with the TMS320C6x DSPs. CRC Press, 2011. http://dx.doi.org/10.1201/b11742-26.

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"One-dimensional discrete-time Phase-Locked Loop." In World Scientific Series on Nonlinear Science Series A. WORLD SCIENTIFIC, 2007. http://dx.doi.org/10.1142/9789812770912_0004.

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"Two-dimensional discrete-time Phase-Locked Loop." In World Scientific Series on Nonlinear Science Series A. WORLD SCIENTIFIC, 2007. http://dx.doi.org/10.1142/9789812770912_0005.

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"Time-Average-Frequency." In Nanometer Frequency Synthesis Beyond the Phase-Locked Loop. John Wiley & Sons, Inc., 2012. http://dx.doi.org/10.1002/9781118347959.ch3.

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Conference papers on the topic "Time-delay phase locked loop"

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Wu, Haitao, Zhaolong Li, Sibo Gui, Junchao Wang, Meng Shi, and Jianye Zhao. "Long-Term Stabilization of an Actively Mode-Locked Optoelectronic Oscillator Using Phase-Locked Loop." In 2024 European Frequency and Time Forum (EFTF). IEEE, 2024. http://dx.doi.org/10.1109/eftf61992.2024.10722450.

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Pan, Jiaming, Meng Su, Fule Li, et al. "A 3-MHz-3-GHz 8-Phase Reset-Free Anti-Harmonic Delay-Locked Loop Using Phase Difference Composition in 65-nm CMOS." In 2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2024. http://dx.doi.org/10.1109/mwscas60917.2024.10658666.

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M V, Akshay Kumar, and Rajath Vasudevamurthy. "Design and Implementation of a Digital Phase-Locked Loop (DPLL) with Vernier Time-to-Digital Converter (TDC) for Dynamic Frequency Selection." In 2024 Global Conference on Communications and Information Technologies (GCCIT). IEEE, 2024. https://doi.org/10.1109/gccit63234.2024.10862110.

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"Research Progress of Phase Locked Loop and Delay Locked Loop." In 2017 2nd International Conference on Mechatronics and Information Technology. Francis Academic Press, 2017. http://dx.doi.org/10.25236/icmit.2017.64.

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Callender, Steven, and Ali M. Niknejad. "A phase-adjustable Delay-Locked Loop utilizing embedded phase interpolation." In 2011 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2011. http://dx.doi.org/10.1109/rfic.2011.5940657.

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Kuo, Chien-Hung, and Yu-Chieh Ma. "A 128-phase delay-locked loop with cyclic VCDL." In 2013 5th Asia Symposium on Quality Electronic Design (ASQED). IEEE, 2013. http://dx.doi.org/10.1109/asqed.2013.6643555.

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Zhang, Larry. "Accurately measure phase-locked loop lock time in production." In 2006 Asia-Pacific Microwave Conference. IEEE, 2006. http://dx.doi.org/10.1109/apmc.2006.4429462.

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Jang, In-Woo, and Min-Seong Choo. "Direct Phase Control in Digital Phase-Locked Loop Mitigating Loop Delay Effect inside Digital Filter." In 2023 International Conference on Electronics, Information, and Communication (ICEIC). IEEE, 2023. http://dx.doi.org/10.1109/iceic57457.2023.10049900.

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Khare, Kavita, Nilay Khare, Pallavi Deshpande, and Vijendra Kulhade. "Phase frequency detector of delay locked loop at high frequency." In 2008 IEEE International Conference on Semiconductor Electronics (ICSE). IEEE, 2008. http://dx.doi.org/10.1109/smelec.2008.4770288.

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Zhang, Larry. "Parallel Testing of Phase-Locked Loop Lock Time In Production." In 2006 8th international Conference on Signal Processing. IEEE, 2006. http://dx.doi.org/10.1109/icosp.2006.345824.

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