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1
Thayaparan, Subramaniam. "Delay-locked loop techniques in direct sequence spread-spectrum receivers." Thesis, Hong Kong : University of Hong Kong, 1999. http://sunzi.lib.hku.hk/hkuto/record.jsp?B21904108.
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Jia, Cheng. "A Delay-Locked Loop for Multiple Clock Phases/Delays Generation." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7470.
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A Delay-Locked Loop (DLL) for the generation of multiple clock phases/delays is proposed. Several new techniques are used to help enhance the DLLs performance, specifically, to achieve wide lock range, short locking time, and reduced jitter. The DLL can be used for a variety of applications which require precise time intervals or phase shifts. The phase detector (PD), charge pump (CP), and voltage-controlled delay line (VCDL) are the three most important blocks in a DLL. In our research, we have proposed a novel structure which integrates the functionality of both the PD and CP. By using this structure, a fast switching speed can be achieved. Moreover, the combined PD and CP also lead to reduced chip area and better jitter performance. A novel phase detection algorithm is developed and implemented in the combined PD and CP structure. This algorithm also involves a start-control circuit to avoid locking failure or false lock to harmonics. With the help of this algorithm, the proposed DLL is able to achieve lock as long as the minimum VCDL delay is less than one reference clock cycle, which is the largest possible lock range that can be achieved by the DLL. The VCDL uses fully differential signaling to minimize jitter. The delay stage of the VCDL is built with a differential topology using symmetrical loads and replica-feedback biasing, which provides a low sensitivity to supply and substrate noise as well as a wide tuning range. In addition, a shift-averaging technique is used to improve the matching between delay stages and thus to equalize the delay of each individual stage.
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Kippenberger, Roger Miles. "On Real Time Digital Phase Locked Loop Implementation with Application to Timing Recovery." Thesis, University of Canterbury. Electrical and Computer Engineering, 2006. http://hdl.handle.net/10092/1146.
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In digital communication systems symbol timing recovery is of fundamental importance. The accuracy in estimation of symbol timing has a direct effect on received data error rates. The primary objective of this thesis is to implement a practical Digital Phase Locked Loop capable of accurate synchronisation of symbols suffering channel corruption typical of modern mobile communications. This thesis describes an all-software implementation of a Digital Phase Locked in a real-time system. A timing error detection (TED) algorithms optimally implemented into a Digital Signal Processor. A real-time transmitter and receiver system is implemented in order to measure performance when the received signal is corrupted by both Additive White Gaussian Noise and Flat Fading. The Timing Error Detection algorithm implemented is a discrete time maximum likelihood one known as FFML1, developed at Canterbury University. FFML1 along with other components of the Digital Phase Locked loop are implemented entirely in software, using Motorola 56321 assembly language.
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Chuai, Kun. "High order phase-locked loop design and test for time-mode signal processing applications." Thesis, McGill University, 2010. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=95015.
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This thesis first presents a pole-zero placement algorithm for the systematic design of high-order phase-locked loops (PLL) serving as anti-imaging and anti-aliasing filters for time-mode signal processing applications. A 6th order PLL is designed and fabricated on a printed circuit board and is interfaced to a production mixed-signal tester. The correct filtering operation and large-signal transfer characteristic of the PLL are verified with an all-digital DFT solution. The digital test input is driven by a single clock, which can be programmed directly from an ATE high-speed digital pattern generator. As application of these high-order PLLs, an accurate and low-cost clock delay generation system is presented. With proper compensation and calibration, a delay resolution of 15 ps is achieved over an 8.4 ns range. This technique is shown experimentally to be a viable solution for clock alignment and for measuring jitter at a 50 GHz effective sampling rate.<br>Ce mémoire présente tout d'abord une approche systématique descendante pour la conception de boucles à verrouillage de phase (PLL) ayant un ordre arbitraire et opérant comme filtre anti-image ou anti-repliement pour le traitement de signal dans le domaine temporel. Un PLL de 6e ordre a été conçu et fabriqué sur une carte de circuit imprimé montée sur un tester à signaux-mixtes (ATE). La fonction de filtrage et la caractéristique de transfert de grands-signaux sont vérifiées à l'aide d'une solution de conception pour test (DFT) entièrement numérique. Le signal d'entrée numérique est cadencé par une horloge unique. Par conséquent, le signal de test peut être programmé sans effort à partir de l'instrument numérique à haute-vitesse (HSD) d'un testeur à signaux-mixtes (ATE). De plus, un système précis et économique de génération de délai d'horloge est présenté comme une application du PLL construit. A l'aide de calibration et compensation appropriées, une résolution de délai de l'ordre de 15 ps est réalisée pour un intervalle de 8.4 ns. Cette technique est démontrée expérimentalement comme étant une solution viable pour l'alignement d'horloge et pour mesurer le vacillement d'horloge à un rythme de sous-échantillonnage de 50 GHz.
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Prakasha, Prarthana. "A Study of Injection Locking in Optoelectronic Oscillator." Thesis, Université d'Ottawa / University of Ottawa, 2020. http://hdl.handle.net/10393/41147.
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The random fluctuations of signal phase of an oscillator limit the precision of time and frequency measurements. The noise and long-term stability of the system’s oscillator or clock is of major importance in applications such as optical and wireless communications, high-speed digital electronics, radar, and astronomy. The Optoelectronic Oscillator (OE Oscillator), a new class of time delay oscillator with promise as a low-phase noise source of microwave carriers, was introduced by Steve Yao and Lute Malek in 1996. The OE Oscillator combines into a closed loop an RF photonic link and an RF chain. The RF photonic link consists of a laser, electro-optic modulator, optical fibre delay line, and a photo-receiver that together provide an RF delay. An RF chain consists of one or more amplifiers and a RF resonator that together provide the sustaining amplification and the frequency selectivity necessary for single mode oscillation of the loop. The low loss of optical fibres enables the attainment of delays that correspond to optical fibre lengths of several kilometers. It is the long delay, unattainable in an all electronic implementations that is responsible for the superior phase noise performance of an OE Oscillator.
In this thesis the fundamental principles of operation of an OE Oscillator are described and the principal sources of in-loop phase fluctuations that are responsible for phase-noise identified. This lays the ground for an exposition of the mechanism that describes the perturbation of a time delay oscillator by injection into the loop of a carrier that is detuned in frequency from the natural frequency of the oscillator. For sufficiently small detuning the oscillator can become phase locked to the injected carrier. The model presented in the thesis generalises the traditional Yao-Maleki and Leeson model to include all the important features that describe the injection locking dynamics of an OE Oscillator. In particular the common assumptions of single mode oscillation and weak injection are removed. This is important to correctly predict the effect of injection locking on the spurious peaks in the phase noise spectrum corresponding to the side-modes of a time delay oscillator. Simulation results are presented in order to validate the dynamics of the oscillator under injection and analytic results on the lock-in range and phase noise spectrum. A 10 GHz OE Oscillator with a single 5km delay line is used as an example in the simulation illustration.
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Reilly, Nicholas James. "Cmos Programmable Time Control Circuit Design For Phased Array Uwb Ground Penetrating Radar Antenna Beamforming." ScholarWorks @ UVM, 2017. http://scholarworks.uvm.edu/graddis/687.
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Phased array radar systems employ multiple antennas to create a radar beam that can be steered electronically. By manipulating the relative phase values of feeding signals among different antennas, the effective radiation pattern of the array can be synthesized to enhance the main lobe in a desired direction while suppressing the undesired side lobes in other directions. Hence the radar scanning angles can be electronically controlled without employing the bulky mechanical gimbal structure, which can significantly reduce radar system size, weight and power consumption. In recent years, phased array technologies have received great attentions and are explored in developing many new applications, such as smart communication systems, military radars, vehicular radar, etc. Most of these systems are narrow band systems, where the phase delays are realized with narrow band phase shifter circuits. For the impulse ground penetrating radar however, its operating frequency spans an ultrawide bandwidth. Therefore the traditional phase shifters are not applicable due to their narrow band nature. To resolve the issue, in this study, a true time delay approach is explored which can precisely control time delays for the feeding pulse signals among different antennas in the array. In the design, an on chip programmable delay generator is being developed using Global Foundry 0.18 µm 7 HV high voltage CMOS process. The time delay control is realized by designing a programmable phase locked loop (PLL) circuit which can generate true time delays ranging from 100 ps (picoseconds) to 500 ps with the step size of 25 ps. The PLL oscillator's frequency is programmable from 100MHz to 500MHz through two reconfigurable frequency dividers in the feedback loop. As a result, the antenna beam angle can be synthesized to change from 9.59° to 56.4° with a step of 2.75°, and the 3dB beamwidth is 10°. The power consumption of the time delay circuit is very low, where the supply voltage is 1.8V and the average current is as low as 472uA.
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Wali, Naveen, and Balamurali Radhakrishnan. "Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106744.
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An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. The all-digital phase locked loop replaces the traditional charge pumpbased analog phase locked loop. The digital nature of the all-digital phase lockedloop system makes it superior to the analog counterpart.There are four main partswhich constitutes the all-digital phase locked loop. The time-to-digital converteris one of the important block in all-digital phase locked loop. Several time-to-digital converter architectures were studied and simulated. TheVernier delay based architecture and inverter delay based architecture was designedand evaluated. There architectures provided certain short comings whilethe pseudo-differential time-to-digital converter architecture was chosen, becauseof it’s less occupation of area. Since there exists a relationship between the sizeof the delay cells and it’s time resolution, the pseudo-differential time-to-digitalconverter severed it’s purpose. The whole time-to-digital converter system was tested on a 1 V power supply,reference frequency 54-MHz which is also the reference clock Fref , and a feedbackfrequency Fckv 2.1-GHz. The power consumption was found to be around 2.78mW without dynamic clock gating. When the clock gating or bypassing is done,the power consumption is expected to be reduced considerably. The measuredtime-to-digital converter resolution is around 7 ps to 9 ps with a load variation of15 fF. The inherent delay was also found to be 5 ps. The total output noise powerwas found to be -128 dBm.
8
Lee, Min Jae. "A low noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution." Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1679290771&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Lucas, de Peslouan Pierre-Olivier. "Conception orientée délai : étude, développement et réalisation d’une boucle à verrouillage de phase large bande stabilisée par une boucle à verrouillage de délai." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14265/document.
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L’explosion du marché des télécommunications a donné lieu, lors de ces dernières années, à la multiplication des standards de radiocommunication. De nos jours, l’ensemble de ces moyens de communication utilisés pour le transfert de voix et de données doit être intégré dans les terminaux mobiles. Cependant, cette tendance s’oppose aux contraintes de faible coût qui tendent à diminuer la taille de l’électronique embarquée dans un terminal mobile, mais aussi aux contraintes de diminution de la consommation pour une plus grande autonomie des objets sans fils. C’est donc autour de ces verrous technologiques et techniques que se concentre une part importante des efforts de « R&D » aujourd’hui. Ainsi, l’objectif des travaux présentés repose sur la recherche et le développement d'une architecture contribuant à l’amélioration des performances du bloc central de la chaîne d’émission/réception : l'oscillateur local.L’architecture innovante de synthétiseur de fréquence multistandard réalisée est fondée sur le principe de « conception orientée délai » (DOD - Delay Oriented Design). Une nouvelle technique de stabilisation, issue de la superposition d’une boucle à verrouillage de délai et de phase, est proposée afin d’élargir la bande passante.De l’étude système à la mesure en passant par l’étude comportementale et la réalisation du circuit, les différentes étapes de conception de ce système fractionnaire sont présentées. Les simulations et les mesures ont démontré la capacité du synthétiseur à couvrir une bande comprise entre 1,6 et 3,5GHz avec un signal de référence à 500MHz, mais aussi à stabiliser une architecture très large bande<br>The explosion of the wireless communication market is largely responsible of the expansion for RF communication standards for voice and data. Nowadays, each one of them must be integrated in one mobile terminal.However, this trend is opposed to the constraints of low cost, which tend to reduce the size of the electronics in a mobile terminal, but also the constraints of reduced consumption for greater autonomy for wireless systems. It is then around these technological and technical barriers that focus an important part of efforts to « R & D » today. Thus, the objective of the work presented is based on research and development of an architecture that contributes to improve the performances of the central block of transceivers: the local oscillator.The innovative architecture of multistandard synthesizer realized is based on the principle of Delay Oriented Design (DOD). A new technique of stabilization, based on the superposition of a delay and a phase locked loop, is proposed to expand the bandwidth. From study system to measurements through the behavioral comportment and implementation of the circuit, the various stages when designing an RF system are presented. Simulations and measurements have demonstrated the ability of the synthesizer to cover a frequency band between 1.6 and 3.5 GHz with a reference signal at 500MHz, but also to stabilize a broadband architecture
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Moberg, Caroline. "Development of measurement algorithm in an industrial PLC : An evaluation of DSOGI-PLL for real time measurements." Thesis, Uppsala universitet, Institutionen för teknikvetenskaper, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-388490.
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The aim of this project was to devise an algorithm for three phase AC power grid measurements that could be utilized in an excitation system for controlling generators. This application requires fast and accurate measurements even when the voltages in the power grid are characterized by unbalanced three-phase, frequency variations and harmonic distortions. Phase locked loop algorithms are used in grid synchronization techniques and are developed to withstand disturbances in the power grid. A DSOGI-PLL was implemented on a PLC and then evaluated. The DSOGI-PLL was tested with input voltages generated by a relay testing system. The result showed that the DSOGI-PLL could measure positive sequence component RMS and grid frequency of unbalanced three-phase voltages and voltages characterized by frequency variations and harmonic distortions. However, the measurements response time and accuracy did not meet the requirements for application in excitation systems.
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Olivarez, Nathan. "Mitigating the Effects of Ionospheric Scintillation on GPS Carrier Recovery." Digital WPI, 2013. https://digitalcommons.wpi.edu/etd-theses/245.
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Ionospheric scintillation is a phenomenon caused by varying concentrations of charged particles in the upper atmosphere that induces deep fades and rapid phase rotations in satellite signals, including GPS. During periods of scintillation, carrier tracking loops often lose lock on the signal because the rapid phase rotations generate cycle slips in the PLL. One solution to mitigating this problem is by employing decision-directed carrier recovery algorithms that achieve data wipe-off using differential bit detection techniques. Other techniques involve PLLs with variable bandwidth and variable integration times. Since nearly 60% of the GPS signal repeats between frames, this thesis explores PLLs utilizing variable integration times and decision-directed algorithms that exploit the repeating data as a training sequence to aid in phase error estimation. Experiments conducted using a GPS signal generator, software radio, and MATLAB scintillation testbed compare the bit error rate of each of the receiver models. Training-based methods utilizing variable integration times show significant reductions in the likelihood of total loss of lock.
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Gong, Jianping. "Sub-Picosecond Jitter Clock Generation for Time Interleaved Analog to Digital Converter." Digital WPI, 2019. https://digitalcommons.wpi.edu/etd-dissertations/557.
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Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-defined radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, offset mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an acceptable effective-numberof-bits (ENOB) which can be degraded by jitter in the sample clock. The clock generation circuits presented in this work achieves sub-picosecond jitter performance in 180nm CMOS which is suitable for time-interleaved ADC. Two different test chips were fabricated in 180nm CMOS to investigate the low jitter design technique. The low jitter delay line in two chips were designed in two different ways, but both of them utilized the low jitter design technique. In first test chip, the measured RMS jitter is 0.1061ps for each delay stage. The second chip uses the proposed low jitter Delay-Locked Loop can work from 80MHz to 120MHz, which means it can provide the time interleaved ADC with 2.4GHz to 3.6GHz low jitter sample clock, the measured delay stage jitter performance in second test chip is 0.1085ps.
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Hussain, Zahir M. "Adaptive instantaneous frequency estimation: Techniques and algorithms." Thesis, Queensland University of Technology, 2002. https://eprints.qut.edu.au/36137/7/36137_Digitised%20Thesis.pdf.
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This thesis deals with the problem of the instantaneous frequency (IF) estimation of sinusoidal signals. This topic plays significant role in signal processing and communications.
Depending on the type of the signal, two major approaches are considered. For IF estimation of single-tone or digitally-modulated sinusoidal signals (like frequency shift keying signals) the approach of digital phase-locked loops (DPLLs) is considered, and this is Part-I of this thesis. For FM signals the approach of time-frequency analysis is considered, and this is Part-II of the thesis.
In part-I we have utilized sinusoidal DPLLs with non-uniform sampling scheme as this type is widely used in communication systems. The digital tanlock loop (DTL) has introduced significant advantages over other existing DPLLs. In the last 10 years many efforts have been made to improve DTL performance. However, this loop and all of its modifications utilizes Hilbert transformer (HT) to produce a signal-independent 90-degree phase-shifted version of the input signal. Hilbert transformer can be realized approximately using a finite impulse response (FIR) digital filter. This realization introduces further complexity in the loop in addition to approximations and frequency limitations on the input signal. We have tried to avoid practical difficulties associated with the conventional tanlock scheme while keeping its advantages. A time-delay is utilized in the tanlock scheme of DTL to produce a signal-dependent phase shift. This gave rise to the time-delay digital tanlock loop (TDTL). Fixed point theorems are used to analyze the behavior of the new loop. As such TDTL combines the two major approaches in DPLLs: the non-linear approach of sinusoidal DPLL based on fixed point analysis, and the linear tanlock approach based on the arctan phase detection. TDTL preserves the main advantages of the DTL despite its reduced structure. An application of TDTL in FSK demodulation is also considered. This idea of replacing HT by a time-delay may be of interest in other signal processing systems. Hence we have analyzed and compared the behaviors of the HT and the time-delay in the presence of additive Gaussian noise.
Based on the above analysis, the behavior of the first and second-order TDTLs has been analyzed in additive Gaussian noise.
Since DPLLs need time for locking, they are normally not efficient in tracking the continuously changing frequencies of non-stationary signals, i.e. signals with time-varying spectra. Nonstationary signals are of importance in synthetic and real life applications. An example is the frequency-modulated (FM) signals widely used in communication systems. Part-II of this thesis is dedicated for the IF estimation of non-stationary signals. For such signals the classical spectral techniques break down, due to the time-varying nature of their spectra, and more advanced techniques should be utilized.
For the purpose of instantaneous frequency estimation of non-stationary signals there are two major approaches: parametric and non-parametric. We chose the non-parametric approach which is based on time-frequency analysis. This approach is computationally less expensive and more effective in dealing with multicomponent signals, which are the main aim of this part of the thesis.
A time-frequency distribution (TFD) of a signal is a two-dimensional transformation of the signal to the time-frequency domain. Multicomponent signals can be identified by multiple energy peaks in the time-frequency domain. Many real life and synthetic signals are of multicomponent nature and there is little in the literature concerning IF estimation of such signals. This is why we have concentrated on multicomponent signals in Part-H.
An adaptive algorithm for IF estimation using the quadratic time-frequency distributions has been analyzed. A class of time-frequency distributions that are more suitable for this purpose has been proposed. The kernels of this class are time-only or one-dimensional, rather than the time-lag (two-dimensional) kernels. Hence this class has been named as the T -class. If the parameters of these TFDs are properly chosen, they are more efficient than the existing fixed-kernel TFDs in terms of resolution (energy concentration around the IF) and artifacts reduction. The T-distributions has been used in the IF adaptive algorithm and proved to be efficient in tracking rapidly changing frequencies. They also enables direct amplitude estimation for the components of a multicomponent
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Rideout, Howard. "A true-time delay beamforming system incorporating a wavelength tunable optical phase-lock loop." Thesis, University of Ottawa (Canada), 2007. http://hdl.handle.net/10393/27550.
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This thesis presents the study of a frequency-discriminator-aided optical phase-lock loop (OPLL) and its application to a fiber-Bragg-grating-based true-time delay (TTD) module for the purpose of phased-array antenna (PAA) beamforming. The TTD module uses uniform fiber Bragg gratings (FBGs) to form the delay lines of an FBG prism. The wavelengths from two external cavity laser diodes are phase-locked by the OPLL and applied to the FBG prism to achieve tunable time delays.
The performance of the system is evaluated using a time-delay measurement experiment. The experimental time delays generated are compared with the theoretically designed values and are found to be in close agreement. Simulations of the radiation patterns generated from the measured time delays are found to closely match the steering angle designed for the system. To the best of our knowledge, this is the first time an OPLL has been used in conjunction with an FBG-based TTD beamforming module.
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Gammoh, Khalil Jacob. "PVT-Tolerant Stochastic Time-to-Digital Converter." BYU ScholarsArchive, 2018. https://scholarsarchive.byu.edu/etd/7692.
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Time-to-digital converters (TDC) are widely used in light-detection-and-ranging (LIDAR) systems to measure the time-of-flight. Conventional TDCs are sensitivity to process, voltage, and temperature (PVT) variations. Recent work utilizing the stochastic delay-line TDC architecture has demonstrated excellent robustness against PVT variations. But important issues affecting the linearity of a stochastic delay-line TDC has yet to be recognized and addressed.This thesis rigorously analyzes the problem of linearity of a stochastic delay-line TDC and formulates an intuitive theory to predict the linearity performance. Apolarvisualization of the phase distribution of a delay line is proposed to aid the analysis. Based on the results of this study, this thesis proposes a stochastic delay-line TDC employing a delay-locked loop (DLL) to guarantee linearity over PVT variations and to reduce the number of redundant bits. The proposed TDC is implemented in a 0.18 µm CMOS process to validate the linearity theory and the proposed solution. The 8-bit TDC samples at 60 MHz and demonstrates a linear-number-of-bit of 6.36 with only 2-bit redundancy. Consuming 25 mW from a 1.8 V supply, the TDC yields a figure-of-merit of 5.04 pJ/conversion-step. With the DLL turned off, the integral nonlinearity (INL) degrades by about a factor of two, verifying the effectiveness of the proposed solution. The TDC is measured at different temperatures and supply voltages to demonstrate robustness against PVT variations. The measurement results show excellent agreement with the behavioral simulations.
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Mäntyniemi, A. (Antti). "An integrated CMOS high precision time-to-digital converter based on stabilised three-stage delay line interpolation." Doctoral thesis, University of Oulu, 2004. http://urn.fi/urn:isbn:951427461X.
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Abstract
This thesis describes the development of a high precision time-to-digital converter (TDC) in which the conversion is based on a counter and three-stage stabilised delay line interpolation developed in this work.
The biggest design challenges in the design of a TDC are related to the fact that the arrival moment of the hit signals (start and stop) is unknown and asynchronous with respect to the reference clock edges. Yet, the time interval measurement system must provide an immediate and unambiguous measurement result over the full dynamic range. It must be made sure that the readings from the counter and the interpolators are always consistent with very high probability. Therefore, the operation of the counter is controlled with a synchronising logic that is in turn controlled with the interpolation result. Another synchronising logic makes it possible to synchronise the timing signals with multiphase time-interleaved clock signals as if the synchronising was done with a GHz-level clock, and enables multi-stage interpolation. Multi-stage interpolation reduces the number of delay cells and registers needed.
The delay line interpolators are stabilised with nested delay-locked loops, which leads to good stability and makes it possible to improve single-shot precision with a single look-up table containing the integral nonlinearities of the interpolators measured at the room temperature.
A multi-channel prototype TDC was fabricated in a 0.6 μm digital CMOS process. The prototype reaches state-of-the-art rms single-shot precision of better than 20 ps and low power consumption of 50 mW as an integrated TDC.
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UGAZIO, SABRINA. "High-performance velocity, frequency and time estimation using GNSS." Doctoral thesis, Politecnico di Torino, 2013. http://hdl.handle.net/11583/2513765.
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GNSS (Global Navigation Satellite System) receivers provide PVT solution,
where PVT stands for Position, Velocity and Time. In general, the main interest
of the common GNSS user is on the position solution and as a consequence the
main focus of the research is the improvement of the position solution accuracy.
However, many applications exist in which the measurement of both velocity
and/or time is crucial and this is the reason why the focus of this thesis is on
the Velocity and Time solution.
The PVT solution is computed through trilateration techniques, based on a TOA
(Time Of Arrival) ranging technique, therefore the PVT solution is correlated
to the measurement of time. In particular, the position solution is related to a
time measurement while the velocity solution is correlated to a frequency measurement.
Different factors that affect the velocity estimate on one side and the time estimate
on the other side are taken into account in this thesis, that in classic PVT
solution are usually neglected.
In the velocity/frequency estimate, the significant measurement is the change in
the user-satellite distance, i.e. a relative measurement, thus the measurements
errors that remain constant during the time interval over which the velocity is estimated
cancel out. Carrier-phase difference solution enables velocity accuracy in
the order of 1 mm/s, a high-level accuracy which is crucial for many applications,
including Inertial Measurement Unit (IMU) calibration, motion compensation for
Synthetic Aperture Radar (SAR) and flight reference systems. Thanks to the
cancellation of the common errors, that in the position solution represents the
very larger error sources, in the velocity solution other minor effects become the
limiting error sources. The first goal investigated in this thesis is to look for the
accuracy limit that can be achieved in the velocity/frequency solution.
The second objective is to investigate the problem of high- accuracy time solution.
As well as the position, the time is an absolute measurement, affected
by large error sources. Furthermore, the clock error is in common to all the
satellite measurements, and due to this, the common errors among the satellites
are not told apart and are in general attributed to the clock measurement. As a
result, lots of error sources that are not involved in the position solution become
dominant in the time solution. A main limiting factor in the timing accuracy is
represented by the errors in ionospheric delay estimate, where many error sources
are involved, in particular the unknown bias due to the receiver hardware.
After a part to introduce GNSS and its basic principles, with the focus on the
aspects that are more relevant for the dissertation and that allow one to outline
the motivations of the work, the thesis is divided in three main parts, two regarding
in particular the velocity/frequency solution and the last one focused on
the high-accuracy time solution.
The first step to improve the velocity solution was to notice how the performance
is much worse on the vertical solution than on the horizontal and how highly correlated
the vertical solution is to the local frequency estimate. This is due to the
geometry of GNSS, that implies that users on the Earth or close to the Earth
(as aircrafts) can see satellites all around them on the horizontal direction, but
they cannot see satellites under them, which is rejected in a poorer geometry on
the vertical direction. Due to this characteristic, an error on the pseudorange, as
the clock error is, reflects on the vertical solution more heavily than on the other
dimensions. As a result, the vertical solution can be about three times worse
than the horizontal and from the covariance matrix of the solution it can be
seen how the correlation is high in particular between the vertical and the clock
solution. This fact is true both for the position and for the velocity solution,
which means that the vertical velocity accuracy is highly correlated to the local
oscillator frequency. As a result, a way to improve the vertical velocity accuracy
is to obtain a better estimate of the local frequency. In this thesis, models for
the local oscillators and ways to integrate the frequency estimate in the GNSS
solution are investigated.
Another important aspect to improve the performance of the velocity measurement
is to improve the accuracy of the GNSS measurement. Since the measurement
used to obtain precise velocity is the carrier phase, which enables accuracy
in the order of 1 mm/s, the goal to improve the accuracy on the carrier-phase
measurement is crucial. With this objective, novel Digital Phase Lock Loops (DPLLs) has been designed, both of second and third order, with an adaptive
bandwidth algorithm. The objective was to tune the loop bandwidth according
to the input signal dynamics and noise, and use a bandwidth small enough to
reduce the noise effects as much as possible, but wide enough to properly track
the input dynamics. Since the PLL is designed for precise velocity measurement,
the performance in terms of dynamics tracking ability is crucial.
The last part of the analysis concerns the time solution. In most of cases in
GNSS, high importance is given to the position accuracy, while the residual
common biases are included in the receiver clock error. This approach makes
the time solution not very accurate. Since the main bias which affects the time
solution is the ionosphere delay, in this thesis the accuracy of the Total Electron
Content (TEC) estimate is investigated, with the focus on the measurement bias.
All the measurements which this thesis refers to are made using GPS (Global
Positioning System) only, nevertheless sometimes in the thesis it is talked about
GNSS in general. This is because the approaches considered in this thesis are
tested here using GPS, but they can be applied to all the GNSSs.
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Hordeski, Theodore J. "Digital FSK/AM/PM Sub-Carrier Modulator on a 6U-VME-Card." International Foundation for Telemetering, 1996. http://hdl.handle.net/10150/611475.
Full textAbstract:
International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California<br>Aerospace Report No. TOR-0059(6110-01)-3, section 1.3.3 outlines the design and performance requirements of SGLS (Space Ground Link Subsystem) uplink services equipment. This modulation system finds application in the U.S. Air Force satellite uplink commanding system. The SGLS signal generator is specified as an FSK (Frequency Shift Keyed)/AM (Amplitude Modulation)/PM (Phase Modulation) sub-carrier modulator. GDP Space Systems has implemented, on a single 6U-VME card, a SGLS signal generator. The modulator accepts data from several possible sources and uses the data to key one of three FSK tone frequencies. This ternary FSK signal is amplitude modulated by a synchronized triangle wave running at one half the data rate. The FSK/AM signal is then used to phase modulate a tunable HF (High-Frequency) sub-carrier. A digital design approach and the availability of integrated circuits with a high level of functionality enabled the realization of a SGLS signal generator on a single VME card. An analog implementation would have required up to three rack-mounted units to generate the same signal. The digital design improve performance, economy and reliability over analog approaches. This paper describes the advantages of a digital FSK/AM/PM modulation method, as well as DDS (Direct Digital Synthesis) and digital phase-lock techniques.
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Lu, Chung-Ting. "Design and Implementation of Low Voltage CMOS Phase-Locked-Loop and Delay-Locked-Loop." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-0703200814075900.
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Lu, Chung-Ting, and 呂宗庭. "Design and Implementation of Low Voltage CMOS Phase-Locked-Loop and Delay-Locked-Loop." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/73103347694520526926.
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碩士<br>臺灣大學<br>電子工程學研究所<br>96<br>Low-power CMOS designs have attracted great attention in the past few years. For portable wireless communication systems such as mobile phones, the power dissipation of the integrated circuits is of crucial importance as it predetermines the battery life. Even for electronic products operated at household electricity, the power consumption and the associated thermal problems are still essential design issues as the packing density of a fully integrated system increases. Besides, clocks are very important in the above mentioned portable devices. Therefore, this thesis is devoted to the implementation of clock production such as phase-locked-loops and delay-locked-loops operated at low voltage with low power consumption.
In chapter 3, by employing the forward-body-bias (FBB) technique and low-voltage circuit topologies for the individual building blocks, a phase-locked loop (PLL) is proposed to operate at reduced supply voltage and power consumption while maintaining the desirable circuit performance at multi-gigahertz frequencies. Using a standard 0.18-μm CMOS process, a 1.9-GHz PLL is implemented for demonstration. Consuming a dc power of 4.5 mW from a 0.5-V supply voltage, the fabricated circuit exhibits in-band and out-of-band phase noise of -83.4 dBc/Hz and -135.3 dBc/Hz at 100- kHz and 10-MHz frequency offset, respectively, and a side-band spur with a power level 44 dB below the carrier.
A ring-like LC QVCO technique is proposed in chapter 4. The proposed QVCO can achieve desirable phase noise and phase error performance with much less power consumption. Push-push frequency doubler technique is also used to produce the dual band signals. This QVCO is then applied in a PLL. The forward-body-bias technique and low-voltage circuit topologies described in Chapter 2 for the individual building blocks are utilized in a phase-locked loop (PLL) at reduced supply voltage and power consumption while maintaining the desirable circuit performance at multi-gigahertz frequencies. Using a standard 0.18-μm CMOS process, a 2.4-GHz PLL is implemented for demonstration. Consuming a dc power of 12 mW from a 0.5-V supply voltage, the fabricated circuit exhibits quadrature outputs with phase noise -113.05 dBc/Hz at 1-MHz frequency offset, and a side-band spur with a power level 38 dB below the carrier. Besides, the phase error is around 0.6° and the IRR is 38dB.
A low voltage, low power, low jitter, and wide range delay-locked-loop (DLL) is proposed in chapter 5. In this design low voltage circuits design approaches and the proposed voltage control delay line (VCDL) have been used to attain the above mentioned performance. Besides, problems in the conventional circuits such as linearity are solved by this new skill. In this way the delay range can cover all the control voltage. Fabricated in a standard 0.18-μm CMOS process, the simulation results show that under the supply voltage of 0.6 V, the proposed DLL can operate from 100 to 400 MHz, and the current drawn from the supply is 4 mA and 7.5 mA, separately. With the data simulated in HSPICE, the corresponding jitter simulated in the MATLAB is 25 ps to
13 ps. The DLL occupies a total area of 680 μm × 680 μm.
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Wang, You-Jen, and 王佑仁. "Design and Application of All-Digital Delay-Locked Loop and All-Digital Phase-Locked Loop." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/29732818975573400808.
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碩士<br>臺灣大學<br>電子工程學研究所<br>98<br>This thesis describes digital implementations and applications of analog circuits for delay-locked loop (DLL) and phase-locked loop (PLL). Compared with analog DLLs and PLLs, the all-digital DLLs and all-digital PLLs have the benefits such as easy process migration, no passive loop filter needed, and fast locked time. Therefore, digital equivalent implementations of analog circuits are more popular, such as delay-locked loop (DLL), phase-locked loop (PLL), clock and data recovery circuit (CDR), and frequency synthesizer.
There are four works in this thesis: all-digital DLL, PLL, CDR and frequency synthesizer. First, an all-digital DLL with adjustable duty cycles is proposed. The phase and duty cycle of output clock are fast adjusted by the time-to-digital conversion result of the input period. Therefore, the phase alignment and the duty cycle of output clock are assured in 10 cycles of input clock.
Second, a 15KHz-1.39GHz all-digital PLL with frequency multiplication by 1 to 32768 is presented. The frequency counting and binary searching methods are applied to reduce the locked time. And a programmable divider is proposed for wide frequency range applications. Furthermore, the timing resolution of the proposed digitally-controlled oscillator (DCO) is improved to 0.013ps by the capacitance difference among the varactors.
Third, a 6.34Mbps-1.5Gbps all-digital wide-range CDR circuit is presented. The proposed frequency-searching algorithm reduces the frequency locked time and eliminates the harmonic locking problem over wide-range data rates. The CDR circuit has been fabricated in 90nm CMOS process, and parts of this circuit is digital synthesized and reduce the area to 0.00368mm2, smaller than previous publish works.
Finally, an all-digital frequency synthesizer with cancellation, calibration, and correction loops is presented. The proposed cancellation, calibration and correction loops reduce the fractional spur and phase noise of output clock. And the cancellation, calibration and correction loops are digital synthesized to reduce silicon area. Furthermore, the frequency resolution of the proposed DCO is improved by adjusting the difference of control voltage between the two varactors with small capacitance difference. And a high-gain time amplifier is proposed to reduce the offset of D flip-flops.
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Lee, Sok-kyu. "Phase-locked loop, delay-locked loop, and linear decorrelating detector for asynchronous multirate DS-CDMA system." Thesis, 2001. http://library1.njit.edu/etd/fromwebvoyage.cfm?id=njit-etd2001-043.
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ChihWei-chiang and 江志偉. "Adaptive-Bandwidth and two different delay feedbacks phase-locked loop." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/35794037742197493908.
Full textAbstract:
碩士<br>南台科技大學<br>電子工程系<br>95<br>The phase-locked loop (PLL) is a key component used broadly in various integrated circuit fields in recent years. It is generally used as clock generation in VLSI or frequency synthesizer in communication systems. Fast locking time, low jitter performance and low power consumption are required in nearly all PLL applications in modem IC systems. Thus the design of PLL must generally deal with a tight tradeoff between the locking time and the amplitude of the ripple on the control line of oscillator. According to the linear-modeling of the PLL, the bandwidth should be large to achieve fast locking and be small to reduce the ripple on the control voltage while the whole loop is near or in the state of lock.
Adaptive-Bandwidth and two different delay feedbacks phase-locked loop (PLL) circuits to achieve fast locking are proposed and presented in this paper. We use controllable charge pumps to realize adaptive bandwidth scheme and a tunable delay cell to achieve different feedbacks path. Basing on a TSMC standard 0.35-μm 2P4M CMOS technology, the simulation result show that the proposed PLL circuits can achieve a fast locking time of 2 s, and a high clock frequency of 150 MHz. Moreover, the corresponding output frequency is in the range from 100 MHz to 1.2 GHz.
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Chiang, Chi-Huan, and 蔣季寰. "Digital Multiplying Delay-Locked Loop Using Switched Biasing Technique and Digital Phase-Locked Loop with Bandwidth Calibration." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/90227530337968693370.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>102<br>This thesis consists of two parts. The first part implement a digital multiplying delay-locked loop (DMDLL) using switched biasing technique. This DMDLL uses the proposed select logic and its main divider can be turned off to reduce the power consumption. The digitally-controlled oscillator (DCO) uses the switched biasing technique to reduce the low-frequency phase noise. This DMDLL is fabricated in 40-nm CMOS technology and its active area is 0.0088 mm2. The integrated RMS jitter is 2.68 ps and the power consumption is 1.51mW at the output frequency of 1050MHz.
The second part implements a digital bang-bang phase-locked loop (BBPLL) with bandwidth calibration. It is presented to against the process, voltage, and temperature (PVT) variations. A linearized model of the BBPLL is constructed to analyze the bandwidth of the BBPLL. The proposed bandwidth calibration circuit adopts the adders, the subtractors, and the comparators to replace the area-consuming division circuit, which reduces the area overhead. This BBPLL was fabricated in 40-nm CMOS technology with an active area of 0.0049 mm2. The output frequency is 5 GHz. The integrated RMS jitter is 1.242 ps, and the power consumption is 3.34 mW.
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Uttarwar, Tushar. "A digital multiplying delay locked loop for high frequency clock generation." Thesis, 2011. http://hdl.handle.net/1957/25739.
Full textAbstract:
As Moore���s Law continues to give rise to ever shrinking channel lengths, circuits are becoming more digital and ever increasingly faster. Generating high frequency clocks in such scaled processes is becoming a tough challenge. Digital phase locked loops (DPLLs) are being explored as an alternative to conventional analog PLLs but suffer from issues such as low bandwidth and higher quantization noise. A digital multiplying delay locked loop (DMDLL) is proposed which aims at leveraging the benefit of high bandwidth of DLL while at the same time achieving the frequency multiplication property of PLL. It also offers the benefits of easier portability across process and occupies lesser area.
The proposed DMDLL uses a simple flip-flop as 1-bit TDC (Time Digital Converter) for Phase Detector (PD). A digital accumulator acts as integrator for loop filter while a ��-�� DAC in combination with a VCO acts like a DCO. A carefully designed select logic in conjunction with a MUX achieves frequency multiplication. The proposed digital MDLL is taped out in 130nm process and tested to obtain 1.4GHz output frequency with 1.6ps RMS jitter, 17ps peak-to-peak jitter and -50dbC/Hz reference spurs.<br>Graduation date: 2012
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Wei, Yu-Chung, and 魏郁忠. "Wide-Range Delay-Locked Loop Using New Structure of Phase Detector." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/16671134182621058521.
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碩士<br>淡江大學<br>電機工程學系<br>91<br>The concept of phase lock is proposed in 1930 years, and is fast used in electric and communication products widely. Nowadays, the concept of phase-locked loops (PLLs) often applies in frequency synthesizers that are in inner of mobile. Due to the theory of delay-locked loops (DLLs) are proposed later than the theory of phase-locked loops, although part circuit structures among PLLs and DLLs are similar, but the concept of DLLs is simple than the concept of PLLs and easy to understand. The differences of circuit structure between DLLs and PLLs are that voltage-controlled delay line (VCDL) and voltage-controlled oscillator (VCO), and the design of VCO is the most difficult than other blocks in PLL. Therefore, if we want to produce clock synchronizer, it can save a lot of designing time that we adopt the concept of DLLs in circuit design and don’t adopt the concept of PLLs in circuit design. Additionally, the lock time of DLLs is shorter than PLLs. According to two focal point above, DLLs suit to tendency of circuit design extremely in the future.
In chapter 1, we discuss the circuit concept and structure of analog delay-locked loops and digital delay-locked loops. Finally, we are aimed at basic structure of conventional mixed-mode wide-range delay-locked loops to discuss. In chapter 2, we propose the design step that we have to understand in the design of wide-range DLLs, and the problems of limitary conditions that we have to notice in the design of wide-range DLLs. In this chapter, we first discuss the ideal design manner that mixed-mode wide-range DLLs don’t contain overlapping region of curve of VCDL. Then we discuss the practical design manner that mixed-mode wide-range DLLs contain overlapping region of curve of VCDL. Finally, we propose the design flow chart of mixed-mode wide-range DLL. In chapter 3, we propose a mixed-mode wide-range DLL designing in 0.35um CMOS 1P4M process. Through the new structure of phase detector that we propose, we make the maximum delay time of single phase output of VCDL reach 4.2 times minimum delay time of single phase output of VCDL and don’t be limited by the locking conditions of conventional phase detectors. Therefore, we can reach 40 times wide range that just needs to pull three phases output from VCDL. The operating frequency range is from 10MHz to 400MHz. Moreover, all circuit adds a confrontational circuit to reach constant KVCDL, and utilizes bandwidth-tracking principle to design current steering logic charge pump that can be used to maintain the stability and lock time.
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Lin, Tsung-Hsiang, and 林琮翔. "A Digital Controlled Multi-Phase Delay Locked Loop with Calibration Technique." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/21223633502549330752.
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碩士<br>國立高雄第一科技大學<br>電腦與通訊工程所<br>97<br>This thesis presents a digital-controlled delay line with digital to voltage converter (DVC) to achieve fast locking. In addition, the digital to voltage converter is applied in a digitally controlled Delay Locked Loop (DLL). The advantages of combining digitally controlled and voltage-controlled delay line characteristics are (1) high-resolution of delay line (2) low jitter (3) low process variation. In conventional design, DLL is usually controlled by a voltage-controlled delay line with the charge pump. The shortcoming of this approach is slow locking time. Therefore, an all-digital controlled delay-locked loop was proposed. However, the jitter is large for all-digital delay locked loop. This thesis proposes a digital to voltage converter to achieve fast locking and low jitter delay locked loop.
In addition, this thesis presents a modified calibration technique in order to improve the phase offset caused by process, voltage, temperature. We improve the traditionally continuous calibration algorithm by divide and conquer. The proposed calibration algorithm simplifies the circuit effort and making it easy to implement.
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GUO, HONG-JIE, and 郭鴻傑. "Design and Implementation of Wide-Range Multi-phase Delay-Locked Loop." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/97448936174539072818.
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碩士<br>華梵大學<br>電子工程學系碩士班<br>101<br>Delay locked loop commonly used in the phase snchronization,
Frequency multiplier and multi-phase generation. Compared to the phase locked loop .The advantages are small size,lock speed, can produce multi-phase bound stable. However delay locked loop limited harmonic lock,false lock problems and limited range of voltage controlled delay lines,restrict the range of the input signal operation.
In this thesis proposes a new voltage-controlled delay line, change the traditional architecture,Enhance the operational range of the input signal. Traditional simple Voltage-Controlled Delay Line(vcdl) from the inverter variable and capacitors, if you have using wide rang operating , you need to use switching variable capacitance, wide rang operating can be achieve ,However if using duty cycle to phase delay cell(DTP) Composition Voltage-Controlled Delay Line, Be able to resolve Traditional architecture using variable capacitance, Reduce phase errors caused by the delay
In delay locked loop based on the design of a 360 phase voltage control delay Line, Eight voltage control lines, replacing traditional single control line voltage.In addition to eight by the input signal through the circuit generates eight phases as eight loop input signal and reduce multi-stage delay units cascaded noise caused by accumulation, increased jitter and phase mismatch problems.
In this thesis, using TSMC 0.18um 1P6M 1.8V CMOS made implementation. Chip size 1.2*1.2mm2, the reference frequency 22~625MHz,, the output frequency of 22~625MHz, Output phase is eight phase ,the power consumption is 100mW.
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Tu, Yo-hao, and 涂祐豪. "A Wide Range Delay-Locked Loop with Phase Error Calibration and Frequency Multiplier." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/94233088302678434259.
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碩士<br>國立中央大學<br>電機工程研究所<br>99<br>This study presents a wide-range and multiphase DLL-based clock generator with the Phase Error Compensation loop. For more applications, we proposed a frequency multiplier to synthesize a combined clock. In this voltage control delay line, we take the multi-gain technique to achieve the wide-range operation frequency. And we proposed a Phase Error Compensation loop with the timing amplifier. It is difficult to realize a DLL in high operation frequency, so using multiphase technique can solve this problem. And the multiphase architecture can become the clock generator of a Transmitter (Tx).
This study was implemented by TSMC 180 nm 1P6M CMOS process. The input frequency range of the proposed DLL is from 80 MHz to 600 MHz with 12-phase output. The output range of frequency multiplier is from 0.96 GHz to 2.5 GHz. The chip area is 0.745 × 0.745 mm2 and the core area is 0.356 × 0.356 mm2. The power consumption is 19.2 mW at a supply of 1.8 V. The peak-to-peak jitter and rms jitter of delay locked loop are 21.22 ps and 2.62 ps at 800 MHz. The peak-to-peak jitter and rms jitter of frequency multiplier are 35.11 ps and 4.28 ps at 2.4 GHz. And the Phase Error Compensation loop can improve 33.33% of the static phase error.
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Wu, Meng-Jhe, and 吳孟哲. "Delay-Locked Loop with Static Phase Error Calibration Based on Wide-Range Operation." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/39825062253595252191.
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碩士<br>國立中央大學<br>電機工程研究所<br>96<br>To court high-frequency generation is coming with the evolution of CMOS process technology. The Phase-Locked Loop (PLL) was used for synchronous circuit between the system chips in the past. However, the voltage control oscillator have jitter accumulation problem in the PLL. Hence, Delay-Locked Loop (DLL) and frequency multiplier used to achieve the high frequency signal synchronization.
DLL with static phase error calibration based on wide-range operation is proposed in this thesis. The wide-range operation is achieved in multi-band voltage controlled delay line . The multi-band voltage controlled delay line is modified current-starved delay line. It utilizes frequency detector that detect the input frequency to switch the delay line band.
Due to dead zone of the phase detector, current mismatch of the charge pump and other non-ideally effect will cause the static phase error. The jitter performance of frequency multiplier will be worse. In order to solve the problems , the detect window phase detector is presented in thesis that is used to calibrate static phase error. DLL has a problem of locking range that is the delay time of voltage controlled delay line must between 0.5 times to 1.5 times for input clock period or it will occur the locking fault problem. Hence, we using a self-correct circuit to detect how long the delay time of the signal of voltage controlled delay line is. It also avoid the problem of locking fault.
The proposed DLL with static phase error calibration is designed in CMOS 0.18um 1P6M process. The circuit is operate at 1.8V and the input frequency range is 25MHz~250MHz. Output frequency range is 25MHz~2.5GHz. The locking time is 253ns when the input frequency is 250MHz. Without the calibration, max phase error calibration of the proposed circuit is 3.57° and after the calibration is 1.098°.The power consumption is 10.1mW. The ten times output frequency is 2.5GHz and peak to peak jitter is 22.6ps. The core area of the chip is 0.466mm^2。
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Chen, Liang-Hsin, and 陳良信. "A Wide-Range and Fast-Locking All-Digital Delay-Locked Loop Using a Phase-Tracing Delay Unit." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/52077077461624655443.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>100<br>Nowadays, system-level integration has become the main trend in the IC design fields. DLLs are widely used in SoCs for solving the clock skew issues and synchronizing each intellectual property (IP) and module. However, wide-range analog DLLs which could be designed as an IP are becoming harder to be implemented and more difficult to be designed in the advanced processes nowadays. In contrast, the all-digital DLLs (ADDLLs) are easier to be realized and integrated with the digital systems in these advanced processes. A wide-range and fast-locking ADDLL as an IP for the system-level is proposed in this work.
In this thesis, a novel phase-tracing delay unit (PTDU) will be proposed as well. The purpose of using a PTDU is to replace with the long delay line which is used in wide-range DLLs and to enlarge the operating frequency range which is over 6.7MHz-1.24GHz. Moreover, the PTDU and the CSD-based control unit achieve fast-locking time which is only 5 cycles. The FSMs and TDC-based code generators provide low jitter performance, which is 2.22ps at 1.24GHz in our measurement. The chip was fabricated in TSMC 90nm CMOS process and occupied 0.0318mm2 active area.
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Lin, Hsiao-chyi, and 林小琪. "Design of Phase Locked Loop with Spectrum Spread in Time Domain." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/20790873885438111160.
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碩士<br>國立交通大學<br>電子工程系<br>87<br>This thesis describes the design of a Phase Locked Loop which is used in CPU to be the interface between external clock and internal clock, with the function of locking the external and internal clock phase to reduce the time delay between them, and also can be a frequency synthesizer to make internal clock multiple times of external clock. For reducing the influence of EMI to meet the regulative specification, we make use of some digital circuits to spread a few percents of PLL frequency spectrum in time domain, thus the peak value of power spectrum density will be lower down to an acceptable level without changing the total energy.
This chip is designed using TSMC 0.6 mm SPTM CMOS process. Total die area excluding pad is 1000 5 1000 mm2. There are two PLL inside, the former one is used for spread spectrum, the later one is used for frequency synthesizer. It works under 3.3V power supply and input frequency is 14.318MHz. According to the simulation result, the operating frequency of VCO with 16 stages inside the former PLL is 28.636MHz; and that with 4 stages inside the later PLL is 2~256MHz.
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Lan, Jhih-Ci, and 藍志錡. "Low-Power And Delay Monotonicity Digitally Controlled Oscillator For All-Digital Phase-Locked Loop Applications." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/26786096094798248691.
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碩士<br>輔仁大學<br>電機工程學系<br>100<br>In this thesis, a low-power and delay monotonicity digitally controlled oscillator (DCO) for all-digital phase-locked loop (ADPLL) applications is presented. The proposed DCO can achieve high delay resolution, wide frequency range and low power consumption while maintaining delay monotonicity that can easily be used to different ADPLL applications. Besides, the proposed DCO is portable that can easily migrate to different technology. As a result, the proposed design is very suitable for system-on-chip (SoC) applications.
There are two type DCO structures have been proposed: interpolator DCO and varactor-interpolator DCO. The proposed interpolator DCO power consumption is 0.3368 mW at 1118 MHz, the delay resolution is 0.82 ps and the delay range is 424~1118 MHz in 90 nm CMOS process technology. The varactor-interpolator DCO power consumption is 0.2053 mW at 838 MHz, the delay resolution is 2.98 ps and the delay range is 322~838 MHz in 90 nm CMOS process technology.
The proposed DCO is integrated into an ADPLL which is an important clocking module in SoC applications. The proposed design of ADPLL is discussed with some simple block that can use gate-level or Verilog Hardware Description Language (Verilog HDL) to implement. So, the design time and design complexity can be reduced by using Verilog HDL.
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Hsin, Su Chung, and 蘇忠信. "The Analysis and Design of All Digitall Phase Locked Loop with New Fine-Tune Delay Elements." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/59153180411208438646.
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碩士<br>長庚大學<br>電子工程研究所<br>92<br>Abstract
The thesis describes the analysis and design of All Digital Phase-Locked Loop. It consists of seven units, which includes Frequency Coarse Tune Detector, Frequency Fine Tune Detector, Phase Detector, Controlled Unit, Divider, Decoder and Digital Controlled Oscillator. Frequency Coarse Tune Detector uses the binary search method to accomplish frequency coarse tune detection. Frequency fine tune detector uses the accumulated frequency tolerance to complete frequency fine tune detection. Controlled unit determines and executes the signal from frequency coarse tune detector, frequency fine tune detector, phase detector and divider and then generates the control word for digital controlled oscillator. Through decoder to digital controlled oscillator, the correct frequency signal from digital controlled oscillator is finally obtained .
A new idea to accomplish the fine tune of digital controlled oscillator is proposed in the paper. This proposed method uses the idea when MOS turns on and turns off, the equivalent capacitor difference obtained from the drain is treated a fine tune variable of digital controlled oscillator. The fine tune resolution achieves 1.713ps. The output range of the digital controlled oscillator is 308MHz — 587MHz and power consumption is 10mW. All the above results are based on post-layout simulations. The layout area of all digital phase locked-loop is 250um x 250um, which does not include PADs. The layout area includes 16 PADs layout is 1100um x 1100um. The post-layout simulation jitter is smaller than 5ps and the whole chip power consumption is 96 mW.
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Liao, Hung-Jen, and 廖宏仁. "An Auto Dead-zone Reduction Phase Detector Circuit Design for All-Digital Delay-Locked Loop Applications." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/3e5b72.
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碩士<br>國立雲林科技大學<br>電子工程系<br>107<br>The difference in the time that the central clock arrives at each trigger unit in the synchronous digital circuit is called clock skew. The time delay of the clock signal paths is called clock skew, which can cause circuit malfunction or system instability. Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) can be used to solve the clock skew problem. Although both PLL and DLL can solve the clock skew problem, PLL has more frequency synthesis than DLL, and its complexity is higher. If we only need to correct the clock phase offset, we usually use DLL. The DLL circuit is simple and has low output jitter characteristics. Besides, the design of the All-Digital DLL (ADDLL) is simple, and it is easier to migrate the designed digital circuit from one process to another. To be applied in digital embedded systems, the DLL of this study will adopt all-digital circuit design architecture.
In general, the operation of the DLL firstly detects the phase relationship between the input reference point and the output point by the phase detector (PD) and then corrects the clock offset by the control circuit. Therefore, PD is a crucial part of the DLLs. In general, when the DLL phase has been corrected to a small phase difference, the PD will not detect two clock differences. It is called the PD's dead-zone, and the dead-zone size directly affects the DLL phase-locking performance. Intuitively, the transistor size can be adjusted by circuit simulation results to achieve dead-zone improvement. However, in the process, voltage, temperature, and other variables, it still can not guarantee as expected. To this end, this paper proposes a new simple PD circuit architecture with automatic reduction of the dead-zone loop. When this PD applied to the full digital delay phase-locked loop, it is verified by simulation. In the CMOS 90nm process, the circuit operating frequency is 200 MHz $\sim$ 2 GHz. This PD can automatically compensate for the process variation and other factors when the circuit starts. The offset PD dead-zone enables the DLL to achieve low dead zone lock, and the clock phase difference is locked within two picoseconds.
Keywords：Dead-zone, Phase Detector, Auto dead-zone reduction.
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蕭彥邦. "An All-Digital Phase-Locked Loop Using a Time-Amplifier TDC with Calibration mechanism." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/47k9yp.
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碩士<br>國立交通大學<br>電機工程學系<br>103<br>In recent years, the 3C products (Computer, Communication and Consumer electronics) have developed extraordinarily quickly. For wireless communication ICs, in either the transmitter or receiver, they all need a phase-locked loop (PLL) circuit to supply a clean clock source, so the phase-locked loop which is the core of the circuit is a very important clock generator. The analog phase-locked loop (APLL) has been developing for several years. However, in recent years, the all-digital phase-locked loop (ADPLL) has gradually become the mainstream in process scaling and small chip area. The drawback of the analog phase-locked loop is that it must be redesigned with process scaling down and the size of resistor and capacitor in the filter cannot be scaled down with the process, while the ADPLL is consisted of the digital logic circuits which can be scaled down directly. The ADPLL improves the analog phase-locked loop to process scaling down directly. However, the performance of ADPLL is usually not as good as the APLL, so it is necessary to put more efforts on how to improve the jitter performance of the ADPLL.
In this thesis, we implement the ADPLL by using full-custom design flow. We design a calibration mechanism for the time amplifier which can increase the amplification range of the time amplifier. This time amplifier with the calibration mechanism is used in the time to digital converter (TDC), and improves the resolution of the TDC to reduce the jitter of the ADPLL. The output frequency of ADPLL is designed as 2.4GHz.
From the measurement result, the output frequency of the ADPLL can be locked at 2.4GHz, the amount of the peak-to-peak jitter is 26.67 ps, and the RMS jitter is 3.38ps. The power consumption of this chip is 16.76mW. The core area of the chip is 0.27 .
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Fang, Ying-Chih, and 方盈智. "Real-time particle detection based on a microwave resonator using phase-locked loop techniques." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/24658667049399908004.
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碩士<br>國立中興大學<br>奈米科學研究所<br>101<br>We demonstrated a real-time detection of 70 μm-in-diameter particles suspended in water based on a microwave resonator detector. On a 0.5 mm-thick printed circuit board, the 3.5 GHz microstrip resonator (MSR) has a 150 μm-sized hole at its end. When a particle passes through the hole, the local dielectric constant changes and causes a shift in resonance frequency of about 0.24 ~ 1.3 MHz for one to probe. The best signal-to-noise ratio (SNR) measured by vector network analyzer (VNA) of phase detection was 23 at the resonance frequency with the intermediate frequency bandwidth (IFB) of 2 kHz. The average time delay of particle’s passing through was about 3.35 ms, which was comparable to the flow velocity of 0.16 m/s. Alternatively, a phase-locked loop (PLL) was employed for measuring the change of the resonant frequency. The best phase resolution of our home-made PLL system is 3∙10-5 rad with a highest detection speed of 3.6 kHz. The PLL could successfully register the through events of single particles: an average frequency shift of 0.244 MHz with an average time delay of 3.34 ms. The best SNR measured by PLL was 65.1, a value better than the result by VNA.
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Jiang, Bo-Qian, and 姜柏阡. "A 6 Gbps Delay-Locked-Loop-Based Clock and Data Recovery Circuit with an Infinite Phase Compensation Technique." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/84813177936174575945.
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碩士<br>國立中央大學<br>電機工程學系<br>101<br>In recent year, according to the rapid evolution of process and computer network development, the various bandwidth requirement such as short distance like chip-to-chip communication and long distance like fiber-optic communication is increased. The use of serial data transmission substitute for the parallel one. The serial data transmission are widely used for bus in computer such as PCI-Express, SATA, USB, and used for fiber-optic network like SONET. Most of these systems adopted the serial link architecture and operate at gigahertz. This study presents a clock and data recovery (CDR), and takes SATA 6 Gbps specification as reference material. The CDR employs the Delay-Locked Loop (DLL) as data recovery (DR) loop which consists of two sets of complementary voltage-controlled delay line (VCDL). It can solve the problem of delay range limitation.
This study presents the CDR circuit fabricated in a 90-nm CMOS process. The dual-loop-based CDR consists of a phase-locked loop (PLL) and a DR loop. Unlike the commonly used PLL-based CDR, the bandwidth for the clock jitter suppression and the specific jitter transfer function (JTF) could be optimized through the PLL and DR loop, respectively. With regard to the DR loop, the DLL could be used for the phase alignment between the input data and the clock signal. However, once the input data accompanies the frequency offset, the DLL may suffer from the limitation of the finite phase tracking range, resulting in the erroneous function. Thus, this study proposes a infinitely phase-compensated DLL (IPDLL), which correlates and swaps the two complementary VCDL if necessary. The IPDLL-based CDR generates the continuous clock phase shifts for data tracking to resolve the operating range limitation of the convenient DLL control scheme. In addition, it exhibits the fast-locking, jitter-peaking-, and jitter-accumulation-free characteristic. As a result, in terms of the CDR setting, conforming that the gain of error signal E(s) of -3 dB lies at the jitter frequency of 4.2±2.1 MHz, the 6-Gb/s input data is simulated with the 3-nH wire bonding, and the RMS and peak-to-peak jitter of the recovered clock are 1.73 ps and 7.77ps, respectively. The chip core area of DR and PLL occupy 0.11 and 0.045 mm2, respectively. The total power consumption is around 79.8 mW at supply of 1.2V.
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Cheng, Yong Xin, and 程永信. "Design and implementation of low-power phase-locked loop in time-division multiple-access receiver." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/55516945897615614880.
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Narasimhan, Srinath S. "Circuit Optimization Using Efficient Parallel Pattern Search." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7704.
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Circuit optimization is extremely important in order to design today's high performance integrated circuits. As systems become more and more complex, traditional optimization techniques are no longer viable due to the complex and simulation intensive nature of the optimization problem. Two examples of such problems include clock mesh skew reduction and optimization of large analog systems, for example Phase locked loops. Mesh-based clock distribution has been employed in many high-performance microprocessor designs due to its favorable properties such as low clock skew and robustness. However, such clock distributions can become quite complex and may consist of hundreds of nonlinear drivers strongly coupled via a large passive network. While the simulation of clock meshes is already very time consuming, tuning such networks under tight performance constraints is an even daunting task. Same is the case with the phase locked loop. Being composed of multiple individual analog blocks, it is an extremely challenging task to optimize the entire system considering all block level trade-offs.
In this work, we address these two challenging optimization problems i.e.; clock mesh skew optimization and PLL locking time reduction. The expensive objective function evaluations and difficulty in getting explicit sensitivity information make these problems intractable to standard optimization methods. We propose to explore the recently developed asynchronous parallel pattern search (APPS) method for efficient driver size tuning. While being a search-based method, APPS not only provides the desirable derivative-free optimization capability, but also is amenable to parallelization and possesses appealing theoretically rigorous convergence properties.
In this work it is shown how such a method can lead to powerful parallel optimization of these complex problems with significant runtime and quality advantages over the traditional sequential quadratic programming (SQP) method. It is also shown how design-specific properties and speeding-up techniques can be exploited to make the optimization even more efficient while maintaining the convergence of APPS in a practical sense. In addition, the optimization technique is further enhanced by introducing the feature to handle non-linear constraints through the use of penalty functions. The enhanced method is used for optimizing phase locked loops at the system level.
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Sheng, Duo, and 盛鐸. "An All Digital Phase Locked-Loop (ADPLL) with Fast Lock-In Time--Analysis, Implementation and Application." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/96233833440043668566.
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碩士<br>國立中正大學<br>電機工程研究所<br>87<br>In this thesis, a new all digital phase-locked loop (ADPLL) is proposed. The architecture of proposed ADPLL is based on [12], but some modifications are made. The phase-lock process is separated into frequency prediction, frequency comparison and phase detection that reduce phase lock_in cycle significantly. By using our lock_in algorithm, our ADPLL can accomplish phase lock process within 25 reference clock cycles. A digitally-controlled oscillator (DCO) is the core of the ADPLL. The DCO we used is a 3-stage ring oscillator with a 7-bit binary weighted control mechanism, and operating linear with DCO control word. The operating frequency range of new ADPLL is 203MHz - 493MHz and jitter is 250ps (at 235MHz). The whole chip is fabricated in 0.35um CMOS 1P4M process. The transistor number is 2984 and core size is 338um * 362um.
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Lin, Keng-Yu, and 林耿裕. "Design of All-Digital Phase-Locked Loop with Low Power Time-to-Digital Converter for Zigbee Applications." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/35744715902679348558.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>101<br>Due to the progress in technology, device size and power consumption keep scaling down. Moreover, more and more function blocks are integrated in a single chip. However, there are also some non-ideal effects accompanied with the progressing CMOS technology. Analog devices suffer from the degrading characteristic such as decreasing supply voltage and increasing leakage current. Thus, it is a tendency that using digital circuits to replace analog circuits.
The 2.4-GHz industrial, scientific and medical (ISM) band is utilized by various short-range wireless systems such as WLAN, Bluetooth and Zigbee. Recently, phase-locked loops (PLLs) are widely used in wireless and wireline communication. As mentioned above, all-digital phase-locked loops (ADPLLs) are more suitable for advanced technology. Thus, this thesis presents an all-digital phase-locked loop with low power time-to-digital (TDC) converter.
The design is analyzed and modeled first, than the implantation is presented. Finally, the chip is fabricated in the TSMC 0.18 μm CMOS technology. The power consumption of TDC is reduced 66%. The measured phase noise are -114 dBc/Hz and -118 dBc/Hz at 1 MHz and 10 MHz offset, respectively and the rms jitter is 0.64 ps. The power consumption is 14.1 mW from 1.8 V supply voltage.
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Wang, Tun-Ju, and 王敦儒. "Digital-to-Time Converter Based Phase-Locked Loop and Frequency Divider Design for Wireline and Wireless Applications." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/2uw428.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>106<br>Digital-to-Time converters (DTC) have been widely used and it serves as one of the building blocks in many timing applications, such as the fractional-N PLL. The delay is of a DTC is controlled by a digital code, and the amount of delay is usually varied by switching on/off of a set of discrete elements, such as unit delay cells or charging capacitors. This thesis focuses on the applications of DTC.
This thesis includes two works. The first work is “A 1.5-GHz Sub-Sampling Fractional-N PLL for Spread-Spectrum Clock Generator”. This work employs a fractional-N sub-sampling PLL, and supports spread-spectrum clocking. This work aims to reduce the electromagnetic interference (EMI) of a clock generator with its neighboring devices. It is fabricated in TSMC 180-nm CMOS process. Measurement results have shown that the EMI reduction with spread-spectrum clocking enabled is 18.98 dB. Measured RMS jitter of the output signal is 0.88 ps. With a 1.8-V supply voltage, the power consumption is measured to be 11.1 mW.
The second work is “A 0.635~162.5 MHz Multiple Output Fractional Divider Using Phase Rotating Technique”. This work is realized by phase rotating technique, supporting multiple frequency outputs, with output frequency range of 0.635-162.5 MHz. This work aims to reduce the number of clock generators in a single SoC. It is fabricated in TSMC 90-nm CMOS process. Measurement results show that the proposed fractional divider functions properly under both integer and fractional division. Furthermore, this work supports dual outputs with two different division ratios, realizing a single input, multiple outputs frequency divider.
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Ko, Chih-Chieh, and 葛致杰. "An Inductor Current Balancing Technique for Fast-locking Delay-locked Loop Based Four-phase Buck Converter with Transient-modulated Constant On-time Control for Fast Load Transient Response." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/my8ny7.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>107<br>This thesis presents a fast-locking delay-locked loop (DLL) based four-phase DC-DC buck converter, which is manipulated by transient-modulated constant on-time control (TMCOT). Besides, a novel inductor current balancing method called pulse-width-shrunk technique (PWST) is proposed and it is capable of simultaneously calibrating the duty cycle and the phase error of pulse-width modulation (PWM) signals in the DLL-based multi-phase converter.
For the sake of much faster load transient response, the DLL adopts a modified dual edge triggered phase detector (DET-PD), namely automatic switching single/dual edge triggered phase detector (ASS/DET-PD), to accomplish the fast-locking mechanism.
The buck converter is operated at 10 MHz switching frequency, and it employs a 330 nH inductor and a 22 μF output capacitor. The input voltage is 3.3V, and the output voltage is 1.8V. The load current ranges from 0.4A to 1.4A. The fully-integrated circuit is implemented in TSMC 0.18-μm CMOS process and the chip area is 6.17mm^2.
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Elshazly, Amr. "Performance enhancement techniques for low power digital phase locked loops." Thesis, 2012. http://hdl.handle.net/1957/31116.
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Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions.
In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques.<br>Graduation date: 2013<br>Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014
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Lin, Jian-Da, and 林建達. "Delay-Locked Loops with phase error calibration." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/11571946077067957002.
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碩士<br>長庚大學<br>電機工程學系<br>100<br>Because of the development of technology, smaller scale of MOSFET, channel effect, low supply voltage, and process-voltage-temperature variations, circuit design has become more and more difficult. The synchronous problem between circuits is undoubtedly important in system integration.
Delay-locked loop is designed and implemented to solve the problem of clock synchronization and tracking. Delay-locked loop is widely used because of easy design, stability, and low power consumption. This thesis presents a new method to improve DLL’s phase error. Due to the current mismatch of Charge Pump, the input and output have phase error. We use the D flip-flop’s setup time to reduce current mismatch of Charge Pump in DLL.
This chip is implemented in a 0.18μm CMOS process with 1.8V power supply voltage. The total area of the chip is 1*1mm2. The operating frequency range is from 700MHz to 900MHz. The power consumption is 46mW. The phase error is 3.3ps and peak-to-peak jitter is 14ps at 900MHz.
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Huang, Chih Wei, and 黃智威. "Delay-Locked Loops with phase error calibration." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/02572634294723259429.
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Lin, Cheng-Chung, and 林正中. "All-Digital Phase-Locked Loops with Multiple-Delay Switching TDC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/54737721259529853018.
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碩士<br>國立交通大學<br>電機工程學系<br>105<br>As the Internet of Things (IOT) and 5G applications become more and more popular, the importance of full-customer and the SOC design increases as well. Phase-Locked Loops (PLLs), as one of the key parts in SOC designs, are widely used in the Clock and Data Recovery (CDR) and wireless communication systems. In the early development of PLLs, the designs were realized by analog approach. Continuous-time signals are transferred among different blocks and the whole system is analyzed the in frequency domain, which can be derived through the Laplace Transformation. From the prospect of the design complexity, the analog PLL (APLL) is a good choice because it requires less complexity. During the time when the product has long Life-Cycle, traditional analog PLLs are capable to deal with almost all diversity of applications. However, as the number of portable devices grows and the process technology advances, the advantages of all digital PLLs (ADPLLs) are gradually discovered and also reveals that it has the penitential to replace the APLLs. Because the signals transferred between each two blocks are digital values (0 or 1), a DPLL provides better performance in anti-noise ability. If a system is realized through digital circuit implementation, then there is no need to redesign with the process technology scaling down, which brings a brilliant merit in designing short-life-cycle products. Moreover, analog PLL circuits use passive components, which occupy lots of area, and the speed of analog PLL circuits is usually slower than that of digital PLL circuits. Therefore, the discussions about all-digital phase-locked-loops (ADPLLs) take up a large proportion of phase-locked-loop researches.
In this thesis, we implement ADPLLs by using full-custom design flow. For the first chip, we propose a time-to-digital converter with multiple-delay switching mechanism which can detect the phase-locked state and decide the optimized delay path according to the detected state. The proposed DCO with a linearly periodic digital-to-frequency relationship operates from 130MHz to 1.22GHz. For the second chip based on the first chip, a Time Amplifier (TA) and a Most-Significant-Bit (MSB) detector are introduced to achieve higher resolution and lower power consumption for the proposed TDC.
Both of chips are designed to lock at 800MHz. The measurement results show that the first chip has a peak-to-peak jitter of 36.67ps. The area of the core circuit in ADPLL is 0.1088mm2, and the power dissipation is 17.5mW. For the second chip, the post-simulation shows the value of the peak-to-peak jitter is 13.6ps, and the power dissipation is 9.1mW. The core circuit occupies the area of 0.0694 mm2.
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Kuo, Chun Yi, and 郭駿逸. "Delay-Locked Loops with fast lock and phase error calibration." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/87995079017614349992.
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碩士<br>長庚大學<br>電機工程學系<br>100<br>Delay-Locked Loops (DLLs) have been widely used in many 3C products, particularly in high-speed communication devices. So precise timing is necessary for chipset design. With the advance of process technology, the operating speeds of digital circuits have been rapidly increased; more and more circuits can be integrated into the same chip. Therefore, the synchronization between circuits becomes pretty important, especially for high-speed systems because clock offset (clock skew) is a crucial factor in determining their performance.
Generally, a charge pump used in DLLs is to change the voltage level by charging and discharging the loop filter. However, when the charge pump is charging and discharging the loop filter, there is a problem with output current mismatch due to the MOS transistor mismatch and process, voltage, and temperature (PVT) variation, etc. In this paper, we propose a method to solve the problem existing in traditional DLLs. For example, before our calibration, there is a static phase error between reference signal and output signal while the DLL is locked. This way, synchronization capability will get worse. So, we find out the hold time of D flip-flop by using a counter and then proceed with calibration. Hence, in our research, we focus on the issue of current mismatch to improve the signal quality and enhance its synchronization. Meanwhile, adding a fast locked circuit to the chip can help us speed up the locked time.
This chip is fabricated in a 0.18μm CMOS process, and it has a operating frequency range from 600MHz to 900MHz. The total chip area is 0.94mm x 0.8mm. Its power consumption measured at 900MHz is 27.47mW under a 1.8V power supply voltage. Under this situation, the phase error between input and output is 3.4ps ; the peak-to-peak and rms (root-mean-square) jitter is 10.5ps and 1.12ps , respectively.
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Teng, Kuang-Fu, and 鄧匡復. "Design and Implementation of Delay-Locked Loops with Static Phase Error Calibration." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/51519481036341790529.
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碩士<br>國立臺灣大學<br>電機工程學研究所<br>97<br>Conventional CMOS charge-pump circuits have some current mismatch problems. The current mismatch induces a phase error which deteriorates the performance of delay-locked loop systems or phase-lock loop systems. In this dissertation, we describes on the design and application of delay-locked loop systems and we use three architectures and circuits to improve the phase error in the synchronization systems, and there is no extra replica charge-pump needed; these architectures and circuits have been fabricated in 0.18µm CMOS to verify the circuits technique and measure the systems calibration result.
Hence, using a digital technique with auto-tracking ability to calibrate the current mismatch of the charge-pump in delay-locked loop systems; and one chip is using a time amplifier[9] to amplify two different input phase and in the other chip, we propose a new switched-delay phase-frequency detector is well suited to the delay-locked loop systems to magnify the phase error in the original system, that increase the phase detectable resolution of phase-frequency detector to fine tune charge-pump calibration.
Next, we propose a new technique is digital different reset time of phase-frequency detector circuit to separate UP and Down that are outputs of phase-frequency detector that control charge-pump will charge or discharge reset time, that will shift the location of phase error to achieve in-phase.
We design three architectures and circuits can cover 10% process variation, and these are all can improve the phase error. The area of these three chips were all 0.85mm * 1.0mm, and reference frequency is 500MHz and voltage on power supply is 1.8V, the power consumes was less than 30mW.