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Journal articles on the topic 'Time-delay phase locked loop'

Author: Grafiati

Published: 5 June 2025

Last updated: 8 July 2025

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1

Bassam, Harb, Qudah Mohammad, Ghareeb Ibrahim, and Harb Ahmad. "Chaos and bifurcation in time delayed third order phase-locked loop." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 1431–38. https://doi.org/10.11591/ijece.v11i2.pp1431-1438.

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In this paper, the modern nonlinear theory is applied to a third order phase locked loop (PLL) with a feedback time delay. Due to this delay, different behaviors that are not accounted for in a conventional PLL model are identified, namely, oscillatory instability, periodic doubling and chaos. Firstly, a Pade approximation is used to model the time delay where it is utilized in deriving the state space representation of the PLL under investigation. The PLL under consideration is simulated with and without time delay. It is shown that for certain loop gain (control parameter) and time delay values, the system changes its stability and becomes chaotic. Simulations show that the PLL with time delay becomes chaotic for control parameter value less than the one without time delay, i.e., the stable region becomes narrower. Moreover, the chaotic region becomes wider as time delay increases.

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2

Spalvieri, A., and M. Magarini. "Wiener's Analysis of the Discrete-Time Phase-Locked Loop With Loop Delay." IEEE Transactions on Circuits and Systems II: Express Briefs 55, no. 6 (2008): 596–600. http://dx.doi.org/10.1109/tcsii.2007.916861.

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3

Harb, Bassam, Mohammad Qudah, Ibrahim Ghareeb, and Ahmad Harb. "Chaos and bifurcation in time delayed third order phase-locked loop." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 2 (2021): 1431. http://dx.doi.org/10.11591/ijece.v11i2.pp1431-1438.

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In this paper, the modern nonlinear theory is applied to a third order phase locked loop (PLL) with a feedback time delay. Due to this delay, different behaviors that are not accounted for in a conventional PLL model are identified, namely, oscillatory instability, periodic doubling and chaos. Firstly, a Pade approximation is used to model the time delay where it is utilized in deriving the state space representation of the PLL under investigation. The PLL under consideration is simulated with and without time delay. It is shown that for certain loop gain (control parameter) and time delay values, the system changes its stability and becomes chaotic. Simulations show that the PLL with time delay becomes chaotic for control parameter value less than the one without time delay, i.e, the stable region becomes narrower. Moreover, the chaotic region becomes wider as time delay increases.

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4

Subhash, Patel *. Abhishek Vaghela Bhavin Gajjar. "DESIGN OF PHASE LOCKED LOOP." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 5 (2017): 312–20. https://doi.org/10.5281/zenodo.573512.

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In this work, we have designed CDR-PLL for 1GHz frequency. The design is carried out in the 180nm CMOS technology. We have use Hogge phase detector with the Kim-Lee delay cell based VCO. The designed CDR-PLL is tested by applying the 8B-10B encoded data and the simulation results are represented. The obtained results show that the clock is recovered successfully.

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5

Radwan, Eyad, Khalil Salih, Emad Awada, and Mutasim Nour. "Modified phase locked loop for grid connected single phase inverter." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (2019): 3934. http://dx.doi.org/10.11591/ijece.v9i5.pp3934-3943.

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Connecting a single-phase or three-phase inverter to the grid in distributed generation applications requires synchronization with the grid. Synchronization of an inverter-connected distributed generation units in its basic form necessitates accurate information about the frequency and phase angle of the utility grid. Phase Locked Loop (PLL) circuit is usually used for the purpose of synchronization. However, deviation in the grid frequency from nominal value will cause errors in the PLL estimated outputs, and that’s a major drawback. Moreover, if the grid is heavily distorted with low order harmonics the estimation of the grid phase angle deteriorates resulting in higher oscillations (errors) appearing in the synchronization voltage signals. This paper proposes a modified time delay PLL (MTDPLL) technique that continuously updates a variable time delay unit to keep track of the variation in the grid frequency. The MTDPLL is implemented along a Multi-Harmonic Decoupling Cell (MHDC) to overcome the effects of distortion caused by gird lower order harmonics. The performance of the proposed MTDPLL is verified by simulation and compared in terms of performance and accuracy with recent PLL techniques.

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6

Eyad, Radwan, Salih Khalil, Awada Emad, and Nour Mutasim. "Modified phase locked loop for grid connected single phase inverter." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 5 (2019): 3934–43. https://doi.org/10.11591/ijece.v9i5.pp3934-3943.

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Connecting a single-phase or three-phase inverter to the grid in distributed generation applications requires synchronization with the grid. Synchronization of an inverter-connected distributed generation units in its basic form necessitates accurate information about the frequency and phase angle of the utility grid. Phase Locked Loop (PLL) circuit is usually used for the purpose of synchronization. However, deviation in the grid frequency from nominal value will cause errors in the PLL estimated outputs, and that’s a major drawback. Moreover, if the grid is heavily distorted with low order harmonics the estimation of the grid phase angle deteriorates resulting in higher oscillations (errors) appearing in the synchronization voltage signals. This paper proposes a modified time delay PLL (MTDPLL) technique that continuously updates a variable time delay unit to keep track of the variation in the grid frequency. The MTDPLL is implemented along a Multi-Harmonic Decoupling Cell (MHDC) to overcome the effects of distortion caused by gird lower order harmonics. The performance of the proposed MTDPLL is verified by simulation and compared in terms of performance and accuracy with recent PLL techniques.

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7

Zhou, Duo, Jin Yi Zhang, and Bo Ye. "An Implementation of Wide-Range Digital Delay Locked Loop." Advanced Materials Research 945-949 (June 2014): 2226–29. http://dx.doi.org/10.4028/www.scientific.net/amr.945-949.2226.

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This paper presents an all digital delay-locked loop (DLL) to achieve wide range operation, fast lock and process immunity. To keep track of any potential phase problem caused by environmental variations, a delay compensation mechanism is employed. Utilizing the delay compensation controller (DCC), the proposed DLL can overcome the false-lock problem in conventional designs. It is fast locking because the DLL’s initial state can be detected by the delay compensation controller and the initial large phase difference can be eliminated. The proposed DLL is implemented in a 0.13μm CMOS process. The experimental result shows that the chip could work in a wide frequency range from 10 MHz to 1 GHz, with less than 20 cycles lock-in time, 10-ps delay resolution, and 6.4 mW at 1 GHz power dissipation.

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8

D Patel, Nilesh, and Amisha P Naik. "PHASE LOCKED LOOP USING SUB HARMONIC INJECTION TECHNIQUE WITH AUTO ADJUSTED DELAY LOCKED LOOP." ICTACT Journal on Microelectronics 6, no. 3 (2020): 959–63. https://doi.org/10.21917/ijme.2020.0166.

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For high speed communication applications; jitter, phase noise and power consumption are most critical parameters required to be considered for PLL designs. A sub harmonically injection locking concept can be used in PLL to reduce jitter and phase noise. Such design is very effective for high frequency applications. This article presents design for low jitter, phase noise, power dissipation for 7.5 GHz Phase locked loop using sub harmonic injection technique with auto adjusted Delay locked loop in 180-nm CMOS technology. The measured phase noise at 1 MHz reference offset frequency is 122.31 dBc/Hz with rms jitter is 127 fs. The overall power dissipation is 13.99 mW for proposed design.

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9

Goodberlet, J., J. Ferrera, and H. I. Smith. "Analogue delay-locked loop for spatial-phase locking." Electronics Letters 33, no. 15 (1997): 1269. http://dx.doi.org/10.1049/el:19970858.

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10

Goodberlet, J. "Spatial-phase-locked electron-beam lithography with a delay-locked loop." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 15, no. 6 (1997): 2293. http://dx.doi.org/10.1116/1.589632.

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11

Dandapathak, M., S. Sarkar, and B. C. Sarkar. "Nonlinear dynamics of an optical phase locked loop in presence of additional loop time delay." Optik 125, no. 23 (2014): 7007–12. http://dx.doi.org/10.1016/j.ijleo.2014.08.072.

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12

Issam, A. Smadi, A. Albatran Saher, and Q. Ababneh Taher. "A synchronization technique for single-phase grid applications." International Journal of Power Electronics and Drive Systems 13, no. 4 (2022): 2181~2189. https://doi.org/10.5281/zenodo.7328831.

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The utility grid disturbances like DC offset and harmonic components can severely affect the estimated variables from the phase-locked loop (PLL), resulting in poor performance of the system relying on it. Therefore, there is an emerging need for well-designed PLL algorithms ensuring robust response against different operating conditions. This paper proposes a simple singlephase PLL algorithm with inherent DC offset and specific harmonic orders rejection capability. Utilizing adaptive time-delay fictitious signal generation. A full mathematical model of the proposed PLL has been provided. The proposed PLL is compared with other filter-based single-phase PLLs, to validate its simplicity and excellent performance.

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13

Piqueira, José Roberto C. "Delay-free phase-locked loop ring: Equilibrium and phase perturbation." Physica D: Nonlinear Phenomena 404 (March 2020): 132344. http://dx.doi.org/10.1016/j.physd.2020.132344.

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14

Manaj, Dandapathak. "Effect of High Frequency Gain on the Performance of Optical Costas Loop in Face of Loop Delay." Indian Journal of Science and Technology 15, no. 25 (2022): 1224–33. https://doi.org/10.17485/IJST/v15i25.1682.

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Abstract <strong>Objectives:</strong> Optical costas loops (OCLs) are widely used in optical communication as homodyne receivers. Due to use of different electronic counterparts and fibre optic cable inherent loop delay always presents in the system. The steady state behaviours of optical costas loop are highly affected by the presence of loop delay. Different nonlinear behaviours may be observed due to presence of delay. There are two main objectives of this article. Firstly, how OCL can be operated as stable receiver up to some large value of loop delay by using a proportional plus integrating type loop filter (LF). Secondly, how a controlled chaotic optical signal can be generated from OCL by choosing the system parameters in correct manner. <strong>Methods:</strong> To investigate system behaviours of OCL both analytical and numerical methods have been used. Stability analysis of OCL has been done by Routh-Hurwitz method. From stability analysis, it is possible to predict the stable and unstable behaviour of the OCL in presence of delay and how system stability can be improved by high frequency gain value of LF. Numerical methods have also been used to solve the nonlinear equation of OCL to observe real time behaviours.<strong> Findings:</strong> Analytical findings show that loop stability can be improved by increasing the value of high frequency gain of LF. For large value of loop delay, chaotic oscillation of phase error may be observed in OCL. The chaotic oscillation can also be controlled by high frequency gain with certain extent value of loop delay. All the numerical findings have been properly verified with numerical results. <strong>Novelty:</strong> This article describes how effects of loop delay can be controlled to run OCL in steady as well as in unsteady state. From designer’s point of view this study would be helpful to choose correct values of system parameters to improve the performance of OCL in optical communication. It also gives the idea for generation of chaotic optical signal, which is used in secured communications. Keywords: Optical Costas loop; Optical Phase locked loop Phase detector; Loop filter; Nonlinear dynamics; and optical communications

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15

Shruti, Suman, G. Sharma K., and K. Ghosh P. "250 MHz Multiphase Delay Locked Loop for Low Power Applications." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 6 (2017): 3323–31. https://doi.org/10.11591/ijece.v7i6.pp3323-3331.

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Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8 V . It has power consumption of 1.39 mW at 125 center frequency with locking range from 0.5 MHz to 250 MHz . MHz

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16

Yu, Ya-Juan, and Zai-Hua Wang. "A Fractional-Order Phase-Locked Loop with Time-Delay and Its Hopf Bifurcation." Chinese Physics Letters 30, no. 11 (2013): 110201. http://dx.doi.org/10.1088/0256-307x/30/11/110201.

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17

Park, Gun-Ho, Jae-Jin Lee, Seong-Jin Oh, and Kang-Yoon Lee. "Low-Power All Digital Delay Locked Loop with Dynamically Phase Error Tracking for a PVT Compensation Loop." Journal of Korean Institute of Electromagnetic Engineering and Science 31, no. 7 (2020): 571–76. http://dx.doi.org/10.5515/kjkiees.2020.31.7.571.

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18

Suman, Shruti, K. G. Sharma, and P. K. Ghosh. "250 MHz Multiphase Delay Locked Loop for Low Power Applications." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 6 (2017): 3323. http://dx.doi.org/10.11591/ijece.v7i6.pp3323-3331.

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Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 <em>um </em>CMOS technology and at power supply of 1.8<em>V </em>. It has power consumption of 1.39 <em>mW </em>at 125 <em>MHz</em> center frequency with locking range from 0.5 <em>MHz</em> to 250 <em>MHz.</em>

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19

Han, Sung-Rung, Chi-Nan Chuang, and Shen-Iuan Liu. "A Time-Constant Calibrated Phase-Locked Loop With a Fast-Locked Time." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 1 (2007): 34–37. http://dx.doi.org/10.1109/tcsii.2006.883826.

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20

Lee, T. H., and J. F. Bulzacchelli. "A 155-MHz clock recovery delay- and phase-locked loop." IEEE Journal of Solid-State Circuits 27, no. 12 (1992): 1736–46. http://dx.doi.org/10.1109/4.173100.

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21

Xu, Pengfei, Zhenyu Wei, Zhiyu Guo, et al. "A Real-Time Circuit Phase Delay Correction System for MEMS Vibratory Gyroscopes." Micromachines 12, no. 5 (2021): 506. http://dx.doi.org/10.3390/mi12050506.

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With the development of the designing and manufacturing level for micro-electromechanical system (MEMS) gyroscopes, the control circuit system has become a key point to determine their internal performance. Nevertheless, the phase delay of electronic components may result in some serious hazards. This study described a real-time circuit phase delay correction system for MEMS vibratory gyroscopes. A detailed theoretical analysis was provided to clarify the influence of circuit phase delay on the in-phase and quadrature (IQ) coupling characteristics and the zero-rate output (ZRO) utilizing a force-to-rebalance (FTR) closed-loop detection and quadrature correction system. By deducing the relationship between the amplitude-frequency, the phase-frequency of the MEMS gyroscope, and the phase relationship of the whole control loop, a real-time correction system was proposed to automatically adjust the phase reference value of the phase-locked loop (PLL) and thus compensate for the real-time circuit phase delay. The experimental results showed that the correction system can accurately measure and compensate the circuit phase delay in real time. Furthermore, the unwanted IQ coupling can be eliminated and the ZRO was decreased by 755% to 0.095°/s. This correction system realized a small angle random walk of 0.978°/√h and a low bias instability of 9.458°/h together with a scale factor nonlinearity of 255 ppm at room temperature. The thermal drift of the ZRO was reduced to 0.0034°/s/°C at a temperature range from −20 to 70 °C.

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22

BANERJEE, TANMOY, BISHWAJIT PAUL, and B. C. SARKAR. "BIFURCATION, CHAOS AND THEIR CONTROL IN A TIME-DELAY DIGITAL TANLOCK LOOP." International Journal of Bifurcation and Chaos 23, no. 08 (2013): 1330029. http://dx.doi.org/10.1142/s0218127413300292.

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This paper reports the detailed parameter space study of the nonlinear dynamical behaviors and their control in a time-delay digital tanlock loop (TDTL). At first, we explore the nonlinear dynamics of the TDTL in parameter space and show that beyond a certain value of loop gain parameter the system manifests bifurcation and chaos. Next, we consider two variants of the delayed feedback control (DFC) technique, namely, the time-delayed feedback control (TDFC) technique, and its modified version, the extended time-delayed feedback control (ETDFC) technique. Stability analyses are carried out to find out the stable phase-locked zone of the system for both the controlled cases. We employ two-parameter bifurcation diagrams and the Lyapunov exponent spectrum to explore the dynamics of the system in the global parameter space. We establish that the control techniques can extend the stable phase-locked region of operation by controlling the occurrence of bifurcation and chaos. We also derive an estimate of the optimum parameter values for which the controlled system has the fastest convergence time even for a larger acquisition range. The present study provides a necessary detailed parameter space study that will enable one to design an improved TDTL system.

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23

Nasir, Qassim. "Behaviour of fractional loop delay zero crossing digital phase locked loop (FR-ZCDPLL)." International Journal of Electronics 105, no. 1 (2017): 153–63. http://dx.doi.org/10.1080/00207217.2017.1355021.

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24

Ding, Yi, Xi Duan, and Jun Liu. "A 3 GHz Semi-Digital Delay Locked Loop with High Resolution." Applied Mechanics and Materials 571-572 (June 2014): 881–84. http://dx.doi.org/10.4028/www.scientific.net/amm.571-572.881.

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A high speed and high resolution semi-digital DLL (Delay Locked Loop) circuit will be discussed. The circuit is composed of three blocks: delay line, phase detector and digital finite-state machine (FSM). The delay line consists of two steps: the coarse tuning by tapping and the fine delay using interpolation to enable a resolution as high as 2 picoseconds. With the two steps approach and configuration of delay line, 3 GHz speed and picoseconds-level resolution can be achieved.

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25

Chen, Chao-Chyun, and Shen-Iuan Liu. "An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line." IEEE Journal of Solid-State Circuits 43, no. 11 (2008): 2413–21. http://dx.doi.org/10.1109/jssc.2008.2004532.

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26

Zhang, Chenglin, Junru Chen, and Wenjia Si. "Analysis of Phase-Locked Loop Filter Delay on Transient Stability of Grid-Following Converters." Electronics 13, no. 5 (2024): 986. http://dx.doi.org/10.3390/electronics13050986.

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To ensure precise phase estimation within the q-axis of the phase-locked loop (PLL), integrating a filter into the q-axis loop is essential to mitigate grid-voltage harmonics. Nevertheless, the intrinsic delay characteristics of this filter impede PLL synchronization during significant grid disturbances. This study begins by developing mathematical models for three types of filters—moving-average filter (MAF) for eliminating odd harmonic components, dq-frame cascaded delayed signal cancellation (dqCDSC) filter, and notch filter (NF). Following the reduction in filter orders, a third-order nonlinear large-signal model of the PLL, incorporating an additional q-axis internal filter, is formulated. Using phase plane analysis, this study investigates the transient synchronism of the grid-following converter (GFL) and explores the influence of delay time constants from the three PLL filters on its behavior while delineating the boundaries of their basins of attraction. Theoretical findings indicate that, relative to the traditional SRF-PLL, incorporating an internal filter into the PLL compromises the transient synchronous stability of GFL. Specifically, greater filter delay time constants exacerbate the GFL’s vulnerability to transient instability amid substantial grid disturbances. Hence, careful consideration is essential when using MAF-PLL and NF-PLL in situations demanding high synchronization stability. The theoretical analyses are validated using Matlab/Simulink to verify their accuracy.

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27

Bany Issa, Mohammad A., Zaid A. Al Muala, and Pastora M. Bello Bugallo. "Simple solution of DC-offset rejection based phase-locked loop for single-phase grid-connected converters." Renewable Energy and Environmental Sustainability 9 (2024): 4. http://dx.doi.org/10.1051/rees/2023024.

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Distributed Generators (DG) systems based on Renewable Energy Sources (RES) such as hydro, wind, and solar power plants have been spread widely due to their lower cost and the advanced capability of connecting them with the grid. The power generated from the DG must be shaped to be interfaced with the grid employing power electronics converters. The grid-connected power electronics converters must be synchronized with the grid (i.e., the same fundamental component of the grid frequency, phase, amplitude, and sequence). Synchronization techniques are employed to achieve accurate and fast grid synchronization between the converter and the grid. The existence of (DC-offset) in the input of Phase Locked Loop (PLL) caused synchronization problems as it causes oscillations in the estimated fundamental grid phase, frequency, and amplitude. In addition, the closed-loop system stability can be affected. This work proposes a simple technique for grid synchronization based on PLL with a phase angle correction. The proposed method was developed using Transfer Delay (TD) and Delay Signal Cancelation (DSC) operators; then, the small single model and stability analysis was employed. Several scenarios were developed to compare the proposed method with previous methods using MATLAB/Simulink tool. The scenarios involve introducing phase jumps, DC offsets, and amplitude changes to the grid voltage. Additionally, the grid frequency was also changed. The results show that the proposed PLL can solved the DC-offset problem using any delay time and fully synchronized with the grid. Moreover, the proposed PLL has the fastest dynamic response and shortest synchronization time over the other methods from literature.

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28

Jurgo, Marijan. "ALL DIGITAL PHASE-LOCKED LOOP / VISIŠKAI SKAITMENINĖ FAZĖS DERINIMO KILPA." Mokslas - Lietuvos ateitis 5, no. 2 (2013): 128–32. http://dx.doi.org/10.3846/mla.2013.24.

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The paper reviews working principles of phase-locked loop and drawbacks of classical PLL structure in nanometric technologies. It is proposed to replace the classical structure by all-digital phase-locked loop structure. Authors described the main blocks of all-digital phase-locked loop (time to digital converter and digitally controlled oscillator) and overviewed the quantization noise arising in these blocks as well as its minimization strategies. The calculated inverter delay in 65 nm CMOS technology was from 8.64 to 27.71 ps and time to digital converter quantization noise was from −104.33 to −82.17 dBc/Hz, with tres = 8.64–27.71 ps, TSVG = 143–333 ps, FREF = 20–60 MHz. Article in Lithuanian. Santrauka Nagrinėjama fazės derinimo kilpa (FDK), jos veikimas, klasikinės struktūros FDK trūkumai nanometrinėse technologijose, galimi jų sprendimo būdai. Siūlomas perėjimas prie visiškai skaitmeninės fazės derinimo kilpos. Aprašomi pagrindiniai visiškai skaitmeninės FDK blokai – laikinis skaitmeninis keitiklis (LSK) ir skaitmeniniu būdu valdomas generatorius (SVG). Aptariamas LSK ir SVG atsirandantis kvantavimo triukšmas ir jo mažinimo priemonės. Apskaičiuota 65 nm KMOP technologijoje pasiekiama inverterio vėlinimo trukmė, lygi nuo 8,64 iki 27,71 ps, ir LSK triukšmo lygis, lygus nuo −104,33 iki −82,17 dBc/Hz, kai inverterio vėlinimo trukmė t res = 8,64–27,71 ps, SVG generuojamo signalo periodas TSVG = 143–333 ps, o atraminio signalo dažnis FREF = 20–60 MHz.

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29

B R, Mr Chethan, Punith H D, Abhishek Gowda H A, Manoj B S, and Rahul H R. "Design of Phase Locked Loop." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 12 (2024): 1–6. https://doi.org/10.55041/ijsrem39446.

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A Phase-Locked Loop (PLL) is a crucial feedback control system used to synchronize the phase of an output signal with a reference signal. This paper explores the design, analysis, and applications of PLLs in modern communication systems, digital circuits, and power electronics. The study covers the fundamental components of a PLL—phase detector, low-pass filter, and voltage-controlled oscillator (VCO)—and their interactions in achieving phase synchronization. Key performance parameters such as lock time, jitter, stability, and noise sensitivity are examined in detail. Furthermore, the paper discusses advanced PLL architectures, including digital PLLs (DPLLs) and all-digital PLLs (ADPLLs), highlighting their advantages in high-speed and low-power applications. Simulation and experimental results validate the theoretical analysis, demonstrating the PLL's effectiveness in frequency synthesis, clock recovery, and modulation/demodulation tasks. The findings underscore the PLL's versatility and its continued relevance in evolving technologies such as 5G networks, IoT devices, and mixed- signal integrated circuits. Key Words: Phase detector, loop filter, VCO, frequency divider.

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30

Wang, Xinjie, and Tadeusz Kwasniewski. "A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop." Circuits and Systems 06, no. 01 (2015): 13–19. http://dx.doi.org/10.4236/cs.2015.61002.

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31

Park, Sungkyung, Youngdon Choi, Sang-Geun Lee, Yeon-Jae Jung, Sin-Chong Park, and Wonchan Kim. "Low-jitter phase-locked loop based on pseudo-differential delay elements." Electronics Letters 37, no. 11 (2001): 669. http://dx.doi.org/10.1049/el:20010460.

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32

Ramos, R. T., and A. J. Seeds. "Delay, linewidth and bandwidth limitations in optical phase-locked loop design." Electronics Letters 26, no. 6 (1990): 389. http://dx.doi.org/10.1049/el:19900254.

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33

Kao, Shao-Ku, Hsiang-Chi Cheng, and Jian-Da Lin. "A self-calibrated delay-locked loop with low static phase error." International Journal of Circuit Theory and Applications 44, no. 4 (2015): 929–44. http://dx.doi.org/10.1002/cta.2114.

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34

Asghar, Haroon, and John G. McInerney. "Control of Timing Stability, and Suppression in Delayed Feedback Induced Frequency-Fluctuations by Means of Power Split Ratio and Delay Phase-Dependent Dual-Loop Optical Feedback." Applied Sciences 11, no. 10 (2021): 4529. http://dx.doi.org/10.3390/app11104529.

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We experimentally demonstrated a power split ratio and optical delay phase dependent dual-loop optical feedback to investigate the suppression of frequency-fluctuations induced due to delayed optical feedback. The device under investigation is self-mode-locked (SML) two-section quantum-dash (QDash) laser operating at ∼21 GHz and emitting at ∼1.55 μm. The effect of two selective combinations of power split ratios (Loop-I: −23.29 dB and Loop-II: −28.06 dB, and Loop-I and Loop-II: −22 dB) and two optical delay phase settings ((i) stronger cavity set to integer resonance and fine-tuning the weaker cavity, (ii) weaker cavity set to integer resonance and fine-tuning of stronger cavity) on the suppression of cavity side-bands have been studied. Measured experimental results demonstrate that delayed optical feedback induced frequency-fluctuations can be effectively suppressed on integer resonance as well as on full delay range tuning (0–84 ps) by adjusting coupling strength −22 dB through Loop-I and Loop-II, respectively. Our findings suggest that power split ratio and delays phase-dependent dual-loop optical feedback can be used to maximize the performance of semiconductor mode-locked lasers.

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Song, Young-Jin, Thomas Pany, and Jong-Hoon Won. "Theoretical Upper and Lower Limits for Normalized Bandwidth of Digital Phase-Locked Loop in GNSS Receivers." Sensors 23, no. 13 (2023): 5887. http://dx.doi.org/10.3390/s23135887.

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Determining the loop noise bandwidth and the coherent integration time is essential and important for the design of a reliable digital phase-locked loop (DPLL) in global navigation satellite system (GNSS) receivers. In general, designers set such parameters approximately by utilizing the well-known fact that the DPLL is stable if the normalized bandwidth, which is the product of the integration time and the noise bandwidth, is much less than one. However, actual limit points are not fixed at exactly one, and they vary with the loop filter order and implementation method. Furthermore, a lower limit on the normalized bandwidth may exist. This paper presents theoretical upper and lower limits for the normalized bandwidth of DPLL in GNSS receivers. The upper limit was obtained by examining the stability of DPLL with a special emphasis on the digital integration methods. The stability was investigated in terms of z-plane root loci with and without the consideration of the computational delay, which is a delay induced by the calculation of the discriminator and the loop filter. The lower limit was analyzed using the DPLL measurement error composed of the thermal noise, oscillator phase noise, and dynamic stress error. By utilizing the carrier-to-noise density ratio threshold which indicates the crossing point between the measurement error and the corresponding threshold, the lower limit of the normalized bandwidth is obtained.

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Li, X., W. Zhang, C. Wang, et al. "A ring-oscillator-based 5.2-ps bin-size integrated circuit for time measurements." Journal of Instrumentation 20, no. 03 (2025): C03034. https://doi.org/10.1088/1748-0221/20/03/c03034.

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Abstract High-resolution time measurement is essential in time-of-flight positron-emission tomography and in high-energy physics experiments. The increasing demands for imaging accuracy and detector performance necessitate high-resolution and high-precision timing circuits. Based on a ring-oscillator delay line incorporating a phase-locked loop, a delay-locked loop, and a passive interpolation technique, we have developed a circuit that achieves an average bin size down to 5.2 ps in a 55-nm CMOS process. High resolution poses challenges in bin-size uniformity, multi-channel integration, power consumption, readout bandwidth, and potential bubble codes. In this prototype we primarily focus on achieving high resolution and establishing a test system. Design and simulation results will be presented, with preparations for testing on-going. In the subsequent iterations we will balance other issues and gradually research a production-ready design.

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Tian, Jie, Kai Li, Yongsheng Cheng, Nan Xie, and Dong Hou. "Real-time loop gain and bandwidth measurement of phase-locked loop." Review of Scientific Instruments 89, no. 12 (2018): 124703. http://dx.doi.org/10.1063/1.5063334.

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Ishak, S. N., J. Sampe, Z. Yusoff, and M. Faseehuddin. "ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW." Jurnal Teknologi 84, no. 1 (2021): 219–30. http://dx.doi.org/10.11113/jurnalteknologi.v84.17123.

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An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. This paper reviews some state-of-art of the ADPLL structures based on their applications and analyses its major implementation block, which is the digital-controlled oscillator (DCO). The DCO is evaluated based on its CMOS scaling and its performance in ADPLL, such as the power consumption, the chip area, the frequency range, the supply voltage, and the phase noise. Based on the review, the reduction in CMOS scaling decreases the transistor size in ADPLL design which leads to a smaller area and a low power dissipation. The combination of the time-to-digital (TDC) and the digital-to-time converter (DTC) that is used as the phase-frequency detector (PFD) in ADPLL is proposed to reduce the power and phase noise performance due to their high linearity design. The delay cell oscillator is found to consume more power at higher operating frequency, but it has an advantage of having less complexity and consuming less power and area in the circuit compared to the LC tank oscillator. For future work, it is recommended that an ADPLL-based LO of RFID transceiver with lowest voltage supply implementation is chosen and the use of the TDC-less as the PFD is selected due to its small area. While for the DCO, the delay cell will be designed due to its simpler implementation and occupy small area.

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Pei, Yu Jie, Yun Shan Zhang, Jian Guo Xu, et al. "Implementation of Single Phase Locked Loop Based on FPGA and its Application in SVC." Advanced Materials Research 986-987 (July 2014): 1826–32. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1826.

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Whereas three-phase phase locked loop could not get accurate phase position under three-phase unbalanced condition of the power grid, the design of single phase locked loop is implemented in the principle of single phase locked loop, based on FPGA technology. the paper explains design difficulties of single phase locked loop in detail, puts forward adaptive sampling scheme using single phase locked loop under variable frequency, increases accuracy of SVC sampling system. And tests response speed of phase locked loop via Real Time Digital Simulator for Power Systems (RTDS), through final verification in Fushun Lishizhai SVC Project, the design could meet system requirement for voltage phase accuracy.

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Imran, Rajib, Monirul Islam, and Abdullah Al Kafi. "Synthesizable Digital Phase Locked Loop Implementation." Advanced Materials Research 684 (April 2013): 317–21. http://dx.doi.org/10.4028/www.scientific.net/amr.684.317.

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Phase locked loop (PLL) is a very common circuit in the most of the electrical devices. The systems where needed clock or data recovery or frequency synthesis, PLL is the most cost effective and efficient choice that from cellular phone in our hands to the computers, televisions, radios and a different controller, PLL is everywhere. Due to ever increasing growth of the digital systems especially in the wireless communication, the Digital PLL (DPLL) has been developed to overcome the disadvantages of analog techniques such as large noise, power hungry, parameter sensitivity etc. Besides DPLL provides faster lock-in time, better testability, stability and portability over different process. The most of the resources available discussed about the theoretical model of the DPLL which is not synthesizable, that’s why a model is presented here keeping in mind that must be fully digital and synthesizable. The proposed PLL structure is fully digital, has the design flexibility with reduced hardware, low power consumption and higher power efficiency.

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Yue, Yang, Cuie Zheng, Yunfeng Han, and Yujie Ouyang. "Anti-Multipath Underwater Acoustic Time-Delay Detection Algorithm Based on Dual-Delta Correlators." Journal of Physics: Conference Series 2718, no. 1 (2024): 012098. http://dx.doi.org/10.1088/1742-6596/2718/1/012098.

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Abstract For the underwater acoustic (UAC) positioning system based on continuous waveform signal, the time-delay estimation of the Line-of-sight (Los) is not robust under the UAC strongly time-varying multipath channel. So an anti-multipath time-delay detection algorithm based on dual-delta (DD) correlators is proposed in this paper to address the issue. The algorithm uses a differential processing code-phase discriminator model to improve the traditional delay-locked-loop (DLL) time-delay detection algorithm, and combines it with the signal tracking loop adapted to the UAC channel condition to estimate time-delay. Theoretical analysis indicates that due to the reduction of local code interval and the differential processing operation, the proposed algorithm effectively mitigates the effect of time-varying multipath signals on time-delay estimation compared with conventional methods. Simulation analysis further demonstrates that the proposed algorithm can robustly detect the Los and achieve high-precision time-delay estimation under the time-varying multipath channel. The algorithm shows great potential for practical applications.

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Adesina, Naheem Olakunle, and Ashok Srivastava. "Memristor-Based Loop Filter Design for Phase Locked Loop." Journal of Low Power Electronics and Applications 9, no. 3 (2019): 24. http://dx.doi.org/10.3390/jlpea9030024.

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The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations.

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Majek, Cedric, Pierre-Olivier Lucas De Peslouan, André Mariano, Hervé Lapuyade, Yann Deval, and Jean-Baptiste Bégueret. "Voltage Controlled Delay Line with Phase Quadrature Outputs for [0.9-4]GHz Factorial Delay Locked Loop Dedicated to Zero-IF Multi-Standard Local Oscillator." Journal of Integrated Circuits and Systems 5, no. 1 (2010): 23–32. http://dx.doi.org/10.29292/jics.v5i1.307.

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This paper presents the design and the measurement results of a novel Voltage Controlled DelayLine (VCDL) dedicated to an original architecture of Delay Locked Loop (DLL): the Factorial DelayLocked Loop (F-DLL). Based on the multiphase ring oscillator technique, the proposed VCDL offers,among others, two outputs in phase quadrature. These last ones allow the F-DLL to be zero-IF compliantand becomes a good candidate for multi-standard local oscillator. The proposed circuit hasbeen fabricated in a 130nm CMOS-SOI technology from STMicroelectronics. Measurement resultsconfirm the low quadrature phase error of the topology (inferior to 5°) and the ability of the F-DLL tosynthesize the [0.9-4] GHz band, being suited for GSM up to WIMAX applications, while offering veryinteresting performances in term of phase noise and settling time.

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Xia, L., H. Chen, Y. Huang, Z. Hong, and P. Y. Chiang. "100-Phase, dual-loop delay-locked loop for impulse radio ultra-wideband coherent receiver synchronisation." IET Circuits, Devices & Systems 5, no. 6 (2011): 484. http://dx.doi.org/10.1049/iet-cds.2011.0112.

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Chen, Zhujia, Haigang Yang, Fei Liu, and Yu Wang. "A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA." Journal of Semiconductors 32, no. 10 (2011): 105009. http://dx.doi.org/10.1088/1674-4926/32/10/105009.

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Anupama, Patil* Dr P.H.Tandel. "DESIGN AND MODELLING HILBERT TRANSFORM BASED PHASE DETECTOR FOR ALL DIGITAL PHASE LOCKED LOOP." DESIGN AND MODELLING HILBERT TRANSFORM BASED PHASE DETECTOR FOR ALL DIGITAL PHASE LOCKED LOOP 5, no. 5 (2016): 134–38. https://doi.org/10.5281/zenodo.51007.

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The Phase Locked Loop (PLL) is an almost always used electronics circuit for communication systems like modulator, demodulator, frequency generator and frequency synthesizer etc. All-digital phase locked loop (ADPLL) is digital version of the PLL. In this paper, a novel Hilbert transform based phase detection system for all-digital phase locked loop (ADPLL) is presented. The digital discrete time components are used to realize the phase detector system reducing the complexity of the design. The Hilbert transform based phase detection system provides a definite advantage over conventional analog phase detectors with both sinusoidal and its Quadrature signal. The studied system is modelled and tested in the MATLAB/Simulink environment

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Lee, Kwang-Hun, and Young-Chan Jang. "A 125 MHz CMOS Delay-Locked Loop with 32-phase Output Clock." Journal of the Korean Institute of Information and Communication Engineering 17, no. 1 (2013): 137–44. http://dx.doi.org/10.6109/jkiice.2013.17.1.137.

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Lin, Gong-Ru, and Yung-Cheng Chang. "Phase-locked-loop-based delay-line-free picosecond electro-optic sampling system." Review of Scientific Instruments 74, no. 4 (2003): 2255–61. http://dx.doi.org/10.1063/1.1536256.

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Ramos, R. T., and A. J. Seeds. "Erratum: Delay, linewidth and bandwidth limitations in optical phase-locked loop design." Electronics Letters 26, no. 22 (1990): 1922. http://dx.doi.org/10.1049/el:19901240.

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Kao, Shao-ku. "A delay-locked loop with self-calibration circuit for reducing phase error." Microelectronics Journal 44, no. 8 (2013): 663–69. http://dx.doi.org/10.1016/j.mejo.2013.04.006.

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