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Santos, Osmar Marchi dos. "Run time detection of timing errors in real-time systems." Thesis, University of York, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.495893.
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Bates, Lakesha. "ANALYSIS OF TIME SYNCHRONIZATION ERRORS IN HIGH DATA RATE ULTRAWIDEBAN." Master's thesis, University of Central Florida, 2004. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2582.
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Emerging Ultra Wideband (UWB) Orthogonal Frequency Division Multiplexing (OFDM) systems hold the promise of delivering wireless data at high speeds, exceeding hundreds of megabits per second over typical distances of 10 meters or less. The purpose of this Thesis is to estimate the timing accuracies required with such systems in order to achieve Bit Error Rates (BER) of the order of magnitude of 10-12 and thereby avoid overloading the correction of irreducible errors due to misaligned timing errors to a small absolute number of bits in error in real-time relative to a data rate of hundreds of megabits per second. Our research approach involves managing bit error rates through identifying maximum timing synchronization errors. Thus, it became our research goal to determine the timing accuracies required to avoid operation of communication systems within the asymptotic region of BER flaring at low BERs in the resultant BER curves. We propose pushing physical layer bit error rates to below 10-12 before using forward error correction (FEC) codes. This way, the maximum reserve is maintained for the FEC hardware to correct for burst as well as recurring bit errors due to corrupt bits caused by other than timing synchronization errors.M.S.E.E.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
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Parker, Peter A., and Melina Lake. "Signal Emitter Localization Using Telemetry Assets." International Foundation for Telemetering, 2013. http://hdl.handle.net/10150/579671.
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ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NVTelemetry ground stations spread over geographically diverse areas are well suited for use in passively locating the source of a distant transmitted signal. In a favorable positioning of receive sites, the accuracy of these passive localization techniques can compete with the accuracy of radars. In these cases, use of receive only assets is a less expensive alternative than the use of a radar's scarce resources. Until recently, the major technical challenge to implementation of the passive localization techniques of time-difference of arrival (TDOA) and frequency-difference of arrival (FDOA) has been the frequency and time stability of geographically separated receivers. Advances in GPS based timing and frequency references has made the implementation of TDOA and FDOA feasible. This paper shows how these limitations have been overcome using the current telemetry assets at the Reagan Test Site in Kwajalein Atoll.
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Cochrane, Angela J. "When to correct errors when teaching a new task to children with autism." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc955059/.
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The purpose of this experiment was to investigate Tosti's proposal about the timing of feedback. The study examined whether it is better to correct immediately after the error occurs or whether it is better to wait until immediately before the next opportunity to respond. In addition, it aimed to determine whether corrections delivered at different times produced different learner affects. Four children with autism were taught to label two sets of pictures under the two different conditions. Results showed that the timing of the feedback yields similar results in regards to number of correct responses and total trial count. However, in regards to time spent in teaching and learner affect, correcting errors before the next opportunity to respond showed to be the more efficient procedure and produced more favorable affect.
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Zimpeck, Alexandra Lackmann. "Timing vulnerability factor analysis in master-slave D flip-flops." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/134459.
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O dimensionamento da tecnologia trouxe consequências indesejáveis para manter a taxa de crescimento exponencial e levanta questões importantes relacionadas com a confiabilidade e robustez dos sistemas eletrônicos. Atualmente, microprocessadores modernos de superpipeline normalmente contêm milhões de dispositivos com cargas nos nós cada vez menores. Esse fator faz com que os circuitos sejam mais sensíveis a variabilidade ambiental e aumenta a probabilidade de um erro transiente acontecer. Erros transientes em circuitos sequenciais ocorrem quando uma única partícula energizada deposita carga suficiente perto de uma região sensível. Flip-Flops mestreescravo são os circuitos sequencias mais utilizados em projeto VLSI para armazenamento de dados. Se um bit-flip ocorrer dentro deles, eles perdem a informação prévia armazenada e podem causar um funcionamento incorreto do sistema. A fim de proporcionar sistemas mais confiáveis que possam lidar com os efeitos da radiação, este trabalho analisa o Fator de Vulnerabilidade Temporal (Timing Vulnerability Factor - TVF) em algumas topologias de flip-flops mestre-escravo em estágios de pipeline sob diferentes condições de operação. A janela de tempo efetivo que o bit-flip ainda pode ser capturado pelo próximo estágio é definido com janela de vulnerabilidade (WOV). O TVF corresponde ao tempo que o flip-flop é vulnerável a erros transientes induzidos pela radiação de acordo com a WOV e a frequência de operação. A primeira etapa deste trabalho determina a dependência entre o TVF com a propagação de falhas até o próximo estágio através de uma lógica combinacional com diferentes atrasos de propagação e com diferentes modelos de tecnologia, incluindo também as versões de alto desempenho e baixo consumo. Todas as simulações foram feitas sob as condições normais pré-definidas nos arquivos de tecnologia. Como a variabilidade se manifesta com o aumento ou diminuição das especificações iniciais, onde o principal problema é a incerteza sobre o valor armazenado em circuitos sequenciais, a segunda etapa deste trabalho consiste em avaliar o impacto que os efeitos da variabilidade ambiental causam no TVF. Algumas simulações foram refeitas considerando variações na tensão de alimentação e na temperatura em diferentes topologias e configurações de flip-flops mestre-escravo. Para encontrar os melhores resultados, é necessário tentar diminuir os valores de TVF, pois isso significa que eles serão menos vulneráveis a bit-flips. Atrasos de propagação entre dois circuitos sequenciais e frequências de operação mais altas ajudam a reduzir o TVF. Além disso, estas informações podem ser facilmente integradas em ferramentas de EDA para ajudar a identificar os flip-flops mestre-escravo mais vulneráveis antes de mitigar ou substituí-los por aqueles tolerantes a radiação.Technology scaling has brought undesirable issues to maintain the exponential growth rate and it raises important topics related to reliability and robustness of electronic systems. Currently, modern super pipelined microprocessors typically contain many millions of devices with ever decreasing load capacitances. This factor makes circuits more sensitive to environmental variations and it is increased the probability to induce a soft error. Soft errors in sequential circuits occur when a single energetic particle deposits enough charge near a sensitive node. Master-slave flip-flops are the most adopted sequential elements to work as registers in pipeline and finite state machines. If a bit-flip happens inside them, they lose the previous stored information and may cause an incorrect system operation. To provide reliable systems that can cope with radiation effects, this work analysis the Timing Vulnerability Factor (TVF) of some master-slave D flip-flops topologies in pipeline stages under different operating conditions. The effective time window, which the bit-flip can still be captured by the next stage, is defined as Window of Vulnerability (WOV). TVF corresponds to the time that a flip-flop is vulnerable to radiation-induced soft errors according to WOV and clock frequency. In the first step of this work, it is determined the dependence between the TVF with the fault propagation to the next stage through a combinational logic with different propagation delays and with different nanometer technological models, including also high performance and low power versions. All these simulations were made under the pre-defined nominal conditions in technology files. The variability manifests with an increase or decreases to initial specification, where the main problem is the uncertainty about the value stored in sequential. In this way, the second step of this work evaluates the impact that environmental variability effect causes in TVF. Some simulations were redone considering supply voltage and temperature variations in different master-slave D flip-flop topologies configurations. To achieve better results, it is necessary to try to decrease the TVF values to reduce the vulnerability to bit-flips. The propagation delay between two sequential elements and higher clock frequencies collaborates to reduce TVF values. Moreover, all the information can be easily integrated into Electronic Design Automation (EDA) tools to help identifying the most vulnerable master-slave flip-flops before mitigating or replacing them by radiation hardened ones.
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Dunsmure, Louise C. ""Can I trust you with my medicines?" A grounded theory study of patients with Parkinson's disease perceptions of medicines management." Thesis, University of Bradford, 2012. http://hdl.handle.net/10454/5649.
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Introduction: People with Parkinson's disease require individualised
medication regimens to achieve symptomatic control whilst managing
complications of the treatments and the underlying disease. Patients
should continue to receive their individualised regimen when they are
admitted to hospital but studies have highlighted that this may not
happen. There is a paucity of research about patients' perceptions of the
management of anti-parkinsonian medicines during a hospital admission
and the aim of this study was to explore the perceptions of Parkinson's
disease patients admitted to Leeds Teaching Hospitals about the
management of their anti-parkinsonian medications.Method: Grounded theory methodology was used to allow detailed
exploration of patients' perceptions and to generate theory about this
under-researched area. Face to face, semi-structured interviews were
conducted with 13 Parkinson's disease patients during their hospital
admission, fully transcribed and analysed using the constant comparative
approach.
Results: Categories contributing to the core category of 'patient anxiety'
were identified as 'maintaining usual medication routine', 'access to
anti-parkinsonian medications', 'accuracy and consistency', 'trust in
healthcare professionals' and 'staff knowledge about Parkinson's
disease'. Strategies used to manage the anxiety were related to the
categories 'utilising expertise' in Parkinson's disease and 'patient
involvement' in their care.
Discussion: The theory suggests that some patients have negative
perceptions about the management of their medicines during a hospital
admission. Areas for practice development are presented along with
areas for future research.
Conclusion: This study provides new insight into the perceptions of
patients with Parkinson's disease about the management of their
medicines during a hospital admission.
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Dunsmure, Louise Charlotte. ""Can I trust you with my medicines?" : a grounded theory study of patients with Parkinson's disease perceptions of medicines management." Thesis, University of Bradford, 2012. http://hdl.handle.net/10454/5649.
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Introduction: People with Parkinson's disease require individualised medication regimens to achieve symptomatic control whilst managing complications of the treatments and the underlying disease. Patients should continue to receive their individualised regimen when they are admitted to hospital but studies have highlighted that this may not happen. There is a paucity of research about patients' perceptions of the management of antiparkinsonian medicines during a hospital admission and the aim of this study was to explore the perceptions of Parkinson's disease patients admitted to Leeds Teaching Hospitals about the management of their antiparkinsonian medications.Method: Grounded theory methodology was used to allow detailed exploration of patients' perceptions and to generate theory about this under-researched area. Face to face, semi-structured interviews were conducted with 13 Parkinson's disease patients during their hospital admission, fully transcribed and analysed using the constant comparative approach. Results: Categories contributing to the core category of 'patient anxiety' were identified as 'maintaining usual medication routine', 'access to antiparkinsonian medications', 'accuracy and consistency', 'trust in healthcare professionals' and 'staff knowledge about Parkinson's disease'. Strategies used to manage the anxiety were related to the categories 'utilising expertise' in Parkinson's disease and 'patient involvement' in their care. Discussion: The theory suggests that some patients have negative perceptions about the management of their medicines during a hospital admission. Areas for practice development are presented along with areas for future research. Conclusion: This study provides new insight into the perceptions of patients with Parkinson's disease about the management of their medicines during a hospital admission.
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Koeslag, Francois. "A detailed analysis of the imperfections of pulsewidth modulated waveforms on the output stage of a class D audio amplifier." Thesis, Stellenbosch : University of Stellenbosch, 2009. http://hdl.handle.net/10019.1/3972.
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Thesis (PhD (Electrical and Electronic Engineering))--University of Stellenbosch, 2009.Although the Class D topology offers several advantages, its use in audio amplification has previously been limited by the lack of competitiveness in fidelity compared to its linear counterparts. During the past decade, technological advances in semiconductor technology have awakened new interest since competitive levels of distortion could now be achieved. The output stage of such an amplifier is the primary limiting factor in its performance. In this dissertation, four non-ideal effects existing in this stage are identified and mathematically analysed. The analytical analysis makes use of a well-established mathematical model, based on the double Fourier series method, to model the imperfections introduced into a naturally sampled pulsewidth modulated waveform. The analysis is complemented by simulation using a strategy based on Newton’s numerical method. The theory is verified by a comparison between the analytical-, simulated- and experimental results.
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Perez, Andrade Isaac. "Timing-error-tolerant iterative decoders." Thesis, University of Southampton, 2016. https://eprints.soton.ac.uk/400254/.
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Iterative decoders such as Low-Density Parity-Check (LDPC) and turbo decoders have an inherent capability to correct the transmission errors that originate during communication over a hostile wireless channel. This capability has engendered the widespread use of LDPC and turbo decoders in current communications standards. As a result, signficant research efforts have been made in order to conceive efficient Very-Large-Scale Integration (VLSI) implementations of both LDPC and turbo decoders. Typically, these efforts have focused on optimizing only one of the various trade-offs associated with the hardware implementation of iterative decoders, such as the chip area, latency, throughput, energy efficiency or Bit Error Ratio (BER) performance. However, tolerance to timing errors that occur during the iterative decoding processing are typically not considered in these implementations. Owing to this, the BER performance and hardware efficiency of the proposed designs may be severely degraded, if timing errors occur during the iterative decoding process. Against this background, this thesis demonstrates that iterative decoders are capable of exploiting their inherent error correction capability to correct not only transmission errors, but also timing errors caused by overclocking and power supply variations. Moreover,we propose modifications to the iterative decoders designs, which further enhance their inherent tolerance to timing errors. We achieve this by considering the close relationship between the different trade-offs associated with the hardware implementation of iterative decoders, with the aim of achieving Pareto optimality, where none of these trade-offs can be further improved without degrading at least one of the others. Owing to this, our proposed timing-error-tolerant design methodology simultaneously considers the design constraints and parameters that affect not only the BER performance, but also the hardware efficiency of each implementation. We first investigate the benefits of stochastic computing in iterative decoders, by characterizing the inherent timing-error tolerance of Stochastic LDPC Decoders (SLDPCDs) and Stochastic Turbo Decoders (STDs). Moreover, we propose modifications to the SLDPCD and STD in order to further improve their inherent tolerance to timing errors. This is achieved by performing extensive transistor-level and post-layout simulations, in order to develop different timing analyses for determining the causes and effects of timing errors in these stochastic decoders. Following this, we propose a novel Reduced-Latency STD (RLSTD), which improves the latency of the state-of-the-art STD by an order of magnitude, without increasing its chip area or energy consumption. Our experimental results demonstrate that our proposed RLSTD achieves ultra-low-latencies required by next-generation Mission-Critical Machine-Type Communication (MCMTC). We also investigate the inherent tolerance to timing errors of a recently-proposed Fully-Parallel Turbo Decoder (FPTD). Furthermore, we propose a novel Reduced-Critical-Path Fully-Parallel Turbo Decoder (RCP-FPTD) algorithm and the employment of Better-Than-Worst-Case (BTWC) design techniques in FPTD and RCP-FPTD implementations, for the sake of improving their throughput and their tolerance to timing errors caused by overclocking. We demonstrate that the FPTD and RCP-FPTD implementations improve the throughput of the state-of-the-art turbo decoder by an order of magnitude. Finally, despite operating in the presence of timing errors, our proposed Better-Than-Worst-Case Reduced-Critical-Path Fully-Parallel Turbo Decoder (BTWC-RCP-FPTD) achieves throughputs on the order of tens of Gbps, which may be expected to be a requirement in next-generation wireless communication standards.
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Bage, Jayaraj Nagendra. "Minimum Symbol Error Rate Timing Recovery System." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/684.
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This thesis presents a timing error detector (TED) used in the symbol timing synchronization subsystem for digital communications. The new timing error detector is designed to minimize the probability of symbol decision error, and it is called minimum symbol error rate TED (MSERTED). The new TED resembles the TED derived using the maximum likelihood (ML) criterion but gives rise to faster convergence relative to MLTED. The new TED requires shorter training sequences for symbol timing recovery. The TED operates on the outputs of the matched filter and estimates the timing offset. The S-curve is used as a tool for analyzing the behavior of the TEDs. The faster convergence of the new TED is shown in simulation results as compared to MLTED. The new TED works well for any two-dimensional constellation with arbitrarily shaped decision regions.
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Gatama, Gachira Peter. "Anticipation timing error as a function of mood lability." Thesis, McGill University, 1993. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=56955.
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The purpose of this study was to examine the effect of mood lability on anticipation timing performance. The influence of gender and stimulus speed on timing error was also analysed. Spectral analysis was used to quantify frequency of mood change. The within-subjects standard deviation was calculated as a measure of intensity of mood change. Thirty-eight physical education students (18 men; M = 23.8 yrs, SD = 2.1 and 20 women; M = 20.4 yrs, SD = 1.6) participated in this study. Mood changes were measured along the Pleasantness and Energetic dimensions of the Affect Grid. Performance was assessed using the Bassin Anticipation Timer. It was hypothesized that: the fast mood changers would incur greater timing errors than the slow mood changers, men would perform with less error than women, and stimulus speed would have a significant influence on timing error.Mixed factorial ANOVAs with repeated measures on the last factor were utilized to compare mean timing error scores: constant error, absolute error, variable error, and total error, over two levels of frequency of mood change (fast/slow) and intensity of mood change (high/low) groups, two levels of gender (men/women) and four levels of stimulus speed (5/10/15/25 mph). Alpha was set at the.05 significance level for all statistical comparisons. Results showed that intensity of mood change had a significant influence on anticipation timing performance, frequency of mood change factor did not have a significant effect on timing error, men performed with less variability than women and stimulus speed had a significant influence on anticipation timing. The Profile of Mood States (POMS) results, showed that women scored lower on the negative mood states than men. Total mood disturbance for both men and women showed no significant relationship to the timing error scores.
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Zuo, Xin. "Fully parallel implementation of timing-error-tolerant LDPC decoders." Thesis, University of Southampton, 2016. https://eprints.soton.ac.uk/400192/.
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In this thesis, the design of fully parallel timing-error-tolerant Low-Density Parity-Check (LDPC) decoders have been investigated. LDPC decoders are employed in numerous communication systems to correct channel-induced transmission errors. The ever increasing data traffic demands require LDPC decoders that are capable of providing high processing throughput and low processing latency, using limited hardware resources and energy consumption. The fully parallel implementation of LDPC decoders is suitable, due to the high throughput and low latency that this affords. However, the task of designing reliable Very Large-Scale Integration (VLSI) systems is becoming increasingly challenging in successive generations of nanoscale fabrication technology. This may be attributed to the occurrence of timing errors, during the processing, which is caused by the increasing susceptibility to IR drop, inductive noise, crosstalk, electrostatic discharges, particle strikes, switching noise and fabrication process variations. Therefore it is necessary to consider the effects of timing errors during the design of LDPC decoders. However, the characterization of the timing error tolerance of LDPC decoders relying on measurements obtained directly from a fabricated Application-Specific Integrated Circuit (ASIC) may not be preferable, owing to the associated risk of wasting all of the invested time, effort and expense, if the ASIC is not able to facilitate the desired outcomes. A novel design flow is therefore proposed in this thesis, which allows the use of simulations at the algorithm level to investigate the decoders' error correction performance, with considerations of the occurrence of timing errors in the hardware architecture level of the design. LDPC decoders employing the optimal Sum-Product Algorithm (SPA) have a very high implementation complexity, which requires the exchange of floating point probabilities between the parity-Check Nodes (CNs) and Variable Nodes (VNs) in their factor graph representation. In order to reduce the complexity, the Log-Sum-Product Algorithm(Log-SPA) and the Min-Sum Algorithm (MSA) may be employed in the LDPC decoder, which operate on a basis of Log-Likelihood Ratios (LLRs), rather than probabilities. These LLRs can be represented by Fixed-Point (FP) numbers, comprising a number of bits, referred to as the bit width. It is this bit width that proportionally determines both the size of the memory required, as well as the area of the data path and hence the energy consumption imposed. We propose the use of EXtrinsic Information Transfer (EXIT) charts to select the bit widths for the Fixed-point LDPC Decoders (LDPC-FDs), in order to achieve a desirable trade-off between the implementation complexity and the error correction performance. This significantly expedites the LDPC-FD design process, relative to the conventional approach of using trial and error based Bit Error Ratio (BER) simulations. Using the proposed design flow, timing characteristics analysis may be performed on the LDPC-FD, in order to derive an error model of the causes and effects of timing errors. With the aid of the error model, the error correction performance of the LDPC-FD in the presence of timing errors may be characterized. In this way, the parametrization of the LDPC-FD may be optimized. In Stochastic LDPC Decoders (LDPC-SDs), only a single bit is exchanged between each pair of CNs and VNs in each clock cycle. Over the course of several successive clock cycles, the individual bits that are exchanged between a particular pair of nodes collectively form a Bernoulli sequence, which may replace the LLRs conventionally used in LDPC-FDs. Owing to this, the operations of the CNs and VNs may be implemented using simple logic gates, which grants LDPC-SDs the practical opportunity for fully parallel implementation. As in LDPC-FDs, the proposed design flow may be adopted to guide the investigation of the timing error tolerance of LDPC-SDs, in order to determine their optimal parametrization.
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Barceló, Adrover Salvador. "An advanced Framework for efficient IC optimization based on analytical models engine." Doctoral thesis, Universitat de les Illes Balears, 2013. http://hdl.handle.net/10803/128968.
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En base als reptes sorgits a conseqüència de l'escalat de la tecnologia, la present tesis desenvolupa i analitza un conjunt d'eines orientades a avaluar la sensibilitat a la propagació d'esdeveniments SET en circuits microelectrònics. S'han proposant varies mètriques de propagació de SETs considerant l'impacto dels emmascaraments lògic, elèctric i combinat lògic-elèctric. Aquestes mètriques proporcionen una via d'anàlisi per quantificar tant les regions més susceptibles a propagar SETs com les sortides més susceptibles de rebre'ls. S'ha desenvolupat un conjunt d'algorismes de cerca de camins sensibilitzables altament adaptables a múltiples aplicacions, un sistema lògic especific i diverses tècniques de simplificació de circuits. S'ha demostrat que el retard d'un camí donat depèn dels vectors de sensibilització aplicats a les portes que formen part del mateix, essent aquesta variació de retard comparable a la atribuïble a les variacions paramètriques del proces.En base a los desafíos surgidos a consecuencia del escalado de la tecnología, la presente tesis desarrolla y analiza un conjunto de herramientas orientadas a evaluar la sensibilidad a la propagación de eventos SET en circuitos microelectrónicos. Se han propuesto varias métricas de propagación de SETs considerando el impacto de los enmascaramientos lógico, eléctrico y combinado lógico-eléctrico. Estas métricas proporcionan una vía de análisis para cuantificar tanto las regiones más susceptibles a propagar eventos SET como las salidas más susceptibles a recibirlos. Ha sido desarrollado un conjunto de algoritmos de búsqueda de caminos sensibilizables altamente adaptables a múltiples aplicaciones, un sistema lógico especifico y diversas técnicas de simplificación de circuitos. Se ha demostrado que el retardo de un camino dado depende de los vectores de sensibilización aplicados a las puertas que forman parte del mismo, siendo esta variación de retardo comparable a la atribuible a las variaciones paramétricas del proceso.
Based on the challenges arising as a result of technology scaling, this thesis develops and evaluates a complete framework for SET propagation sensitivity. The framework comprises a number of processing tools capable of handling circuits with high complexity in an efficient way. Various SET propagation metrics have been proposed considering the impact of logic, electric and combined logic-electric masking. Such metrics provide a valuable vehicle to grade either in-circuit regions being more susceptible of propagating SETs toward the circuit outputs or circuit outputs more susceptible to produce SET. A quite efficient and customizable true path finding algorithm with a specific logic system has been constructed and its efficacy demonstrated on large benchmark circuits. It has been shown that the delay of a path depends on the sensitization vectors applied to the gates within the path. In some cases, this variation is comparable to the one caused by process parameters variations.
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Bal, Aatreyi. "Revamping Timing Error Resilience to Tackle Choke Points at NTC." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7456.
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The growing market of portable devices and smart wearables has contributed to innovation and development of systems with longer battery-life. While Near Threshold Computing (NTC) systems address the need for longer battery-life, they have certain limitations. NTC systems are prone to be significantly affected by variations in the fabrication process, commonly called process variation (PV). This dissertation explores an intriguing effect of PV, called choke points. Choke points are especially important due to their multifarious influence on the functional correctness of an NTC system. This work shows why novel research is required in this direction and proposes two techniques to resolve the problems created by choke points, while maintaining the reduced power needs.
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Bijsterbosch, Janine. "Behavioural and neural correlates of sensorimotor timing and error correction." Thesis, University of Sheffield, 2011. http://etheses.whiterose.ac.uk/2008/.
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Timing is essential for human movement and cognition and is affected in many psychiatric and neurological disorders. The aim of this thesis was to determine the behavioural and neural correlates of sensorimotor timing and of temporal error correction. Motor timing can be studied using a sensorimotor synchronization (SMS) task. In SMS, timing accuracy is assessed during synchronized finger tapping with a regular pacing stimulus and error correction performance is measured based on responses following induced local timing shifts. Study one addressed the effects of task-related and subject-specific factors on SMS performance and showed that tapping variability was reduced during bimanual SMS, compared with unimanual SMS. Study two examined the role of the primary and pre-motor cortices in SMS using theta burst transcranial magnetic stimulation (TBS). The findings suggested that the left-lateralized pre-motor cortex may play a role in temporal error correction. This hypothesis was tested in study three which confirmed that suppression TBS over the left pre-motor significantly affected error correction responses following supraliminal timing shifts. Study four used functional magnetic resonance imaging (fMRI) to determine the neural correlates of timing and error correction. It was shown that connectivity emerges in a cortico- cerebellar network including the left-lateralized cerebellum and frontal regions during the correction of supraliminal timing shifts. Study five further examined the role of functional connectivity using fMRI and revealed that interhemispheric connectivity between the primary motor cortices was significantly greater during bimanual SMS, compared with unimanual SMS. Lastly, studies six and seven addressed the efficacy of TBS and showed that the local distribution of subarachnoid cerebrospinal fluid can significantly alter TBS-induced stimulation. In the general discussion it is suggested that sensorimotor timing and error correction may be achieved using internal feedforward models in the cerebellum that inform movement initiation controlled by the left pre-motor cortex.
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Veerabasavaiah, Hanumantharaju T. "Timing error noise reduction in distributed wireless network using Kalman filter." Thesis, Wichita State University, 2013. http://hdl.handle.net/10057/7048.
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The distributed network has been considered the future's wireless networking. A key challenge to implementing a distributed network is time synchronization of nodes in a network in
a noisy environment. A few parallel synchronization schemes have been proposed. But when the data rate is high, the performances of these algorithms are degraded because of timing error noise. Thus thesis deals with the problem of timing error noise using the Kalman filter, which is highly effective for additive white Gaussian noise (AWGN) but also restrains other kinds of
noise, although not as effectively as for AWGN. By means of the Kalman filter, the effect of timing error noise can be reduced. Simulation results provide the effectiveness of the algorithm
used.Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical Engineering and Computer Science.
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Koppel, Piret. "Effects of self-efficacy on attention and error in coincidence timing." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=59517.
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The purpose of this study was to examine the influence of self-efficacy on attentional deployment in a coincidence timing (CT) task.Hypotheses stating that high self-efficacy would incur less performance error than low self-efficacy and that increasing task difficulty, or stimulus speed, would increase CT error as a result of decreased reserve attentional capacity were tested. MANOVA procedures were used to compare CT error scores over three experimental conditions, two levels of task condition (single/dual) and two speeds (15/25 mph). Alpha was set at the.10 probability level for all statistical comparisons.
As predicted, the positive feedback group reported significantly higher levels of self-efficacy than did the control and negative feedback groups, who were statistically similar in self-efficacy. Less variable, absolute, and total error was incurred by positive feedback than by the negative and no feedback treatments. A significant difference between the negative and no feedback groups was also noted in reserve attentional capacity.
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Whatmough, P. N. "Timing-error tolerance techniques for low-power DSP : filters and transforms." Thesis, University College London (University of London), 2012. http://discovery.ucl.ac.uk/1370582/.
Full textAbstract:
Low-power Digital Signal Processing (DSP) circuits are critical to commercial System-on-Chip design for battery powered devices. Dynamic Voltage Scaling (DVS) of digital circuits can reclaim worst-case supply voltage margins for delay variation, reducing power consumption. However, removing static margins without compromising robustness is tremendously challenging, especially in an era of escalating reliability concerns due to continued process scaling. The Razor DVS scheme addresses these concerns, by ensuring robustness using explicit timing-error detection and correction circuits. Nonetheless, the design of low-complexity and low-power error correction is often challenging. In this thesis, the Razor framework is applied to fixed-precision DSP filters and transforms. The inherent error tolerance of many DSP algorithms is exploited to achieve very low-overhead error correction. Novel error correction schemes for DSP datapaths are proposed, with very low-overhead circuit realisations. Two new approximate error correction approaches are proposed. The first is based on an adapted sum-of-products form that prevents errors in intermediate results reaching the output, while the second approach forces errors to occur only in less significant bits of each result by shaping the critical path distribution. A third approach is described that achieves exact error correction using time borrowing techniques on critical paths. Unlike previously published approaches, all three proposed are suitable for high clock frequency implementations, as demonstrated with fully placed and routed FIR, FFT and DCT implementations in 90nm and 32nm CMOS. Design issues and theoretical modelling are presented for each approach, along with SPICE simulation results demonstrating power savings of 21 – 29%. Finally, the design of a baseband transmitter in 32nm CMOS for the Spectrally Efficient FDM (SEFDM) system is presented. SEFDM systems offer bandwidth savings compared to Orthogonal FDM (OFDM), at the cost of increased complexity and power consumption, which is quantified with the first VLSI architecture.
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McMichael, Joseph Gary. "Timing offset and quantization error trade-off in interleaved multi-channel measurements." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66035.
Full textAbstract:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 117-118).
Time-interleaved analog-to-digital converters (ADCs) are traditionally designed with equal quantization granularity in each channel and uniform sampling offsets. Recent work suggests that it is often possible to achieve a better signal-to-quantization noise ratio (SQNR) with different quantization granularity in each channel, non-uniform sampling, and appropriate reconstruction filtering. This thesis develops a framework for optimal design of non-uniform sampling constellations to maximize SQNR in time-interleaved ADCs. The first portion of this thesis investigates discrepancies between the additive noise model and uniform quantizers. A simulation is implemented for the multi-channel measurement and reconstruction system. The simulation reveals a key inconsistency in the environment of time-interleaved ADCs: cross-channel quantization error correlation. Statistical analysis is presented to characterize error correlation between quantizers with different granularities. A novel ADC architecture is developed based on weighted least squares (WLS) to exploit this correlation, with particular application for time-interleaved ADCs. A "correlated noise model" is proposed that incorporates error correlation between channels. The proposed model is shown to perform significantly better than the traditional additive noise model for channels in close proximity. The second portion of this thesis focuses on optimizing channel configurations in time-interleaved ADCs. Analytical and numerical optimization techniques are presented that rely on the additive noise model for determining non-uniform sampling constellations that maximize SQNR. Optimal constellations for critically sampled systems are always uniform, while solution sets for oversampled systems are larger. Systems with diverse bit allocations often exhibit "clusters" of low-precision channels in close proximity. Genetic optimization is shown to be effective for quickly and accurately determining optimal timing constellations in systems with many channels. Finally, a framework for efficient design of optimal channel configurations is formulated that incorporates statistical analysis of cross-channel quantization error correlation and solutions based on the additive noise model. For homogeneous bit allocations, the framework proposes timing offset corrections to avoid performance degradation from the optimal scenario predicted by the additive noise model. For diverse bit allocations, the framework proposes timing corrections and a "unification" of low-precision quantizers in close proximity. This technique results in significant improvements in performance above the previously known optimal additive noise model solution.
by Joseph Gary McMichael.
S.M.
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Mariano, Daniel Teodoro Gonçalves. "Configurações para métodos de acesso por escaneamento." Universidade Federal de Uberlândia, 2016. https://repositorio.ufu.br/handle/123456789/17612.
Full textAbstract:
O emprego de tecnologias de acesso a comunicação, baseados em métodos de acesso
por escaneamento, viabiliza novas oportunidades de comunicação para indivíduos
com disfunção motora severa. Um dos exemplos mais comuns desse tipo de tecnologia
é o teclado virtual operado por varredura. Teclados virtuais são frequentemente
utilizados como dispositivos de comunicação aumentativa e alternativa por indivíduos
com restrições motoras graves e que apresentam comprometimento da fala e da escrita.
São compostos por uma matriz de teclas e simulam a operação de um teclado
físico para a composição de mensagens. Uma das limitações desses sistemas é o
baixo desempenho que possuem. Taxas de comunicação lentas e a considerável
ocorrência de erros são alguns dos problemas que usuários desses dispositivos sofrem
durante o uso diário. O desenvolvimento e a avaliação de novas estratégias em
comunicação aumentativa e alternativa são essenciais para a melhoria das oportunidades
de comunicação dos usuários que fazem uso desse tipo de tecnologia. Neste
sentido, este trabalho explora diferentes estratégias para aumentar essa taxa de comunicação
e reduzir os erros cometidos por seus usuários. Análises computacionais
e práticas foram executadas para a avaliação das estratégias propostas.The use of access technologies for communication, based on scanning methods, enables new communication opportunities for individuals with severe motor dysfunction. One of the most commom examples of this type of technology is the single switch scanning. Single switch scanning keyboards are often used as augmentative and alternative communication devices for inidividuals with severe mobility restrictions and with compromised speech and writing. They consist of a matrix of keys and simulate the operation of a physical keyboard to write messages. One of the limitations of these systems is their low performance. Low communication rates and considerable errors ocurrence are some of the few problems that users of these devices suffers during daily use. The development and evaluation of new strategies in augmentative and alternative communication are essential to improve the communication opportunities of user who make use of such technology. Thus, this work explores different strategies to increase communication rate and reduce user’s mistakes. Computational and practical analysis were performed for the evaluation of proposed strategies.
Dissertação (Mestrado)
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Kippenberger, Roger Miles. "On Real Time Digital Phase Locked Loop Implementation with Application to Timing Recovery." Thesis, University of Canterbury. Electrical and Computer Engineering, 2006. http://hdl.handle.net/10092/1146.
Full textAbstract:
In digital communication systems symbol timing recovery is of fundamental importance. The accuracy in estimation of symbol timing has a direct effect on received data error rates. The primary objective of this thesis is to implement a practical Digital Phase Locked Loop capable of accurate synchronisation of symbols suffering channel corruption typical of modern mobile communications. This thesis describes an all-software implementation of a Digital Phase Locked in a real-time system. A timing error detection (TED) algorithms optimally implemented into a Digital Signal Processor. A real-time transmitter and receiver system is implemented in order to measure performance when the received signal is corrupted by both Additive White Gaussian Noise and Flat Fading. The Timing Error Detection algorithm implemented is a discrete time maximum likelihood one known as FFML1, developed at Canterbury University. FFML1 along with other components of the Digital Phase Locked loop are implemented entirely in software, using Motorola 56321 assembly language.
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Saito, Masato, Hiraku Okada, Takeshi Sato, Takaya Yamazato, Masaaki Katayama, and Akira Ogawa. "Throughput Improvement of CDMA Slotted ALOHA Systems." IEICE, 1997. http://hdl.handle.net/2237/7204.
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Barakat, Bilal. ""Sorry I forgot your birthday!": Adjusting apparent school participation for survey timing when age is measured in whole years." Elsevier, 2016. http://dx.doi.org/10.1016/j.ijedudev.2016.03.011.
Full textAbstract:
When only whole years of age are recorded in survey data, children who experienced a birthday since the beginning of the school year may appear to be of school-age when they are not, or vice-versa. This creates an error in estimates of school participation indicators based on such data. This issue is well-known in education statistics, and several procedures attempting to correct for this error have been proposed. The present study critiques current practice and demonstrates that its limitations continue to confound educational research and high-stakes policy conclusions: speculative explanations have been proposed for what is actually a measurement artefact. An alternative adjustment strategy is proposed that coherently exploits all available information and explicitly indicates the remaining uncertainty. The application of the method is illustrated by a number of empirical case studies using recent household survey data. These examples demonstrate that the method is feasible, accurate, and that taking survey timing into account can significantly alter how these data are interpreted.
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Alfredsson, Jon. "Design of a parallel A/D converter system on PCB : For high-speed sampling and timing error correction." Thesis, Linköping University, Department of Electrical Engineering, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1201.
Full textAbstract:
The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically.
In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors.
This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.
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Mason, Terry. "ADVANCES IN WIDEBAND VHS CASSETTE RECORDING." International Foundation for Telemetering, 1992. http://hdl.handle.net/10150/608887.
Full textAbstract:
International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, CaliforniaIn recent years, many designers have turned to digital techniques as a means of improving the fidelity of instrumentation data recorders. However, single and multi-channel recorders based on professional VHS transports are now available which use innovative methods for achieving near-perfect timebase accuracy, inter-channel timing and group delay specifications for long-duration wideband analog recording applications. This paper discusses some of the interesting technical problems involved and demonstrates that VHS cassette recorders are now a convenient and low cost proposition for high precision multi-channel wideband data recording.
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Bouchard, Amy. "Effect of haptic guidance and error amplification robotic training interventions on the immediate improvement of timing among individuals that had a stroke." Mémoire, Université de Sherbrooke, 2016. http://hdl.handle.net/11143/9543.
Full textAbstract:
Abstract : Many individuals that had a stroke have motor impairments such as timing deficits that hinder their ability to complete daily activities like getting dressed. Robotic rehabilitation is an increasingly popular therapeutic avenue in order to improve motor recovery among this population. Yet, most studies have focused on improving the spatial aspect of movement (e.g. reaching), and not the temporal one (e.g. timing). Hence, the main aim of this study was to compare two types of robotic rehabilitation on the immediate improvement of timing accuracy: haptic guidance (HG), which consists of guiding the person to make the correct movement, and thus decreasing his or her movement errors, and error amplification (EA), which consists of increasing the person’s movement errors. The secondary objective consisted of exploring whether the side of the stroke lesion had an effect on timing accuracy following HG and EA training. Thirty-four persons that had a stroke (average age 67 ± 7 years) participated in a single training session of a timing-based task (simulated pinball-like task), where they had to activate a robot at the correct moment to successfully hit targets that were presented a random on a computer screen. Participants were randomly divided into two groups, receiving either HG or EA. During the same session, a baseline phase and a retention phase were given before and after each training, and these phases were compared in order to evaluate and compare the immediate impact of HG and EA on movement timing accuracy. The results showed that HG helped improve the immediate timing accuracy (p=0.03), but not EA (p=0.45). After comparing both trainings, HG was revealed to be superior to EA at improving timing (p=0.04). Furthermore, a significant correlation was found between the side of stroke lesion and the change in timing accuracy following EA (r[subscript pb]=0.7, p=0.001), but not HG (r[subscript pb]=0.18, p=0.24). In other words, a deterioration in timing accuracy was found for participants with a lesion in the left hemisphere that had trained with EA. On the other hand, for the participants having a right-sided stroke lesion, an improvement in timing accuracy was noted following EA. In sum, it seems that HG helps improve the immediate timing accuracy for individuals that had a stroke. Still, the side of the stroke lesion seems to play a part in the participants’ response to training. This remains to be further explored, in addition to the impact of providing more training sessions in order to assess any long-term benefits of HG or EA.Résumé : À la suite d’un accident vasculaire cérébral (AVC), plusieurs atteintes, comme un déficit de timing, sont notées, et ce, même à la phase chronique d’un AVC, ce qui nuit à l’accomplissement de tâches quotidiennes comme se vêtir. L’entrainement robotisé est un entrainement qui est de plus en plus préconisé dans le but d’améliorer la récupération motrice à la suite d’un AVC. Par contre, la plupart des études ont étudié les effets de l’entrainement robotisé sur l’amélioration de l’aspect spatial du mouvement (ex : la direction du mouvement), et non l’aspect temporel (ex : timing). L’objectif principal de ce projet était donc d’évaluer et de comparer l’impact de deux entrainements robotisés sur l’amélioration immédiate du timing soit : la réduction de l’erreur (RE), qui consiste à guider la personne à faire le mouvement désiré, et l’augmentation de l’erreur (AE), qui nuit au mouvement de la personne. L’objectif secondaire consistait à explorer s’il y avait une relation entre le côté de la lésion cérébrale et le changement dans les erreurs de timing suivant l’entrainement par RE et AE. Trente-quatre personnes atteintes d’un AVC au stade chronique (âge moyen de 67 ± 7 années) ont participé à cette étude, où ils devaient jouer à un jeu simulé de machine à boules. Les participants devaient activer une main robotisée au bon moment pour atteindre des cibles présentées aléatoirement sur un écran d’ordinateur. Les participants recevaient soit RE ou AE. Une ligne de base et une phase de rétention étaient données avant et après chaque entrainement, et elles étaient utilisées pour évaluer et comparer l’effet immédiat de RE et AE sur le timing. Les résultats ont démontré que RE permet d’améliorer les erreurs de timing (p=0,03), mais pas AE (p=0,45). De plus, la comparaison entre les deux entrainements a démontré que RE était supérieur à AE pour améliorer le timing (p=0,04). Par ailleurs, une corrélation significative a été notée entre le côté de la lésion cérébrale et le changement des erreurs de timing suivant AE (r[indice inférieur pb]=0,70; p=0,001), mais pas RE (r[indice inférieur pb]=0,18; p=0,24). En d’autres mots, une détérioration de l’exécution de la tâche de timing a été notée pour les participants ayant leur lésion cérébrale à gauche. Par contre, ceux ayant leur lésion à droite ont bénéficié de l’entrainement par AE. Bref, l’entrainement par RE peut améliorer les erreurs de timing pour les survivants d’AVC au stade chronique. Toutefois, le côté de la lésion cérébrale semble jouer un rôle important dans la réponse à l’entrainement par AE. Ceci demeure à être exploré, ainsi que l’impact d’un entrainement par RE et AE de plus longue durée pour en déterminer leurs effets à long terme.
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Saito, Masato, Takaya Yamazato, Masaaki Katayama, and Akira Ogawa. "New Quasi-Synchronous Sequences for CDMA Slotted ALOHA Systems." IEICE, 1998. http://hdl.handle.net/2237/7207.
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Mladen, Kovačević. "Error-Correcting Codes in Spaces of Sets and Multisets and Their Applications in Permutation Channels." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2014. https://www.cris.uns.ac.rs/record.jsf?recordId=85935&source=NDLTD&language=en.
Full textAbstract:
The thesis studies two communicationchannels and corresponding error-correctingcodes. Multiset codes are introduced andtheir applications described. Properties ofentropy and relative entropy are investigated.U tezi su analizirana dva tipa komunikacionihkanala i odgovarajući zaštitni kodovi.Uveden je pojam multiskupovnog koda iopisane njegove primene. Proučavane suosobine entropije i relativne entropije.
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Rathnala, Prasanthi. "Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation." Thesis, University of Derby, 2017. http://hdl.handle.net/10545/621716.
Full textAbstract:
Growing usage of smart and portable electronic devices demands embedded system designers to provide solutions with better performance and reduced power consumption. Due to the new development of IoT and embedded systems usage, not only power and performance of these devices but also security of them is becoming an important design constraint. In this work, a novel aggressive scaling based on timing speculation is proposed to overcome the drawbacks of traditional DVFS and provide security from power analysis attacks at the same time. Dynamic voltage and frequency scaling (DVFS) is proven to be the most suitable technique for power efficiency in processor designs. Due to its promising benefits, the technique is still getting researchers attention to trade off power and performance of modern processor designs. The issues of traditional DVFS are: 1) Due to its pre-calculated operating points, the system is not able to suit to modern process variations. 2) Since Process Voltage and Temperature (PVT) variations are not considered, large timing margins are added to guarantee a safe operation in the presence of variations. The research work presented here addresses these issues by employing aggressive scaling mechanisms to achieve more power savings with increased performance. This approach uses in-situ timing error monitoring and recovering mechanisms to reduce extra timing margins and to account for process variations. A novel timing error detection and correction mechanism, to achieve more power savings or high performance, is presented. This novel technique has also been shown to improve security of processors against differential power analysis attacks technique. Differential power analysis attacks can extract secret information from embedded systems without knowing much details about the internal architecture of the device. Simulated and experimental data show that the novel technique can provide a performance improvement of 24% or power savings of 44% while occupying less area and power overhead. Overall, the proposed aggressive scaling technique provides an improvement in power consumption and performance while increasing the security of processors from power analysis attacks.
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Asturiol, Bofill David. "Basis set superposition error effects, excited-state potential energy surface and photodynamics of thymine." Doctoral thesis, Universitat de Girona, 2010. http://hdl.handle.net/10803/7943.
Full textAbstract:
En aquesta tesi he estudiat l'efecte de l'error de superposició de base (BSSE) en la planaritat d'algunes molècules. He observat que l'ús d'alguns mètodes de càlcul amb determinades funcions de base descriuen mínims d'energia no planars per les bases nitrogenades de l'ADN. He demostrat que aquests problemes es poden arreglar utilitzant el mètode Counterpoise per corregir el BSSE en els càlculs. En aquesta tesi també he estudiat la fotofísica de la timina i els resultats mostren que existeixen dos camins de relaxació des de l'estat excitat que permeten la regeneració de l'estructura inicial de forma ultraràpida.The effect of the basis set superposition error (BSSE) on the planarity of some molecules has been studied in this thesis. I have observed that the use of some correlated methods with certain basis sets lead to non-planar minima structures of nucleobases. I have shown that the use of the Counterpoise method fixes these pitfalls in all cases. I have also studied the photophysics of thymine in this thesis and my results show that there exist two decay paths that can regenerate the initial structure of thymine in less than tenths of picoseconds upon photon absorption.
31
Du, Jimmy. "Kompenseringsalgoritm för löptidsmätande laseravståndsmätare baserad på Time to Digital Converter." Thesis, Karlstads universitet, Fakulteten för hälsa, natur- och teknikvetenskap (from 2013), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-73275.
Full textAbstract:
This bachelor thesis has been collaborated with Saab Dynamics AB in Karlskoga. The purpose is to analyze time-based rangefinder based on Time-to-Digital Converter with short laser pulses. Compensation will be produced for timing walk-error that is introduced by a dynamic problem. The temperatures influence on the distance measurement will be verified. After collecting data from measurements, compensation is produced. With help from the compensation the measurements are working on different targets.
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Rabizadeh, Ehsan [Verfasser], and Timon [Akademischer Betreuer] Rabczuk. "Goal-oriented A Posteriori Error Estimation and Adaptive Mesh Refinement in 2D/3D Thermoelasticity Problems / Ehsan Rabizadeh ; Betreuer: Timon Rabczuk." Weimar : Bauhaus-Universität Weimar, 2020. http://d-nb.info/1221528041/34.
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Grobler, Johannes Petrus. "Design and implementation of a high resolution soft real-time timer." Diss., Pretoria : [s.n.], 2006. http://upetd.up.ac.za/thesis/available/etd-08282007-095022.
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Funk, James Cyril. "Rate-Adaptive Runlength Limited Encoding for High-Speed Infrared Communication." BYU ScholarsArchive, 2005. https://scholarsarchive.byu.edu/etd/780.
Full textAbstract:
My thesis will demonstrate that Rate Adaptive Runlength Limited encoding (RA-RLL) achieves high data rates with acceptable error rate over a wide range of signal distortion/attenuation, and background noise. RA-RLL has performance superior to other infrared modulation schemes in terms of bandwidth efficiency, duty cycle control, and synchronization frequency. Rate adaptive techniques allow for quick convergence of RA-RLL parameters to acceptable values. RA-RLL may be feasibly implemented on systems with non-ideal timing and digital synchronization.
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Kilic, Ergin. "Structured Neural Networks For Modeling And Identification Of Nonlinear Mechanical Systems." Phd thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614735/index.pdf.
Full textAbstract:
Most engineering systems are highly nonlinear in nature and thus one could not
develop efficient mathematical models for these systems. Artificial neural
networks, which are used in estimation, filtering, identification and control in
technical literature, are considered as universal modeling and functional
approximation tools. Unfortunately, developing a well trained monolithic type
neural network (with many free parameters/weights) is known to be a daunting
task since the process of loading a specific pattern (functional relationship) onto a
generic neural network is proven to be a NP-complete problem. It implies that if
training is conducted on a deterministic computer, the time required for training
process grows exponentially with increasing size of the free parameter space (and
the training data in correlation). As an alternative modeling technique for
nonlinear dynamic systemsthis thesis proposed a general methodology for structured neural network topologies and their corresponding applications are realized. The main idea behind this (rather classic) divide-and-conquer approach is to employ a priori information on the process to divide the problem into its fundamental components. Hence, a number of smaller neural networks could be designed to tackle with these elementary mapping problems. Then, all these networks are combined to yield a tailored structured neural network for the purpose of modeling the dynamic system under study accurately. Finally, implementations of the devised networks are taken into consideration and the efficiency of the proposed methodology is tested on four different types of mechanical systems.
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Naab-Levy, Adam O. "Enhanced Distance Measuring Equipment Data Broadcast Design, Analysis, Implementation, and Flight-Test Validation." Ohio University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1449158180.
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Lee, Suk Ho. "Jamming effects on digital communications receivers (timing errors and frequency errors)." Thesis, 1985. http://hdl.handle.net/10945/37407.
Full textAbstract:
A refinement of the results obtained for optimum energy constrained jamming of digital receivers is obtained by modeling the jammer as a random process. In the modeling process, a random time arrival or random frequency errors are accounted for by including these effects in the repre- sentation of the jamming waveforms. Performance analyses are carried out in order to determine the effect of random time of arrival and random frequency errors on the part of the jammer, on the receiver probability of error. The mathematical results derived are programmed, evaluated on the computer, and compared against ideal optimum energy constrained jamming strategies previously studied. Results for both coherent and incoherent receivers are derived and analyzed utilizing conventional binary modulation schemes. Results show that generally some but not a great deal of jammer effectiveness is lost due to random time of arrival or random frequency errors associated with the jammer waveform.
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Chen, Chia-Sheng, and 陳家聖. "Design of Systolic Arrays for Tolerating Timing Errors." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/92573152136184293323.
Full textAbstract:
碩士國立東華大學
電子工程研究所
98
With the rapid progress of semiconductor process in recent years, we have been able to put more than hundreds of millions transistors into a single chip. The circuit characteristics in a large-scale chip have therefore changed significantly, while the transistor count and clock frequency of the chip keep increasing. As the transistors size and working voltage are getting smaller and lower, the connection design between IP blocks within the chip has become increasingly complex. On such advanced chip, signal transmission is no longer as stable and reliable as before. Since the signal is more susceptible to wire delay, noise, soft error, and synchronization, these factors affects the occurrence of timing errors. This thesis describes a timing-error-tolerant design of pipeline circuits. In such architecture, the pipeline stage buffer is replaced with a new design circuit to support timing error resilience. The organization of the circuit tolerates the timing errors with the ability to detect and correct such problems in the pipeline. We have applied the technique to systolic arrays. Two systolic architectures for matrix multiplication are designed with our proposed techniques, including linear and hexagonal systolic arrays. We use hardware description language to design and simulate them, and verify the timing error tolerance of the circuits. Furthermore, the circuit synthesis and physical design tools are also employed to realize our design. The results show that in order to achieve timing error resilience, we need to pay a portion for circuit speed and chip area. However, with the data width increasing, such overhead decreases and can be hidden and negligible for designs with high data width.
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Lin, Shao-Hsien, and 林紹賢. "Design of Elastic Pipelines for Tolerating Timing Errors." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/58904495525831106190.
Full textAbstract:
碩士國立東華大學
電子工程研究所
98
With the rapid and sophisticated development of semiconductor manufacturing, designing chips has become increasingly challenging. Chip designers are now faced with much more complicated nanometer-based circuits with not only finer manufacturing process but also higher possibilities of unexpected variations caused by the leakage of current. There are many potential problems to be addressed on this issue, such as crosstalk, delay defects, and the sensitivity of noise. In addition, the stability of temperature and voltage of the circuit also affects the reliability of signals. Factors such as timing errors or soft errors can cause circuit failures. The need to avoid these problems and to enhance the circuit reliability starting from the designing stage is very important. When an error occurs, the speed and accuracy of error detection and data recovery are critical issues on designing reliable circuits. This thesis investigates the timing-error-resilient structure on synchronous digital systems design. The focus is on how to use delays to detect and correct the signal errors. Two possibilities for timing-error-resilient structures will be studied: one is automatic error-free design, and the other is elastic datapath design. Experiments are performed to validate our ideas through logic simulation, synthesis, and physical layout.
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Wang, Yi-Kai, and 王逸凱. "Design of Pipelined VLSI Circuits for Tolerating Timing Errors." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/85736205639217314454.
Full textAbstract:
碩士國立東華大學
電子工程研究所
96
Abstract Owing to the ever advancing of semiconductor technology, the size of transistors and their operating voltage keep decreasing. Hence, the problems of wires and circuits being susceptible to noise, wire delay, and soft errors are getting more and more severe. One of the challenges we are faced with is timing errors. As the clock rate is higher, the probability of timing errors gets higher too. One of the solutions to these problems is error-resilient design. Error-resilient design of VLSI circuits can detect and even correct errors. Such design is more important when the system-on-chip era has become practical for many applications. This thesis proposes a new error resilient design for pipelined VLSI circuits to tolerate timing errors. In our design, a technique is presented to detect and correct the timing errors. Basically, we modify the pipeline buffer by adding appropriate control circuits to adjust to the timing error event. We have validated our idea by applying our technique to two example digital signal processing designs: an FIR filter and an IIR filter. We have simulated the two designs and implemented them with cell-based design flow. The results show that our designs add nearly no delay at a reasonable area cost.
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Gu, Ｍin-Sheng, and 古閔升. "Design of Pipelined Circuits for Tolerating Multiple Timing Errors." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/94632029539263269679.
Full textAbstract:
碩士國立東華大學
電子工程研究所
97
In modern VLSI design, many large systems are realized with system-on-chip technology. As the technology of IC manufacturing advances, the number of transistors and the operating voltage keep decreasing. Hence, circuits are susceptible to noise, wire delay, soft errors, and other factors. Many of the problems are caused by timing errors. When data get into pipeline buffers due to environmental factors or process variation, timing errors may cause the circuit to operate incorrectly. One of solutions to these problems is error-resilient design. Error-resilient design for VLSI circuits can immediately detect and even correct errors. Such design is even more important when the system-on-chip era becomes practical for many applications. This thesis proposes a new error-resilient design of pipelined circuits for tolerating multiple timing errors. We modify the pipeline buffer structure by adding appropriate control circuits to adjust to the timing errors. We have validated our technique by applying it to two example digital signal processing design: an FIR filter and an IIR filter. Finally, we have simulated the designs and implemented them with cell-based IC design flow. The results show that our designs add nearly no delay at a reasonable area cost.
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Lai, Jiun-Nian, and 賴俊年. "A Design Framework of Systolic Arrays for Tolerating Timing Errors." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/2p7hw3.
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碩士國立東華大學
電機工程學系
100
Along with the progress of making semiconductor the technique of manufacturing integrated circuit skill take from 0.35um to 90nm and even smaller. Both power capacity and the mass of transistors reduction is what nowadays processor of semiconductor are after Therefore, electric circuit is more easily get effective by elements like noise, wire delay, and soft error etc. that may produce timing error. So designing a tolerant timing error is crucial. Timing error means when the data enters the calculate unit the collective sampling data has been affected therefore causing errors. Not letting time go to waste and to be insuring the arithmetic results can be correct, this is the reason why we must add the error resilient during the designed circuit. This circuit has the ability to detect out the errors right during the data has its errors, and also be able to correct it at the instance letting the circuit transmit to the next target normally, so that at last we will be able to get an error-free data. This thesis is about: Firstly we use systolic arrays architecture to designed and make a pipeline buffer circuit. Than we replace it with a designed pipeline circuit that has an approved timing error When errors happens, timing errors detects the errors and uses clock period to recover the error data without effecting the ongoing and future function. Putting out the seven types that systolic arrays have given rise we improved the designs letting every model have the capability of timing error toleration. Using verilog, the description language of hardware to test and verifying the tolerant of timing error. We use the synthesis to verify if the time delay grows out to our demand or not than layout to complete the design of cellbased IC. Lastly, we add the time tolerant circuit to the original circuit to analysis.
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Jian, Jia-Wei, and 簡嘉韋. "Design of Reconfigurable Digital Filters for Tolerating Multiple Timing Errors." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/43492701971268492948.
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碩士國立東華大學
電機工程學系
101
As the feature size of chips shrinks with semiconductor technology advancing, the size of transistors and their operating voltage keep decreasing. One of the major problems with advanced semiconductor technology is timing errors caused by process variation and device aging. With such problems, conventional worst-case designs suffer poor system performance. This thesis proposes an aggressive design technique for VLSI digital filters for tolerating multiple timing errors. We have developed a methodology of designing reconfigurable VLSI digital filters that can tolerate multiple timing errors. The reconfigurable digital filters are resilient to any timing errors occurring at any stage and any time. When the timing error occurs, the system reconfigures the buffer cells of digital filters with little performance degradation. We have applied the technique to two example digital filter designs, including an FIR filter and an IIR filter. The implementation results show that our proposed designs achieve tolerance of multiple timing errors with reasonable cost.
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Tsai, Chia chun, and 蔡佳君. "The Effect of Analyst Earnings Forecast Errors and Earnings Announcement Timing on Earnings Management." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/71063836312195116331.
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碩士東海大學
會計學系
93
Abstract Previous literatures defined the information content of earnings announcement by testing their response to the stock price. Most internal empirical results have not found the information content of earnings announcement timing. According to the disparity of earnings announcement timing between the analyst and manager announcement, this study discusses the public companies in Taiwan’s earnings management problem controlled earnings announcement timing. This research try to verify earnings management via discretionary accrual conditioned earnings announcement timing. Empirical results found that late announcement of the good news sample group and the bad news sample group manipulates range more than the others. This research found significant positive correlation exists between the deferred announcement and abnormal accruals. Finally, in the characteristic of late announcement company, this research also found significant positive correlation exists between the days of deferred announcement and debt rate.
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Smith, Jennifer Elizabeth. "Re-tuning Shakespeare: Meter and timing in "The Comedy of Errors" and "A Midsummer Night's Dream."." 2007. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=510500&T=F.
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Quinn, Paul. "Delayed Versus Immediate Corrective Feedback on Orally Produced Passive Errors in English." Thesis, 2014. http://hdl.handle.net/1807/65728.
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Research demonstrating the beneficial effects of corrective feedback (CF) for second language (L2) learning (e,g., Li, 2010) has almost invariably resulted from studies in which CF was provided immediately. Yet teachers are often encouraged to delay CF to avoid interrupting learners (Harmer, 2001). This study investigates how differences in the timing of CF on oral production affect L2 learning and learners’ reactions to CF.
Theoretically, Immediate CF may facilitate L2 development by allowing learners to immediately compare their errors to accurate models (i.e., recasting, e.g., Doughty, 2001). The effectiveness of Immediate CF has also been linked to skill acquisition theory because some CF (i.e., prompting) is hypothesized to help learners proceduralize their L2 knowledge (Ranta & Lyster, 2007). This thesis introduces additional theoretical explanations to explain the effectiveness of both Immediate and Delayed CF. For example, reactivation and reconsolidation theory (Nader & Einarsson, 2010) holds that long-term mental representations are susceptible to change when they are recalled. Thus, both Immediate and Delayed CF may help learners alter their incorrect mental representations of language features if that CF reminds learners of those incorrect representations and provides them with accurate models.
In a laboratory-based study, 90 intermediate-level adult ESL learners were randomly assigned to Immediate, Delayed, and No CF conditions. Learners took three pre-tests to measure their knowledge of the English passive construction: an aural grammaticality judgment test (AGJT), an oral production test (OPT), and a written error correction test (ECT). Next, they received some brief instruction on the passive. Learners then completed three communicative tasks in which the CF conditions were provided. These tasks were followed by immediate and delayed post-tests. Learners’ reactions to CF were elicited with a questionnaire.
Mixed-design one-way ANOVAs revealed statistically significant improvement for all conditions over time on all measures, but no statistically significant differences between conditions. The questionnaires revealed that learners prefer Immediate CF, but that Immediate CF may constrain CF noticeability and learners’ independence, while Delayed CF may cause anxiety or embarrassment. In summary, altering the timing of CF did not differentially affect L2 development, but it did elicit different reactions from learners.
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Wu, Chu-Wen, and 吳主文. "VLSI Design of Timing-Error-Resilient Sorting Hardware." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/frn692.
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碩士國立東華大學
電機工程學系
104
As the feature size of chips shrinks with advance of semiconductor technology, the size of transistors and their operating voltage keep decreasing. One of the major problems with advanced semiconductor technology is timing errors caused by variation of process, supply voltage, temperature (PVT). Furthermore, device aging can also cause timing errors. With such problems, conventional worst-case designs suffer poor system performance. When timing errors happen, the computing result from the integrated circuit is incorrect. Although we can employ worst-case frequency for insuring correctness, the performance is sacrificed significantly. Hence, design of timing-error-resilient VLSI circuit with aggressive design approach is more and more important. This thesis proposes a technique for aggressive VLSI design of timing-error resilient sorting hardware, which has an error detection and fault tolerance function. Even if the circuit timing errors occur, the design can still operate and produce the correct output. Although this design is at the expense of a small amount of chip area cost and power consumption, it can achieve reliability for the circuit, while keeps high performance. We have applied the technique to three sorting algorithms, including Bubble Sort, Odd-Even Sort, and Bitonic Sort. Two versions of the sorting hardware are implemented for the three sorters for comparison: one is original sorting hardware and the other is with timing-error-tolerant capability. The implementation results show that our proposed designs achieve tolerance of timing errors with reasonable cost.
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Peng, Guan-Lin, and 彭冠霖. "VLSI Design of a Timing-Error-Tolerant Microprocessor." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/05087571276420541666.
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碩士國立東華大學
資訊工程學系
104
Due to the ever advancing of semiconductor technology, the size of transistors and their operating voltage keep decreasing. Hence, the problems of wires and circuits being susceptible to noise, wire delay, and soft errors are getting worse and worse. One of the challenges we are faced with is timing errors of the circuits. Timing errors may happen when transmitted data arrive later than the timing clock or simply has not enough setup time. With VLSI circuit in advanced manufacturing process, timing errors either result in reduced operational reliability of circuits, or we have to tolerate the much slower clock pessimistically. One of the solutions to these problems is error-resilient design. Error-resilient design of VLSI circuits can detect and even correct errors. Such design is even more important for advanced microprocessors in modern technology for many applications in recently years. This master thesis employs timing-error-tolerant circuits in our designed 5-stage pipelined microprocessor with a 32-bit reduced MIPS instruction set. We implement our design using the cell-based IC design flow with Verilog hardware description language. We have run extensive simulation to validate the timing-error-tolerant capability. We then use logic synthesis to generate the circuit, and static timing analysis to verify that the timing delay meets our goal. The final step is to do automatic place and route, physical verification. We measure the cost we have to pay for the timing-error-tolerant capability. It is shown that our design can improve test coverage of the microprocessor with a reasonable cost.
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何松庭. "Short path padding for timing error resilient circuits." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/41795110924219377910.
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碩士國立交通大學
電子研究所
101
Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a conservative timing guardband is required to guarantee correct operations under the worst-case variation, thus leading to performance degradation. To remove the guardband, resilient circuits are proposed. However, the short path padding (hold time fixing) problem is severe in resilient circuits. In this thesis, to enable the timing error detection and correction mechanism of resilient circuits, we focus on the short path padding problem. Unlike recent prior work adopts greedy heuristics with a global view, we determine the padding values and locations with a global view. Moreover, we propose coarse-grained and fine-grained padding allocation methods to further achieve the derived padding values at physical implementation.
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Chang, Po-Hsien, and 張柏賢. "Synthesis of a Novel Timing Error Detection Architecture." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/54749626504975597989.
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碩士國立清華大學
資訊工程學系
93
Delay variation can cause a design to fail its timing specification. Research [5, 12] observes that the worst case of a design is highly improbable to occur. They propose a mechanism to detect and correct occasional errors while the design can be optimized for the common cases. Their xperimental results show significant performance or power gain as compared to the worst-case design. However, the architecture in [5, 12] suffers the short path problem which is difficult to resolve in the advanced technology. In this thesis, we propose a Timing Error Detection (TED) architecture without using a delayed clock and therefore the TED architecture is free from the short path problem. Given a design and a maximum delay margin, our algorithm can automatically construct a TED architecture to tolerate the given delay margin. Our experimental results also show that the TED architecture can be a good alternative for those cases where the minimum delay is difficult to meet in the advanced technology.