Dissertations / Theses on the topic 'Transformée de cosinus discrète'
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Eude, Thierry. "Compression d'images médicales pour la transmission et l'archivage, par la transformée en cosinus discrète." Rouen, 1993. http://www.theses.fr/1993ROUES056.
Full textAuclair, Beaudry Jean-Sébastien. "Modelage de contexte simplifié pour la compression basée sur la transformée en cosinus discrète." Mémoire, Université de Sherbrooke, 2009. http://savoirs.usherbrooke.ca/handle/11143/1511.
Full textDugas, Alexandre. "Architecture de transformée de cosinus discrète sur deux dimensions sans multiplication et mémoire de transposition." Mémoire, Université de Sherbrooke, 2012. http://hdl.handle.net/11143/6174.
Full textHmida, Hedi. "Étude et comparaison d'algorithmes de transformée en cosinus discrète en vue de leur intégration en VLSI." Paris 11, 1988. http://www.theses.fr/1988PA112133.
Full textMaschio, Nicole. "Contribution à la compression d'images numériques par codage prédictif et transformée en cosinus discrète avec utilisation de codes arithmétiques." Nice, 1989. http://www.theses.fr/1989NICE4281.
Full textUrbano, Rodriguez Luis Alberto. "Contribution à la compression d'images par transformée en cosinus discrète en imagerie médicale, et évaluation sur une base d'images multi-modalités." Tours, 1991. http://www.theses.fr/1991TOUR3307.
Full textCoudoux, François-Xavier. "Evaluation de la visibilité des effets de blocs dans les images codées par transformée : application à l'amélioration d'images." Valenciennes, 1994. https://ged.uphf.fr/nuxeo/site/esupversions/a0a7cc38-609d-4d86-9c3a-a018590bc012.
Full textNortershauser, David. "Résolution de problèmes inverses tridimensionnels instationnaires de conduction de la chaleur." Toulouse, ENSAE, 2000. http://www.theses.fr/2000ESAE0017.
Full textVirette, David. "Étude de transformées temps-fréquence pour le codage audio faible retard en haute qualité." Rennes 1, 2012. http://www.theses.fr/2012REN1E014.
Full textZhu, Zuowei. "Modèles géométriques avec defauts pour la fabrication additive." Thesis, Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLN021/document.
Full textThe intricate error sources within different stages of the Additive Manufacturing (AM) process have brought about major issues regarding the dimensional and geometrical accuracy of the manufactured product. Therefore, effective modeling of the geometric deviations is critical for AM. The Skin Model Shapes (SMS) paradigm offers a comprehensive framework aiming at addressing the deviation modeling problem at different stages of product lifecycle, and is thus a promising solution for deviation modeling in AM. In this thesis, considering the layer-wise characteristic of AM, a new SMS framework is proposed which characterizes the deviations in AM with in-plane and out-of-plane perspectives. The modeling of in-plane deviation aims at capturing the variability of the 2D shape of each layer. A shape transformation perspective is proposed which maps the variational effects of deviation sources into affine transformations of the nominal shape. With this assumption, a parametric deviation model is established based on the Polar Coordinate System which manages to capture deviation patterns regardless of the shape complexity. This model is further enhanced with a statistical learning capability to simultaneously learn from deviation data of multiple shapes and improve the performance on all shapes.Out-of-plane deviation is defined as the deformation of layer in the build direction. A layer-level investigation of out-of-plane deviation is conducted with a data-driven method. Based on the deviation data collected from a number of Finite Element simulations, two modal analysis methods, Discrete Cosine Transform (DCT) and Statistical Shape Analysis (SSA), are adopted to identify the most significant deviation modes in the layer-wise data. The effect of part and process parameters on the identified modes is further characterized with a Gaussian Process (GP) model. The discussed methods are finally used to obtain high-fidelity SMSs of AM products by deforming the nominal layer contours with predicted deviations and rebuilding the complete non-ideal surface model from the deformed contours. A toolbox is developed in the MATLAB environment to demonstrate the effectiveness of the proposed methods
Mammeri, Abdelhamid. "Compression et transmission d'images avec énergie minimale application aux capteurs sans fil." Thèse, Université de Sherbrooke, 2010. http://hdl.handle.net/11143/5800.
Full textAtrevi, Dieudonne Fabrice. "Détection et analyse des évènements rares par vision, dans un contexte urbain ou péri-urbain." Thesis, Orléans, 2019. http://www.theses.fr/2019ORLE2008.
Full textThe main objective of this thesis is the development of complete methods for rare events detection. The works can be summarized in two parts. The first part is devoted to the study of shapes descriptors of the state of the art. On the one hand, the robustness of some descriptors to varying light conditions was studied.On the other hand, the ability of geometric moments to describe the human shape was also studied through a3D human pose estimation application based on 2D images. From this study, we have shown that through a shape retrieval application, geometric moments can be used to estimate a human pose through an exhaustive search in a pose database. This kind of application can be used in human actions recognition system which may be a final step of an event analysis system. In the second part of this report, three main contributions to rare event detection are presented. The first contribution concerns the development of a global scene analysis method for crowd event detection. In this method, global scene modeling is done based on spatiotemporal interest points filtered from the saliency map of the scene. The characteristics used are the histogram of the optical flow orientations and a set of shapes descriptors studied in the first part. The Latent Dirichlet Allocation algorithm is used to create event models by using a visual document representation of image sequences(video clip). The second contribution is the development of a method for salient motions detection in video.This method is totally unsupervised and relies on the properties of the discrete cosine transform to explore the optical flow information of the scene. Local modeling for events detection and localization is at the core of the latest contribution of this thesis. The method is based on the saliency score of movements and one class SVM algorithm to create the events model. The methods have been tested on different public database and the results obtained are promising
Makkaoui, Leila. "Compression d'images dans les réseaux de capteurs sans fil." Phd thesis, Université de Lorraine, 2012. http://tel.archives-ouvertes.fr/tel-00795503.
Full textBaskurt, Atilla. "Compression d'images numériques par la transformation cosinus discrète." Lyon, INSA, 1989. http://www.theses.fr/1989ISAL0036.
Full textYu, Sungwook. "VLSI implementation of multidimensional discrete Fourier transform and discrete cosine transform /." Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
Full textHu, Ta-Hsiang. "Discrete cosine transform implementation in VHDL." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA245791.
Full textThesis Advisor(s): Lee, Chin-Hwa ; Yang, Chyan. "December 1990." Description based on title screen as viewed on March 29, 2010. DTIC Identifier(s): Fast Fourier Transform, High Level Languages, CHIPS (Electronics), Computerized Simulation, Signal Processing, Theses, Algorithms, Floating Point Operation, VHDL (Vhsic Hardware Description Language). Author(s) subject terms: FFT System, DCT System Implementation. Includes bibliographical references (p. 152). Also available in print.
Jin, Chengzhou. "Discrete Cosine Transform for Pre-coded EGPRS." Thesis, KTH, Signalbehandling, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-98761.
Full textAbedi, Safdar Ali Syed. "Exploring Discrete Cosine Transform for Multi-resolution Analysis." Digital Archive @ GSU, 2005. http://digitalarchive.gsu.edu/cs_theses/12.
Full textScargall, Lee David. "Very low bit-rate digital video coding." Thesis, University of Newcastle Upon Tyne, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299046.
Full textChua, Doi-eng, and 蔡岱榮. "Some variations on Discrete-Cosine-Transform-based lossy image compression." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2000. http://hub.hku.hk/bib/B31222523.
Full textDeng, An-Te. "VHDL behavioral description of Discrete Cosine Transform in image compression." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/28641.
Full textHantehzadeh, Neda. "3-D Face Recognition using the Discrete Cosine Transform (DCT)." Available to subscribers only, 2009. http://proquest.umi.com/pqdweb?did=1964658571&sid=3&Fmt=2&clientId=1509&RQT=309&VName=PQD.
Full textHaque, S. M. Rafizul. "Singular Value Decomposition and Discrete Cosine Transform based Image Watermarking." Thesis, Blekinge Tekniska Högskola, Avdelningen för för interaktion och systemdesign, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5269.
Full textPhone number: +88041730212
Hmida, Hedi. "Etude et comparaison d'algorythmes de transformée en cosinus discrète en vue de leur intégration VLSI." Grenoble 2 : ANRT, 1988. http://catalogue.bnf.fr/ark:/12148/cb37614318f.
Full textBhardwaj, Divya Anshu. "Inverse Discrete Cosine Transform by Bit Parallel Implementation and Power Comparision." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2447.
Full textThe goal of this project was to implement and compare Invere Discrete Cosine Transform using three methods i.e. by bit parallel, digit serial and bit serial. This application describes a one dimensional Discrete Cosine Transform by bit prallel method and has been implemented by 0.35 ìm technology. When implementing a design, there are several considerations like word length etc. were taken into account. The code was implemented using WHDL and some of the calculations were done in MATLAB. The VHDL code was the synthesized using Design Analyzer of Synopsis; power was calculated and the results were compared.
Shah, Rajul R. (Rajul Ramesh) 1979. "Hardware implementation of a low-power two-dimensional discrete cosine transform." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/16859.
Full textIncludes bibliographical references (p. 143-144).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
In this project, a JPEG compliant, low-power dedicated, two-dimensional, Discrete Cosine Transform (DCT) core meeting all IBM Softcore requirements is developed. Power is optimized completely at the algorithmic, architectural, and logic levels. The architecture uses row-column decomposition of a fast 1-D algorithm implemented with distributed arithmetic. It features clock gating schemes as well as power-aware schemes that utilize input correlations to dynamically scale down power consumption. This is done by eliminating glitching in the ROM Accumulate (RAC) units to effectively stop unnecessary computation. The core is approximately 180K transistors, runs at a maximum of 100MHz, is synthesized to a .18[mu]m double-well CMOS technology with a 1.8V power supply, and consumes between 63 and 87 mW of power at 100MHz depending on the image data. The thesis explores the algorithmic evaluations, architectural design, development of the C and VHDL models, verification methods, synthesis operations, static timing analysis, design for test compliance, power analysis, and performance comparisons for the development of the core. The work has been completed in the ASIC Digital Cores I department of the IBM Microelectronics Division in Burlington, Vermont as part of the third assignment in the MIT VI-A program.
by Rajul R. Shah.
M.Eng.
Der, Sarkissian Henri. "Tomographie et géométrie discrètes avec la transformée Mojette." Nantes, 2015. https://archive.bu.univ-nantes.fr/pollux/show/show?id=a404e001-c417-4fae-86db-d3734355a07e.
Full textWe explore through this thesis the insights of discrete tomography over classical tomography in continuous space. We use the Mojette transform, a discrete and exact form of the Radon transform, as a link between classical tomography and discrete tomography. We focus especially on the study of the discrete space induced by the Mojette transform operator through four research axis. Axis 1 focuses on the Mojette space properties in regards to discrete affine transforms of digital images. We provide tools to achieve affine transforms directly from the projections of a digital object, without preliminary tomographic reconstruction. This property is well-known for the continuous Radon transform but non-trivial for its sampled versions. Axis 2 seeks for some links between continuous-sampled projections related to medical imaging acquisition modalities and discrete projections derived by the Mojette transform. We implement interpolation schemes to estimate discrete projections from the continuous ones — on either synthetic or real data — and their reconstruction. In axis 3, we provide an algebraic framework for the description and inversion of the Mojette transform. The input data, the projections as well as the operators are modeled as polynomials. Within this framework, the Mojette projection operator advantageously reduce to a Vandermonde matrix. This thesis has been realized at both IRCCyN Lab and Keosys company within the Quanticardi FUI project. Axis 4 focuses on the design and the implementation of a clinical software for the absolute quantification of myocardial perfusion with positron emission tomography
Martucci, Stephen A. "Symmetric convolution and the discrete sine and cosine transforms : principles and applications." Diss., Georgia Institute of Technology, 1993. http://hdl.handle.net/1853/15038.
Full textBanham, Benjamin E. "An Evolutionary Approach to Image Compression in the Discrete Cosine Transform Domain." DigitalCommons@USU, 2008. https://digitalcommons.usu.edu/etd/5.
Full textMclean, Ivan Hugh. "An adaptive discrete cosine transform coding scheme for digital x-ray images." Thesis, Rhodes University, 1989. http://hdl.handle.net/10962/d1002032.
Full textPagliari, Carla Liberal. "Perspective-view image matching in the DCT domain." Thesis, University of Essex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.298594.
Full textOyana, Damalie M. "Implementation of a new data stream clustering algorithm using discrete cosine transformed data /." Available to subscribers only, 2006. http://proquest.umi.com/pqdweb?did=1203588021&sid=12&Fmt=2&clientId=1509&RQT=309&VName=PQD.
Full textWang, Jiun-Lung, and 王俊隴. "EFFICIENT RECURSIVE STRUCTURES FOR DISCRETE COSINES TRANSFORMS." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/10490926827771364154.
Full text國立成功大學
電機工程學系
87
Discrete cosine transform (DCT) is widely used in video and image compression. In this thesis, we proposed two new recursive structures for computing DCT. This recursive structure is based on finite impulse response filter (IIR). One kind of them is the IIR form with fixed and selected filter coefficient. The advantage is that it only needs one filter module for computing all DCT components. The other kind is using several IIR structures for concurrent computing DCT components. The advantages are efficiency and high throughput rate. They are also suitable for VLSI implementation because of their regularity and modularity. In thesis, we contribute a VLSI realization with efficient recursion DCT algorithm. We use COMPASS 0.6μm high performance cell library for TSMC SPTM 0.6μm process technology. It integrates about 36k gates in a 4mm 4mm silicon area. The measurement result shows that this chip can operate at 29MHz clock rate.
Tsai, Hsing-Juan, and 蔡幸娟. "A Parameterizable Architecture for Two-Dimensional Discrete Cosine Transform and Inverse Discrete Cosine Transform." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/66341916946119230484.
Full text逢甲大學
資訊工程所
93
The Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transforms (IDCT) are widely used in various audio and image processing applications. Because of the computation complexity of these algorithms, the dedicated hardware is usually required to achieve the performance of real-time applications. This thesis presents an efficient implementation of a two-dimensional DCT/IDCT processor using a serial-parallel systolic array architecture. The data transfer between processing elements is propagated serially in order to reduce the data communication cost. The data within the processing element is computed in a parallel manner to make the architecture high-speed. By carefully collocating the propagate data in the register of processing element, the transposition operation can be eliminated in this architecture. The block size of 2-D DCT/IDCT and the bit-width of computation data are extracted as parameters that can easily and systematically be adapted to conform to the various imaging coding standard. The behavior and structure model in C language is used to verify the correctness of the 2-D DCT/IDCT computation and the parameterizable implementation. The precision analysis of the 2-D DCT/IDCT implementation was performed by MatLab. The DCT design cost about 14K gate counts when block size is 8 and bit width is 6. The numbers of gate count increase 4 times when block size increases 2 times and those increase about 1.5 times when bit width increases 2 times.
Hwang, Jen-Jyh, and 黃仁志. "Digital Watermarking by Discrete Cosine Transform." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/99105407359663155102.
Full text世新大學
資訊管理學研究所(含碩專班)
98
With the rapid development and extensive use of multimedia and network technology, multimedia protection such as image, audio, video is an urgent issue. It has been widely concerned to view watermarking technology as a powerful tool for copyright protection and safety certification. The paper is based on watermarks hiding creation by Discrete Cosine Transform (DCT) to analyze the robustness of the watermarked images. By not affecting the visually indistinguishable, this research hopes to provide bigger help for the area of watermarks hiding and digital documents.
Liu, Chun-Wen, and 劉仲文. "Adaptive Voltage Scaling for Discrete Cosine Transform." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/00937421266683497648.
Full text國立交通大學
電子工程系所
96
In the modern digital IC system, adaptive voltage scaling is the most efficient technology for low power design. A new variable voltage generator (VVG) has been proposed in this paper. Five voltage levels ranged from 0.8V to 1.2V can be generated. An adaptive voltage scaling controller has been developed to fit the VVG to form an adaptive voltage scaling control system. In stead of the off-chip DC-DC converter which is often used in voltage regulation, the on-chip VVG takes an important roll in this system. Discrete Cosine Transform (DCT) has become one of the widely used transform techniques in digital signal processing. The adaptive voltage scaling system has been applied to DCT and reduces at most 45% power consumption of DCT. All simulations are implemented in TSMC0.13-μm CMOS technology.
Tsai, Ya-Ting, and 蔡雅婷. "Object Detection with Integer Discrete Cosine Transform." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/40998194573150464909.
Full text中華大學
資訊工程學系碩士班
100
Multimedia technologies, including those for video- and image-related applications, are widely used in various fields, such as security surveillance, medical diagnosis, education, entertainment, and business presentations. Moving objects are of significant interest in surveillance applications. Therefore, detecting the moving objects and identifying their moving trajectories may provide useful information for assuring the security of the monitored site. However, many lighting conditions cause video cameras to record the shadows of moving objects in video images. To identify accurate moving trajectories, the shadows associated with moving objects need to be removed from the recorded video images. Otherwise, false alarm may be triggered, or miscalculation may result. In this thesis, we propose a real-time method for verifying a block belonging to a moving object block or a shadow block. The method includes the following phases. First, we simplify the DCT transformation to construct a novel integer DCT transformation. Second, based on the integer DCT transformed DC and AC coefficients, the background variations are modeled via the GMM probabilistic models. Third, by analyzing the respective variances of the DC and the AC coefficients we can determine the foreground as a moving object or a shadow region. Experimental results show that our method outperforms the conventional methods in terms of accuracy and efficiency.
Chen, Chingson, and 陳慶勳. "Design and Implementation of Discrete Cosine Transform." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/38242894398568802620.
Full text國立交通大學
電子研究所
83
Discrete Cosine Transform (DCT) is now used in many communication standards for the removal of redundancies of correlation in random sequences. A random sequence with less correlation could be well compressed after quantisation and entropy coding. Since DCT and its inverse (IDCT) cost much computation power, the design of DCT or IDCT is important in overall system consideration. Traditionally, ROM-Based Distributed Arithmetic (DA) architecture has been used in many commercial systems. Since ROMs cost much area in ROM-Based DA, a new architecture named Adder-Based DA replacing ROMs with serial adders is proposed in this thesis. This new architecture cost much less area than traditionally ROM-Based DA since the ROMs are all replaced by small serial adders. An IDCT chip with 16 mm^2 core area by CCL CMOS standard cells is designed and implemented in this thesis and speed of 98 M pels/ sec is achieved in simulation of VERILOG.
Chung, Ming-Shen, and 鐘明聲. "FPGA Implementation of the Discrete Fourier Transform (DFT) and the Discrete Cosine Transform (DCT)." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/01456280849939764692.
Full text國立高雄第一科技大學
電腦與通訊工程所
90
The Discrete Fourier Transform(DFT)has been widely applied in communcation, speech processing, image processing, radar and sonar systems, etc. The architecture of DFT implement can be classified into two fields:(1)one is a pipelined systolic architecture,(2)the other is a memory-based architecture. Discrete Cosine Transform(DCT)has been commonly adopted in the various atandardsfor image compression while FPGA has become a new trend of ASIC design, so we will apply FPGA techinque to implement the DFT and the DCT. This thesis deals with how to use FPGA techinque to implement: (1)the pipelined systolic array architecture that requires log2N complex multipliers, 2log2N complex adders, 2log2N multiplexers, N delay elements and is able to provide a throughput of one transform sample per clock cycle; (2)the memory-based architecture that consists of three two-port RAM’s, one ROM, one complex multiplier, two complex adders, one multiplexer, and has capability of computing one transform sample every log2N+1 clock cycles on average; (3)Improved architecture in(2)under increasing little hardware that spends half of run time, i.e.N(log2N)/2; (4)2D-DFT that use architecture in(2)of 1D-DFT; (5)DCT operation and 2D-DCT operation.
Poplin, Dwight. "Distributed arithmetic architecture for the discrete cosine transform." Thesis, 1997. http://hdl.handle.net/1957/34243.
Full textGraduation date: 1997
ZHENG, BO-WEN, and 鄭博文. "Design of three dimension discrete cosine transform coder." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/86282721872260597212.
Full textLIN, GUO-ZHEN, and 林國楨. "VLSI implementation of 2-dimensional discrete cosine transform." Thesis, 1991. http://ndltd.ncl.edu.tw/handle/86587200420273634574.
Full textWu, Yung-Gi, and 吳永基. "Finite State Discrete Cosine Transform for Image Compression." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/68322478679918275389.
Full text國立成功大學
電機工程研究所
82
In this thesis,a new image compression method is devised. Discrete Cosine Transform is the kernel of the compressor. The new technique classifies the image subblock into eights classes by their characteristics which can be got from the transfomed domain.Four edge classes,three texture classes ,one smooth class.This kind of classification is called Three Model Classification.As to the overhead of classification ,finite state concept is used to reduce the overhead by predicting the current block's class from the previously blocks. In order to promote the correct ratio of prediction,edge orientation should be considered.We exploit the relationship between the transformed domain and edge orientation.As we know, the smooth regions occupy most part of a natual images.Larger coding size can get higher compression ratio in the smooth regions. But this will sacrifice the quality of complicated regions.In order to solve this deficiency.We devised a variable block coding size algorithm.The edge blocks use the fixed 8*8 block to keep the detailed parts and the variable block size segmentation scheme is applied to texture and smooth regions. The new segmentation method is called "class driven segmentation" The overhead of the segmention is zero. The simulation results show good quality for the decoded images.
Hsieh, Yen-Long, and 謝顏隆. "Architecture Design of H.264 Discrete Cosine Transform." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/74024470056539167481.
Full text國立成功大學
電機工程學系碩博士班
97
This thesis proposes a Discrete Cosine Transform architecture with high throughput and low area. This architecture can be applied in H.264 High Definition (HD) resolution video products. In H.264, the block sizes of the Discrete Cosine Transform are 4×4 and 8×8. The 8×8 block size transform is mainly used in Standard Definition resolution, High Definition resolution, and above Definition resolution. This thesis implements an 8×8 transform architecture. For application in HD resolution video products, the proposed architecture supplies enough high throughput, but a big area should also be associated with a high throughput. Through some property of the DCT, this thesis shows that the area can be reduced and then a high throughput and small area architecture can be implemented. In the proposed architecture, the specification of proposed architecture is 1080p and 60 frames per second. The proposed architecture is synthesized with TSMC 0.18 μm technology cell library and the operating speed is 81 MHz. In this operation speed, the proposed architecture has smaller area when compared with other architectures which also implement H.264 8×8 DCT architecture recently.
Liu, Jian-Cheng, and 劉建成. "Multi-dimentional Discrete Cosine Transform (DCT) Chip Design." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/56071432152209136424.
Full textHuang, Mu-Chang, and 黃牧常. "3D Face Recognition Using Discrete Cosine Transform Approach." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/67021825468958961692.
Full text義守大學
電機工程學系
92
It is found that the feature extraction is important in recognition systems, such as faces recognition systems. This thesis studies a 3D face recognition system using the height information in the 3D face as the features. The 3D face database is built up by our 3D reconstruction system. The difference between 3D faces and 2D faces is that the variable in a 3D face including height information rather than the grey level in a 2D face image. The well known Discrete Cosine Transform and Principle Components Analysis method express very good performance in the image compression and faces recognition respectively. In this thesis, we propose the approach which combines DCT and PCA in forming face characteristic coefficient extraction, and compare the results with that using PCA and Wavelet Transform in the 3D face and the 2D face recognition. Our experimental results shows that the combined DCT and PCA approach has outstanding performance. The Nearest Feature Line, Linear Discriminant Analysis and Euclidean Distance are also incorporated into the process to improve the stability and robustness in the recognition system.
LIN, RUI-QI, and 林瑞琦. "A study of discrete cosine and hartley transform." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/63434531522833015784.
Full textShan, Yi-Chia, and 單益嘉. "ASYNCHRONOUS TWO-DIMENSION DISCRETE COSINE TRANSFORM CIRCUIT DESIGN." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/92076365087289606386.
Full text大同大學
通訊工程研究所
96
This thesis proposes an asynchronous two-dimension discrete cosine transform (2-D DCT) processor. In asynchronous design, we used Sutherland’s Micropipelines to implement handshake pipeline. In DCT process, we adopt row-column decomposition method to separate 2-D DCT into two one-dimensional discrete cosine transform (1-D DCT) and a transpose memory. In order to realize the matrix calculation easily, multiplier and accumulator method has been adapted. We implement 2-D DCT function with Field Programable Gate Array (FPGA), and verify the design by the function simulation and timing simulation. FPGA has the programble property, so it’s very convient to be used in design level. We design asynchronous circuit which is based on FPGA architecture. The proposed circuit has asynchronous design spirit, but not completely followed the asynchronous design of the reference paper. The timing simulation result of 2-D DCT is not satisfied, the reason is related with FPGA architecture and the compile tool. Because we can not control the placement and routing of the circuit very well, the programs are auto compiled by FPGA tool, so it could cause the circuit failed. Although we met many challenges in FPGA design, but these experiences can be refered in the future ASIC asynchronous design.
Lao, Hsing-Sheng, and 勞杏生. "Two-Dimension Interpolation Scheme Using Discrete Cosine Transform." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/10377114762758902394.
Full text大同大學
通訊工程研究所
92
The interpolation of an image provides an approach to sample an image at a low rate for transmission or storage and then increase the sampling rate later. Some basic properties of an interpolator must satisfy these zero crossings guarantee that the image is not modified if it is resampled on the same grid. In addition to, the complexity of the interpolation algorithm is needed to be considered. Based on the above principles, a DCT (Discrete Cosine Transform) is proposed to do two-dimensional interpolation. We compare the results of using DCT with those of conventional using DFT (Discrete Fourie Transform) interpolation scheme and Wang’s DFT interpolation scheme. The experiment results show that no matter with human subjective perception to observe or with PSNR(Peak Signal - to - Noise Ratio)error metrics to measure, the results of two-dimensional DCT interpolation scheme are better than those of two-dimensional conventional DFT interpolation scheme and there is no big difference between the methods of two-dimensional DCT interpolation and Wang’s improved two-dimensional DFT interpolation scheme. And the complexity of the two-dimensional DCT interpolation algorithm is simpler than that of two-dimensional DFT one.
Lin, You-Chung, and 林友中. "Design and Test of Discrete Cosine Transform Circuits." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/24801626295131883922.
Full text國立成功大學
電機工程學系碩博士班
91
We present three testable 2-D Discrete Cosine Transform (DCT) circuits with high fault coverage and short test application time. The three DCT circuits are implemented with the row-column decomposition method, the direct method, and the folded direct method, respectively. We do some modifications when designing these DCT circuits to improve their fault coverage. These modifications include scan design, ad hoc design, and pipeline design, which are used according to different circumstances of these DCT circuits. After the modifications on these circuits, their fault coverage can reach 100% or near 100%. However, inserting scan design and pipeline design into the circuits would substantially increase the test application time. To overcome this defect, we apply two testing methods, namely the input reduction testing method and the broadcasting scan method, to these circuits. With these methods the test application time can be reduced to 0.647%~15.48% of those of the original circuits with single full scan design, and the area overhead is 5.84%~9.16% of those of the original circuits.