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Bulja, Senad. "New phase shifter, amplifier linearisation and transistor characterisation." Thesis, University of Essex, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.442786.
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Julien, Marquis C. "Bipolar transistor modelling from a power amplifier designer's perspective." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp04/mq22121.pdf.
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Julien, Marquis C. (Marquis Christian) Carleton University Dissertation Engineering Electronics. "Bipolar transistor modelling from a power amplifier designer's perspective." Ottawa, 1997.
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Gallagher, Jeanne M. B. "A monolithic bipolar junction transistor amplifier in the common emitter configuration." Honors in the Major Thesis, University of Central Florida, 1992. http://digital.library.ucf.edu/cdm/ref/collection/ETH/id/98.
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Electrical Engineering
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Neethling, M. (Marthinus). "A broadband microwave limiting amplifier." Thesis, Stellenbosch : University of Stellenbosch, 2004. http://hdl.handle.net/10019.1/16406.
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Thesis (MScIng)--University of Stellenbosch, 2004.ENGLISH ABSTRACT: Limiting amplifiers are employed in electronic warfare (EW) systems requiring a high measure of amplitude control. These EW systems employ sensitive signal processing components that are unable to accept the full dynamic range of input signals the system must face. The limiting amplifier, however, offers the unique capability of reducing the received signal spectrum to a suitable dynamic range. A typical application of the limiting amplifier is in the instantaneous frequency measurement (IFM) receiver where the limiting amplifier allows the receiver to accurately measure pulsed signals over a wide input dynamic range The aim of this study is the design and analysis of a broadband limiting amplifier. Focus is placed on the design of a socalled backbone limiting amplifier (BLA) which forms an integral part of a proposed modular design approach for realizing a design with improved input dynamic range. A designed BLA is discussed in this thesis while insight is given as to the intricacies associated with its mechanism of operation. Over its 45 dB (- 40 to + 5 dBm) input dynamic range, the designed 2-18 GHz limiting amplifier offers a typical saturated output power of 7.5 dBm while harmonic suppression of better than 8.6 dBc is achieved. The BLA design was based on an existing limiting amplifier design, the so-called baseline limiting amplifier, employing alternating amplifiers and attenuators. Evaluation of the baseline limiting amplifier design allowed for formulation of a design hypothesis for realizing the BLA design. Physical measurements on the BLA were then used to scrutinize and validate the formulated design hypothesis. The requirements for realizing the BLA design were the establishment of a thorough radio frequency (RF) amplifier design capability, an understanding of the nonlinear phenomena associated with the RF amplifier and the utilization and control thereof within the limiting amplifier. Different RF amplifier designs that were carried out are discussed in this thesis, while it is shown how they were used to further investigate important design considerations for application in the BLA design. The computer-aided design packages namely MultiMatch and Microwave Office (MWO) were successfully used in realizing the desired broadband RF amplifier designs and the eventual BLA design.
AFRIKAANSE OPSOMMING: Beperker versterkers word gebruik in elektroniese oorlogvoering (EO) stelsels waar ’n redelike mate van amplitude beheer noodsaaklik is. Sensitiewe seinverwerking komponente, wat nie die volle dinamiese bereik van intreeseine kan hanteer nie, maak deel uit van hierdie EO stelsels. Die beperker versterker bied egter die unieke eienskap om die ontvangde seinspektra te reduseer tot ’n gepaste dinamiese bereik. ’n Tipiese toepassing vir die beperker versterker is as deel van die oombliksfrekwensie- meting ontvanger waar die beperker versterker die ontvanger toelaat om akkurate meting van gepulsde seine te doen oor ’n wye intree dinamiese bereik. Die doel van hierdie studie is die ontwerp en analise van ’n wye-band beperker versterker. Fokus word geplaas op die ontwerp van ’n sogenaamde kruks beperker versterker wat ’n integrale deel uitmaak van ’n voorgestelde modulêre ontwerpsbenadering, wat ten doel het om ’n verbeterde intree dinamiese bereik daar te stel. Oor die 45 dB (- 40 tot + 5 dBm) intree dinamiese bereik, bied die ontwerpte 2-18 GHz beperker versterker ’n tipiese versadigde uittreedrywing van 7.5 dBm terwyl harmonieke onderdrukking van beter as 8.6 dBc verkry is. Die ontwerp van hierdie komponent word in hierdie tesis bespreek terwyl belangrike aspekte oor die werking daarvan uitgelig word. Die ontwerp van die kruks beperker versterker is gebaseer op ’n bestaande beperker versterker ontwerp, of sogenaamde basis ontwerp, wat gebruik maak van afwisselende versterkers en attenuators. Evaluering van die basis ontwerp het toegelaat vir die formulering van 'n ontwerpshipotese om die kruks beperker versterker te realiseer. Fisiese metings op die kruks beperker versterker is gebruik om die ontwerpshipotese krities te evalueer. Om die kruks beperker versterker te realiseer moes die nodige RF versterker ontwerpsvaardigheid daargestel word, ’n begrip vir die nie-liniêere verskynsels in die RF versterker en die gebruik en beheer daarvan in die beperker versterker moes daargestel word. Verskeie RF versterkers wat ontwerp is word in hierdie tesis bespreek, terwyl getoon word hoe hierdie ontwerpe gebruik is om belangrike ontwerpsaspekte te ondersoek wat uiteindelik toegepas is in die kruks beperker versterker ontwerp. Die ontwerpspakkette naamlik MultiMatch en Microwave Office is suksesvol gebruik vir die realisering van die nodige wye-band RF versterkers en die uiteindelike kruks beperker versterker ontwerp.
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Hashim, Shaiful Jahari. "Wideband active envelope load-pull for robust power amplifier and transistor characterisation." Thesis, Cardiff University, 2010. http://orca.cf.ac.uk/54181/.
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The advent of fourth generation (4G) wireless communication with available modulation bandwidth ranging from 1 MHz to 20 MHz is starting to emerge. The linear modulation technique being employed means that the power amplifiers that support the standards need to have high degree of linearity. By nature, however, all power amplifiers are non-linear. Load-pull measurement system provides anindispensable non-linear tool for the characterization of power amplifier and transistor for linearity enhancement. Conventional passive or active load-pull has delay problem that get worse as the modulation frequency is increased beyond few MHz. Furthermore in order to provide robust non-linear measurement, load-pull system needs to provide bandwidth at least five times the modulation bandwidth by including the fifth-order inter-modulation (IMD5). This thesis presents, for the first time, delay compensation on the unique active envelope load-pull architecture providing constant impedance for bandwidth up to 20 MHz. In doing so, it provides a superior load-pull measurement and also the ability to directly control in-band impedances. Artificial variations imposed on the in-band impedances offer further insight on power amplifier and transistor behaviours under wideband multi-tone stimulus.
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Varelas, Theodoros Carleton University Dissertation Engineering Electrical. "A monolithic BiCMOS power amplifier for low power digital radio transmitter." Ottawa, 1992.
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Rastogi, Priyam. "Design of a Novel Transistor and aMicrowave Pallet&Testing of a Novel Power Amplifier." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-105077.
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Radiofrekvens baserad teknik har utlöst ett stort område inom forskning och utveckling. Denna avhandling arbete bygger på RF krafttransistorer och deras sedvänjor i olika tillämpningar. Traditionellt har RF-transistorer som används i applikationer basstationer. Men nu är de som används i nya applikationer som mikrovågstillämpningar, medicinsk utrustning, energikällor för kapning av trä, torkning kläder och för offentlig belysning. Därför designa RF transistorer krävs för att göra dem lämpliga för deras nya program. Avhandlingen fokuserar på att bygga mycket effektiva och billigt RF transistorer och RF förstärkare genom omkonstruktion flera avsnitt av dem. Rapporten är indelad i tre sektioner. Den första delen beskriver en ny RF-transistor från design till slutlig testfas. Förpackningen stil nya RF-effekttransistor modifieras genom att använda olika material för att göra förpackningar enklare och tillverkningsprocess mer effektiv. Den modifierade RF-transistorn visade positiva resultat, medan testning som styrker möjligheten att använda det nya paketet för RF-transistor. Den andra delen av rapporten beskriver en mikrovågsugn pall omdesignad genom att anpassa transistorn byggd i det första avsnittet. Detta omkonstruktion har en extra fördel av enkelhet, färre steg tillverkning och låg kostnad. Denna mikrovågsugn pall har en bandbredd på drift från 2900MHz till 3300MHz. Liknande till transistorn har mikrovågsugn pall förpackningen stil omgjorda utan att påverka dess elektriska beteende. Pallen visade positiva resultat, medan testning, vilket visar på genomförbarheten av denna nya design. Den sista delen av rapporten beskriver testning av en ny effektförstärkare. Syftet med detta test var att observera effekten på olika delar av effektförstärkaren under avlägsnande av cirkulatorn från det. Testet utfördes för att minska kostnaderna och storleken hos effektförstärkaren. Testet var inte helt lyckad indikerar behovet av omkonstruktion effektförstärkaren. Arbetet som presenteras i denna rapport representerar inledande forskning som behöver omfattande granskas i framtiden att minska kostnaderna och tillverkning tiden för RF-produkter.Radio frequency based technology has unleashed a vast area in research and development. This thesis work is based on RF power transistors and their usages in different applications. Traditionally, RF transistors were used in base station applications. But now, they are being used in new applications like microwave applications, medical equipment, energy sources for cutting wood, drying clothes, and street lighting systems. Hence redesign of RF transistors is required to make them suitable for their new applications. The thesis work focuses on building highly efficient yet cheap RF transistors and RF amplifiers by redesigning several sections of them. This report is divided into three sections. The first section describes a novel RF transistor from design to final testing phase. The packaging style of the new RF power transistor is modified by using different material to make packaging process simpler and manufacturing process more efficient. The modified RF transistor showed positive results while testing, thus proving the feasibility of using the new package for RF transistor. The second section of the report describes a microwave pallet redesigned by adapting the transistor built in the first section. This redesigning has an added advantage of simplicity, fewer manufacturing steps, and low cost. This microwave pallet has a bandwidth of operation from 2900MHz to 3300MHz. Similar to the transistor, the microwave pallet packaging style was redesigned without affecting its electrical behavior. The pallet showed positive results while testing, thus proving the feasibility of this new design. The last section of the report describes the testing of a novel power amplifier. The aim of this test was to observe the effect on various parts of the power amplifier while removing the circulator from it. The test was performed to reduce the cost and size of the power amplifier. The test was not completely successful indicating the need for redesigning the power amplifier. The work presented in this report represents initial research that needs to be extensively examined in the future to reduce the cost and manufacturing time of the RF products.
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Yoo, Seungyup. "Field effect transistor noise model analysis and low noise amplifier design for wireless data communications." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13024.
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Cardon, Christopher Don. "1/f AM and PM noise in a common source heterojunction field effect transistor amplifier." Laramie, Wyo. : University of Wyoming, 2007. http://proquest.umi.com/pqdweb?did=1317343431&sid=1&Fmt=2&clientId=18949&RQT=309&VName=PQD.
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Vagts, Christopher Bryan. "A single-transistor memory cell and sense amplifier for a gallium arsenide dynamic random access memory." Thesis, Monterey, California. Naval Postgraduate School, 1992. http://hdl.handle.net/10945/24038.
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Approved for public release; distribution is unlimitedThis thesis presents the design and layout of a Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM) cell. Attempts have been made at producing GaAs DRAM cells, but these have dealt with modifications to the fabrication process, are expensive, and have met with little success. An eight-address by one-bit memory is designed, simulated, and laid out for a standard GaAs digital fabrication process. Three different configurations of RAM cells are considered: the Three-Transistor RAM Cell, the One-Transistor RAM Cell with a Diode and the One-Transistor RAM Cell with a capacitor. All are tested and compared using the circuit simulator HSPICE. The chosen DRAM design uses the One- Transistor RAM Cell with a parallel plate capacitor and a five-transistor differential sense amplifier that handles reading as well as refresh of the memory cells. The differential sense amplifier compares a dummy cell with a memory cell to perform a read. The required timing is presented and demonstrated with read, write, and refresh cycles. Actions to minimize charge leakage are also considered and discussed. The design is simulated for access rates of approximately five nanoseconds, but the basic design can work at much faster rates with little modification.
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Sajedin, M., Issa T. Elfergani, J. Rodriguez, M. Violas, Abdalfettah S. Asharaa, Raed A. Abd-Alhameed, M. Fernandez-Barciela, and A. M. Abdulkhaleq. "Multi-Resonant Class-F Power Amplifier Design for 5G Cellular Networks." RadioEngineering, 2020. http://hdl.handle.net/10454/18495.
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yesThis work integrates a harmonic tuning mechanism in synergy with the GaN HEMT transistor for 5G mobile transceiver applications. Following a theoretical study on the operational behavior of the Class-F power amplifier (PA), a complete amplifier design procedure is described that includes the proposed Harmonic Control Circuits for the second and third harmonics and optimum loading conditions for phase shifting of the drain current and voltage waveforms. The performance improvement provided by the Class-F configuration is validated by comparing the experimental and simulated results. The designed 10W Class-F PA prototype provides a measured peak drain efficiency of 64.7% at 1dB compression point of the PA at 3.6GHz frequency.
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Filko, Patrik. "Analogové funkční převodníky pro laboratorní výuku." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-400536.
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This master’s thesis deals with the design and the realization of a laboratory teaching device, which includes two-port parts with nonlinear transmission characteristics corresponding to quadratic, inverse quadratic and cubic functions. It also includes a more complicated design of a polynomial function converter that offers students a practical view of functions mathematically designed while verifying their accuracy in laboratory exercises. The whole concept is supported by the design of the power supply circuit and the harmonic signal generator. The individual features of this project are feasible from components commercially available.
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Heo, Deukhyoun. "Silicon MOS field effect transistor RF/Microwave nonlinear model study and power amplifier development for wireless communications." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/15618.
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Rodriguez, Luis. "Design of a Monolithic Bipolar Junction Transistor Amplifier in the Common Emitter with Cascaded Common Collector Configuration." Honors in the Major Thesis, University of Central Florida, 2004. http://digital.library.ucf.edu/cdm/ref/collection/ETH/id/724.
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Engineering and Computer Science
Electrical Engineering
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Najjari, Hamza. "Power Amplifier Design Based on Electro-Thermal Considerations." Thesis, Bordeaux, 2019. http://www.theses.fr/2019BORD0422.
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L’objectif de ce travail de recherche est de concevoir un amplificateur de puissance sur la base de considérations électrothermiques. Il décrit la question du dynamique EVM et du « paquet long » lors de la conception de l’amplificateur avec des transistors bipolaires à hétérojonctions. Basé sur le comportement électrothermique du circuit, une méthode d’optimisation de l’EVM statique et dynamique est proposée. Un frontend RF complet (amplificateur de puissance + coupleur + interrupteur + amplificateur faible bruit) est conçu pour le dernier standard WLAN : le Wi-Fi 6. La distribution de temperature dynamique dans le circuit est analysée. Son effet sur les performances de la puce est quantifié. Enfin, une polarisation adaptative programmable a été conçue pour garder des performances optimales sur toute la plage de température. Les mesures du circuit montre tout l’effet bénéfique de cette compensation, permettant de garder le dynamique EVM en dessous de -47 dB sur la plage de température ambiante de -40 à 85°CThe aim of this work is to design a power amplifier based on electrothermal considerations. It describes the Dynamic Error Vector Magnitude challenge and long packet issue when designing a power amplifier with hetero-junction bipolar transistors. Based on the circuit electrothermal behavior, an optimization method of both the static and dynamic linearity is proposed. A complete RF front-end (PA + coupler + switch + LNA) is designed for the latest WLAN standard: the Wi-Fi 6. The dynamic temperature distribution in the circuit is analyzed. It’s impact on the performances is quantified. Finally, a programmable temperature dependent bias is designed to compensate for performance degradation. The measurements show a significant linearity improvement with this compensation, allowing the PA to maintain the DEVM lower than -47dB at 14.5 dBm output power, over a large ambient temperature range from -40°C to 85°C
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Henry, Michael B. "Emerging Power-Gating Techniques for Low Power Digital Circuits." Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/29627.
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As transistor sizes scale down and levels of integration increase, leakage power has become a critical problem in modern low-power microprocessors. This is especially true for ultra-low-voltage (ULV) circuits, where high levels of leakage force designers to chose relatively high threshold voltages, which limits performance. In this thesis, an industry-standard technique known as power-gating is explored, whereby transistors are used to disconnect the power from idle portions of a chip. Present power-gating implementations suffer from limitations including non-zero off-state leakage, which can aggregate to a large amount of wasted energy during long idle periods, and high energy overhead, which limits its use to long-term system-wide sleep modes. As this thesis will show however, by vastly increasing the effectiveness of power-gating through the use of emerging technologies, and by implementing aggressive hardware-oriented power-gating policies, leakage in microprocessors can be eliminated to a large extent. This allows the threshold voltage to be lowered, leading to ULV microprocessors with both low switching energy and high performance.
The first emerging technology investigated is the Nanoelectromechnical-Systems (NEMS) switch, which is a CMOS-compatible mechanical relay with near-infinite off-resistance and low on-resistance. When used for power-gating, this switch completely eliminates off-state leakage, yet is compact enough to be contained on die. This has tremendous benefits for applications with long sleep times. For example, a NEMS-power-gated architecture performing an FFT per hour consumes 30 times less power than a transistor-power-gated architecture. Additionally, the low on-resistance can lower power-gating area overhead by 36-83\%.
The second technology targets the high energy overhead associated with powering a circuit on and off. This thesis demonstrates that a new logic style specifically designed for ULV operation, Sense Amplifier Pass Transistor Logic (SAPTL), requires power-gates that are 8-10 times smaller, and consumes up to 15 times less boot-up energy, compared to static-CMOS. These abilities enable effective power-gating of an SAPTL circuit, even for very short idle periods. Microprocessor simulations demonstrate that a fine-grained power-gating policy, along with this drastically lower overhead, can result in up to a 44\% drop in energy.
Encompassing these investigations is an energy estimation framework built around a cycle-accurate microprocessor simulator, which allows a wide range of circuit and power-gating parameters to be optimized. This framework implements two hardware-based power-gating schedulers that are completely invisible to the OS, and have extremely low hardware overhead, allowing for a large number of power-gated regions. All together, this thesis represents the most complete and forward-looking study on power-gating in the ULV region. The results demonstrate that aggressive power-gating allows designers to leverage the very low switching energy of ULV operation, while achieving performance levels that can greatly expand the capabilities of energy-constrained systems.Ph. D.
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Janic, Lukáš. "Výkonový zesilovač a jeho linearizace pomocí lokálních zpětných vazeb." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2018. http://www.nusl.cz/ntk/nusl-376943.
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The thesis deals with the construction of a linear power amplifier. Theoretical analysis of the final work explains the function of the amplifier blocks, which is necessary to understand the functions of the whole construction. Thesis continues in simulation analysis of separate blocks or whole construction and at the end of the implementation of the complete power amplifier.
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Kiefer, Jean-Georges. "Contribution à l'étude des effets de la réduction des dimensions du transistor MOS : application à la conception des circuits intégrés analogiques CMOS." Grenoble 1, 1986. http://www.theses.fr/1986GRE10105.
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Ce memoire traite des effets de petites dimensions du transistor metal-oxyde-semiconducteur (mos). Les principales methodes de maigrissement sont analysees et les grandes lignes de l'evolution des technologies mos sont esquissees. Un modele courant-tension du transistor, qui prend en compte ces effets physiques et qui se prete bien a une extraction de parametres rapide et facile, est adopte. Cette derniere etude est concretisee par la mise au point et la programmation d'un banc de caracterisation en continu. Une structure d'amplificateur operationnel est etudiee et realisee dans une technologie cmos reduite. Enfin, les consequences des petites dimensions sur les performances de cet amplificateur operationnel sont evaluees.
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Santos, Filipe de Andrade Tabarani. "Projeto de amplificadores com realimentação em corrente utilizando tecnologia 0,35 µm CMOS." [s.n.], 2011. http://repositorio.unicamp.br/jspui/handle/REPOSIP/262023.
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Orientador: Carlos Alberto dos Reis FilhoDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
Made available in DSpace on 2018-08-19T10:35:49Z (GMT). No. of bitstreams: 1 Santos_FilipedeAndradeTabarani_M.pdf: 11362655 bytes, checksum: 2e42c97ddd2bc2cb397c41f31568dc37 (MD5) Previous issue date: 2011
Resumo: Este trabalho apresenta o estudo aprofundado e a confecção de amplificadores realimentados por corrente (CFA). São analisadas as principais características de um CFA e comparado com o amplificador realimentado por tensão (VOA). Buscou-se esclarecer as aplicações nas quais a primeira célula apresenta-se como melhor alternativa e como importante ferramenta a ser disponibiliza aos projetistas. Ao longo desta analise são frisadas as principais dificuldades na implementação da célula em tecnologia CMOS mencionando as soluções encontradas pela na literatura. Estas dificuldades impedem a confecção de CFAs CMOS comerciais. Um dos principais problemas da implementação de amplificadores realimentados por corrente em tecnologia CMOS e a baixa transcondutância dos transistores. A literatura propõe contornar esta deficiência da tecnologia utilizando células que obtêm alta transcondutância através do uso de realimentação interna [1]. Entretanto, a topologia proposta possui um severo compromisso entre transcondutância e banda de freqüência. O trabalho apresentado nesta dissertação deixa sua contribuição a literatura propondo dois métodos para amenizar este compromisso, que resultam no deslocamento da freqüência de -3dB, tornando-a significantemente maior que a original. No exemplo de projeto, aqui ilustrado, foi obtida banda 3,25 vezes a original,mantendo as características DC.O projeto de duas topologias, sendo uma baseada no primeiro CFA monolítico comercializado e a outra que utiliza transistores compostos, foi realizado visando a implementação monolítica em tecnologia 0,35 ?m CMOS da fabrica Austriamicrosystems. Os protótipos fabricados foram medidos e os resultados comparados com o esperado por simulação
Abstract: This work presents the study and design of current-feedback amplifiers (CFA).It is analyzed the main characteristics of a CFA as it compares to a typical voltage feedback amplifier (VOA). It was attempted to clarify in which applications the first mentioned cell excels at and why it can serve as an important tool for the designers. Throughout the analysis, the main difficulties regarding the implementation of the cell using CMOS technology are highlighted and the solutions proposed by the literature exposed. Those characteristics restrain the conception of CMOS commercials CFAs. One of the primary obstacles for the implementation of current-feedback amplifiers using CMOS technology is the low transconductance of the transistors. The literature proposes the use of cells with internal feedback in order to solve this issue [1].However, the proposed cell has a severe trade-off between transconductance and frequency bandwidth. This work provides its contribution to the literature by proposing two methods to loosen this trade-off. Using the proposed modification, it was obtained 3.25 times the original bandwidth while maintaining all of its native DC characteristics. The design of two topologies was carried out using monolithic Austriamicrosystems0.35?m CMOS technology; one based on the topology of the first commercialized monolithic CFA and the other using compound transistors. The produced prototypes were measured and the results compared with expected by simulation
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
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Rozkopal, Tomáš. "Vliv topologie operačních zesilovačů na kvalitu audiosignálu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-318196.
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The thesis describes different between any signal and audio signal from the used amplifier´s quality point of view. There are mentioned ways of origin of distortions and their effect on the audio signal quality. There is also described in detail the principal of operational amplifier, it´s circuit realization and ways to improve the circuit topology in order to reach the best qualities. Choice of parts used for discreet realization of operational amplifier is consulted. Last but not least the thesis contents the practical part, stating the reasons for realization of operational amplifiers from discreet parts and also describing two most commonly used topologies of operational amplifiers. Their discreet version is designed and there are compared the different between the manufacturer’s data and the data measured during the simulation.
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Connor, Mark Anthony. "Design of Power-Scalable Gallium Nitride Class E Power Amplifiers." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1405437893.
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Mohamad, Isa Muammar Bin. "Low Noise Amplifiers using highly strained InGaAs/InAlAs/InP pHEMT for implementation in the Square Kilometre Array (SKA)." Thesis, University of Manchester, 2012. https://www.research.manchester.ac.uk/portal/en/theses/low-noise-amplifiers-using-highly-strained-ingaasinalasinp-phemt-for-implementation-in-the-square-kilometre-array-ska(31b6cbae-7b7e-43fe-a612-b3555dd2263d).html.
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The Square Kilometre Array (SKA) is a multibillion and a multinational science project to build the world’s largest and most sensitive radio telescope. For a very large field of view, the combined collecting area would be one square kilometre (or 1, 000, 000 square metre) and spread over more than 3,000 km wide which will require a massive count of antennas (thousands). Each of the antennas contains hundreds of low noise amplifier (LNA) circuits. The antenna arrays are divided into low, medium and high operational frequencies and located at different positions to boost up the telescope’s scanning sensitivity.The objective of this work was to develop and fabricate fully on-chip LNA circuits to meet the stringent requirements for the mid-frequency array from 0.4 GHz to 1.4 GHz of the SKA radio astronomy telescope using Monolithic Microwave Integrated Circuit technology (MMIC). Due to the number of LNA reaching figures of millions, the fabricated circuits were designed with the consideration for low cost fabrication and high reliability in the receiver chain. Therefore, a relaxed optical lithography with Lg = 1 µm was adopted for a high yield fabrication process.Towards the fulfilment of the device’s low noise characteristics, a large number of device designs, fabrication and characterisation of InGaAs/InAlAs/InP pHEMTs were undertaken. These include optimisations at each critical fabrication steps. The device’s high breakdown and very low gate leakage characteristics were further improved by a combination of judicious epitaxial growth and manipulation of materials’ energy gaps. An attempt to increase the device breakdown voltage was also employed by incorporating Field Plate structure at the gate terminal. This yielded the devices with improvements in the breakdown voltage up to 15 V and very low gate leakage of 1 µA/mm, in addition to high transconductance (gm) characteristic. Fully integrated double stage LNA had measured NF varying from 1.2 dB to 1.6 dB from 0.4 GHz to 1.4 GHz, compared with a slightly lower NF obtained from simulation (0.8 dB to 1.1 dB) across the same frequency band.These are amongst the attractive device properties for the implementation of a fully on-chip MMIC LNA circuits demonstrated in this work. The lower circuit’s low noise characteristic has been demonstrated using large gate width geometry pHEMTs, where the system’s noise resistance (Rn) has successfully reduced to a few ohms. The work reported here should facilitate the successful implementation of rugged low noise amplifiers as required by SKA receivers.
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Aurangabadkar, Nilesh Kirti Kumar. "Simulations of analog circuit building blocks based on radiation and temperature-tolerant SIC JFET Technologies." Master's thesis, Mississippi State : Mississippi State University, 2003. http://library.msstate.edu/etd/show.asp?etd=etd-05162003-114102.
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Banerjee, Aritra. "Design of digitally assisted adaptive analog and RF circuits and systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/52919.
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With more and more integration of analog and RF circuits in scaled CMOS technologies, process variation is playing a critical role which makes it difficult to achieve all the performance specifications across all the process corners. Moreover, at scaled technology nodes, due to lower voltage and current handling capabilities of the devices, they suffer from reliability issues that reduce the overall lifetime of the system. Finally, traditional static style of designing analog and RF circuits does not result in optimal performance of the system. A new design paradigm is emerging toward digitally assisted analog and RF circuits and systems aiming to leverage digital correction and calibration techniques to detect and compensate for the manufacturing imperfections and improve the analog and RF performance offering a high level of integration. The objective of the proposed research is to design digital friendly and performance tunable adaptive analog/RF circuits and systems with digital enhancement techniques for higher performance, better process variation tolerance, and more reliable operation and developing strategy for testing the proposed adaptive systems. An adaptation framework is developed for process variation tolerant RF systems which has two parts – optimized test stimulus driven diagnosis of individual modules and power optimal system level tuning. Another direct tuning approach is developed and demonstrated on a carbon nanotube based analog circuit. An adaptive switched mode power amplifier is designed which is more digital-intensive in nature and has higher efficiency, improved reliability and better process resiliency. Finally, a testing strategy for adaptive RF systems is shown which reduces test time and test cost compared to traditional testing.
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Kšica, Radim. "Návrh operačního zesilovače s proudovou zpětnou vazbou." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218578.
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This Master`s thesis deals with properties of current feedback operational amplifier. The main goal of this work is creation design process of current feedback operational amplifier by using CMOS technology AMIS 0,7 µm. Next goal of this work is attestation of funciton our design process. Last goal is creation the datasheet of our amplifier.
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Jha, Nand Kishore. "Design of a complementary silicon-germanium variable gain amplifier." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24614.
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Ahmad, Norhawati Binti. "Modelling and design of Low Noise Amplifiers using strained InGaAs/InAlAs/InP pHEMT for the Square Kilometre Array (SKA) application." Thesis, University of Manchester, 2012. https://www.research.manchester.ac.uk/portal/en/theses/modelling-and-design-of-low-noise-amplifiers-using-strained-ingaasinalasinp-phemt-for-the-square-kilometre-array-ska-application(b2b50fd8-0a13-4f71-b3f0-616ee4b2a82b).html.
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The largest 21st century radio telescope, the Square Kilometre Array (SKA) is now being planned, and the first phase of construction is estimated to commence in the year 2016. Phased array technology, the key feature of the SKA, requires the use of a tremendous number of receivers, estimated at approximately 37 million. Therefore, in the context of this project, the Low Noise Amplifier (LNA) located at the front end of the receiver chain remains the critical block. The demanding specifications in terms of bandwidth, low power consumption, low cost and low noise characteristics make the LNA topologies and their design methodologies one of the most challenging tasks for the realisation of the SKA. The LNA design is a compromise between the topology selection, wideband matching for a low noise figure, low power consumption and linearity. Considering these critical issues, this thesis describes the procedure for designing a monolithic microwave integrated circuit (MMIC) LNA for operation in the mid frequency band (400 MHz to 1.4 GHz) of the SKA. The main focus of this work is to investigate the potential of MMIC LNA designs based on a novel InGaAs/InAlAs/InP pHEMT developed for 1 µm gate length transistors, fabricated at The University of Manchester. An accurate technique for the extraction of empirical linear and nonlinear models for the fabricated active devices has been developed. In addition to the linear and nonlinear model of the transistors, precise models for passive devices have also been obtained and incorporated in the design of the amplifiers. The models show excellent agreement between measured and modelled DC and RF data. These models have been used in designing single, double and differential stage MMIC LNAs. The LNAs were designed for a 50 Ω input and output impedance. The excellent fits between the measured and modelled S-parameters for single and double stage single-ended LNAs reflects the accurate models that have been developed. The single stage LNA achieved a gain ranging from 9 to 13 dB over the band of operation. The gain was increased between 27 dB and 36 dB for the double stage and differential LNA designs. The measured noise figures obtained were higher by ~0.3 to ~0.8 dB when compared to the simulated figures. This is due to several factors which are discussed in this thesis. The single stage design consumes only a third of the power (47 mW) of that required for the double stage design, when driven from a 3 V supply. All designs were unconditionally stable. The chip sizes of the fabricated MMIC LNAs were 1.5 x 1.5 mm2 and 1.6 x 2.5 mm2 for the single and double stage designs respectively. Significantly, a series of differential input to single-ended output LNAs became of interest for use in the Square Kilometre Array (SKA), as it utilises differential output antennas in some of its configurations. The single-ended output is preferable for interfacing to the subsequent stages in the analogue chain. A noise figure of less than 0.9 dB with a power consumption of 180 mW is expected for these designs.
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Rujzl, Miroslav. "Analýza a obvodové realizace speciálních chaotických systémů." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2021. http://www.nusl.cz/ntk/nusl-442418.
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This master‘s thesis deals with analysis of electronic dynamical systems exhibiting chaotic solution. In introduction, some basic concepts for better understanding of dynamical systems are explained. After introduction, current knowledge from the world of circuits exhibiting chaotic solutions are discussed. The best-known chaotic systems are analyzed numerically in Matlab software. Numerical analysis and experimental verification were demonstrated at C class transistor amplifier, which confirmed the chaotic behavior and generation of a strange attractor.
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Giry, Alexandre. "Étude des potentialités des technologies CMOS avancées pour les radiofréquences : application aux amplificateurs de puissance." Grenoble INPG, 2001. http://www.theses.fr/2001INPG0057.
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Gillet, Vincent. "Développement d'un banc de load-pull actif innovant, utilisant un signal multi-tons large bande pour la mesure de la linéarité (EVM, NPR, ACPR) des dispositifs actifs." Thesis, Limoges, 2019. http://www.theses.fr/2019LIMO0114.
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Cette thèse présente l’utilisation innovante du signal Unequally Spaced Multi-Tones (USMT) dans la mesure de linéarité des transmetteurs de télécommunications (5G). Ce signal offre une nouvelle perspective permettant la caractérisation des formes d’ondes réelles en utilisant un signal avec un nombre de tons très réduit, se comportant comme une extension de la caractérisation 2-tons. Ce signal est simple à mettre en oeuvre, à mesurer et à analyser. Il nécessite des moyens peu onéreux, (générateur de signaux arbitraires, analyseur de spectre). Il peut s’utiliser à différent niveau de l’industrie : de la fabrication (wafer) jusqu’à la ligne de production, en passant par les transistors packagés. Cette thèse a démontré la faisabilité d’un banc automatique de mesures multi-tons, utilisant ce signal USMT, pour la caractérisation load-pull (passif et actif ) de transmetteurs de télécommunications. La maîtrise de cette technique de mesure des non-linéarités représente un avantage concurrentiel à tous les niveaux de la conception du front-end radio fréquence et un gain financier indéniableThis manuscript describes an innovative use of the Unequally Spaced Multi-Tones test signal to achieve linearity characterization of telecommunication transmitter (5G). This signal offers new perspectives of characterization using real waveform involving a reduce number of tone test signal, which in turn behaves as an extension of the 2- tone characterization. This innovative test signal is easy to generate, to measure and to analyze. It required not particular expensive hardware to be generated (arbitrary waveform generator, spectrum analyzer). It is particularly interesting for production line testing, from on-wafer measurements up to radiofrequency front-end, passing through packaged transistor. This thesis demonstrated the feasability of automation of multitone measurement, using this particular USMT signal, for load-pull measurement (passive and active) of telecommunications transmitters. Managing this measurement technics represents a competitive advantage at all levels of the radio frequency front-end design and an undeniable financial gain
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Capovilla, Carlos Eduardo. "Circuitos integrados de radio-recepção para a operação de multiplexação espacial de antenas em tempo real." [s.n.], 2008. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260964.
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Orientador: Luiz Carlos KretlyTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Esta pesquisa tem por objetivo a concepção de novas topologias de circuitos integrados e suas caracterizações para operação em sistemas de rádio-recepção. O projeto e a fabricação de chaves de RF, LNAs, mixer e VCOs são apresentados. A técnica SMILE (Spatial MultIplexing ofLocal Elements) foi adotada devido às suas vantagens e funcionalidade para a otimização física de antenas inteligentes. Essa técnica requer um chaveamento sequencial das antenas do arranjo e para tal foi desenvolvido um controle de chaveamento acionado por um VCO digital. A demultiplexação analógica do sinal é implementada através de um OTA e chaves analógicas diferenciais. Assim, além da introdução de novas topologias de circuitos integrados, este trabalho estabelece procedimentos de projeto e simulação associados à validação dos dispositivos fabricados. Palavras-chave: circuitos integrados, rádio-recepção, antenas inteligentes, SMILE
Abstract: This research aims the conception of new topologies of integrated circuits and its characterizations for operation in radio-receiver systems. The design and fabrication of RF switches, LNAs, mixer, and VCOs are presented. The SMILE - Spatial MultIplexing of Local Elements - technique was adopted due to its advantages and functionality for the intelligent antennas physical optimization. This technique requires a sequential switching of the antennas and for this purpose a switch driver with a digital VCO was developed. The analog demultiplexation of the signal is implemented with OTA and differential analog switches. Thus, besides the introduction of new integrated circuit topologies, this work establishes procedures of design and simulation together with the manufactured devices validation. Keywords: integrated circuits, radio-reception, smart antennas, SMILE
Doutorado
Eletrônica, Microeletrônica e Optoeletrônica
Doutor em Engenharia Elétrica
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Novotný, Jakub. "Behaviorální modely aktivních prvků s nezávislým víceparametrovým elektronickým řízením." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-241053.
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This thesis is focused on behavioral modelling of active elements with independent multi-parameter electronic control using comercially available components. In a first part of the thesis, CVDIBA, CVDOBA, CVCC and OC elements are discussed. The functionality is verified by simulations using OrCAD PSpice. Used components are diamond transistor OPA860, variable gain amplifier LMH6505, differencing amplifier AD830, low distortion differential driver AD8138, current conveyor EL2082 and current mode four quadrant multiplier EL4083. Four active elements are further built on PCB and measured. Some applications like low pass filter, high pass filter, all pass filter and reconfigurable filter.
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FALEH, MOHAMAD SALEH. "Conception, realisation et caracterisation de transistors bipolaires de puissance a heterojonction gainp/gaas et comparaison avec les tbh's gaalas/gaas." Toulouse 3, 1998. http://www.theses.fr/1998TOU30027.
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L'objet de cette these est la conception, la realisation et la caracterisation de transistors bipolaires de puissance a heterojonction gainp/gaas et la comparaison avec les tbhs gaalas/gaas. Le premier chapitre presente d'abord un rappel des principales proprietes des materiaux gainp et gaas utilises dans la fabrication des tbh etudies. Il examine ensuite les parametres physiques et technologiques qui influent sur les performances statiques et dynamiques. Un modele electrique petit signal permettant la description precise du comportement du transistor est presente. L'influence des effets thermiques qui constituent la principale limitation des tbhs de puissance sur arseniure de gallium est enfin analysee. La technologie mise en oeuvre pour realiser les tbhs gainp/gaas est decrite dans le deuxieme chapitre. Deux familles de dispositifs presentant une surface d'emetteur elementaire de 10x200 m#2 et 6x60 m#2 sont realisees dans des technologies triple mesa classique ou autoalignee, avec une prise du contact d'emetteur utilisant un pont a air. Le troisieme chapitre rapporte les resultats des caracterisations statique et dynamique ainsi que les performances des transistors realises. L'analyse des mecanismes qui regissent le courant principal d'electrons dans la structure permet de proposer une nouvelle caracterisation de la discontinuite de la bande de conduction e#c=17016 mev dans l'heterojonction ga#0#. #5in#0#. #5p/gaas. La caracterisation du comportement electrothermique, avec notamment l'identification de la resistance thermique et l'etude du gain en courant qui depend du niveau d'injection, a permis d'interpreter un comportement specifique de nos transistors. Les performances obtenues pour les transistors classiques sont f#t=18 ghz, f#m#a#x=20 ghz, et la reduction de la resistance de base par autoalignement du contact de base sur l'emetteur a conduit au doublement de la frequence maximale d'oscillation (f#m#a#x=42ghz). Pour l'application a l'amplification de puissance, il a ete releve a une frequence de 1ghz une puissance r. F de sortie de l'ordre de 1w avec un rendement en puissance ajoutee de 49% et a 10ghz, une puissance et un rendement de 170mw et 29% respectivement.
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Janse, van Rensburg Christo. "A SiGe BiCMOS LNA for mm-wave applications." Diss., University of Pretoria, 2012. http://hdl.handle.net/2263/26501.
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A 5 GHz continuous unlicensed bandwidth is available at millimeter-wave (mm-wave) frequencies around 60 GHz and offers the prospect for multi gigabit wireless applications. The inherent atmospheric attenuation at 60 GHz due to oxygen absorption makes the frequency range ideal for short distance communication networks. For these mm-wave wireless networks, the low noise amplifier (LNA) is a critical subsystem determining the receiver performance i.e., the noise figure (NF) and receiver sensitivity. It however proves challenging to realise high performance mm-wave LNAs in a silicon (Si) complementary metal-oxide semiconductor (CMOS) technology. The mm-wave passive devices, specifically on-chip inductors, experience high propagation loss due to the conductivity of the Si substrate at mm-wave frequencies, degrading the performance of the LNA and subsequently the performance of the receiver architecture. The research is aimed at realising a high performance mm-wave LNA in a Si BiCMOS technology. The focal points are firstly, the fundamental understanding of the various forms of losses passive inductors experience and the techniques to address these issues, and secondly, whether the performance of mm-wave passive inductors can be improved by means of geometry optimising. An associated hypothesis is formulated, where the research outcome results in a preferred passive inductor and formulates an optimised passive inductor for mm-wave applications. The performance of the mm-wave inductor is evaluated using the quality factor (Q-factor) as a figure of merit. An increased inductor Q-factor translates to improved LNA input and output matching performance and contributes to the lowering of the LNA NF. The passive inductors are designed and simulated in a 2.5D electromagnetic (EM) simulator. The electrical characteristics of the passive structures are exported to a SPICE netlist which is included in a circuit simulator to evaluate and investigate the LNA performance. Two LNAs are designed and prototyped using the 13μ-m SiGe BiCMOS process from IBM as part of the experimental process to validate the hypothesis. One LNA implements the preferred inductor structures as a benchmark, while the second LNA, identical to the first, replaces one inductor with the optimised inductor. Experimental verification allows complete characterization of the passive inductors and the performance of the LNAs to prove the hypothesis. According to the author's knowledge, the slow-wave coplanar waveguide (S-CPW) achieves a higher Q-factor than microstrip and coplanar waveguide (CPW) transmission lines at mm-wave frequencies implemented for the 130 nm SiGe BiCMOS technology node. In literature, specific S-CPW transmission line geometry parameters have previously been investigated, but this work optimises the signal-to-ground spacing of the S-CPW transmission lines without changing the characteristic impedance of the lines. Optimising the S-CPW transmission line for 60 GHz increases the Q-factor from 38 to 50 in simulation, a 32 % improvement, and from 8 to 10 in measurements. Furthermore, replacing only one inductor in the output matching network of the LNA with the higher Q-factor inductor, improves the input and output matching performance of the LNA, resulting in a 5 dB input and output reflection coefficient improvement. Although a 5 dB improvement in matching performance is obtained, the resultant noise and gain performance show no significant improvement. The single stage LNAs achieve a simulated gain and NF of 13 dB and 5.3 dB respectively, and dissipate 6 mW from the 1.5 V supply. The LNA focused to attain high gain and a low NF, trading off linearity and as a result obtained poor 1 dB compression of -21.7 dBm. The LNA results are not state of the art but are comparable to SiGe BiCMOS LNAs presented in literature, achieving similar gain, NF and power dissipation figures.Dissertation (MEng)--University of Pretoria, 2012.
Electrical, Electronic and Computer Engineering
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Weststrate, Marnus. "LC-ladder and capacitive shunt-shunt feedback LNA modelling for wideband HBT receivers." Thesis, University of Pretoria, 2011. http://hdl.handle.net/2263/26615.
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Although the majority of wireless receiver subsystems have moved to digital signal processing over the last decade, the low noise amplifier (LNA) remains a crucial analogue subsystem in any design being the dominant subsystem in determining the noise figure (NF) and dynamic range of the receiver as a whole. In this research a novel LNA configuration, namely the LC-ladder and capacitive shunt-shunt feedback topology, was proposed for use in the implementation of very wideband LNAs. This was done after a thorough theoretical investigation of LNA configurations available in the body of knowledge from which it became apparent that for the most part narrowband LNA configurations are applied to wideband applications with suboptimal results, and also that the wideband configurations that exist have certain shortcomings. A mathematical model was derived to describe the new configuration and consists of equations for the input impedance, input return loss, gain and NF, as well as an approximation of the worst case IIP3. Compact design equations were also derived from this model and a design strategy was given which allows for electronic design automation of a LNA using this configuration. A process for simultaneously optimizing the circuit for minimum NF and maximum gain was deduced from this model and different means of improving the linearity of the LNA were given. This proposed design process was used successfully throughout this research. The accuracy of the mathematical model has been verified using simulations. Two versions of the LNA were also fabricated and the measured results compared well with these simulations. The good correlation found between the calculated, simulated and measured results prove the accuracy of the model, and some comments on how the accuracy of the model could be improved even further are provided as well. The simulated results of a LNA designed for the 1 GHz to 18 GHz band in the IBM 8HP process show a gain of 21.4 dB and a minimum NF of only 1.7 dB, increasing to 3.3 dB at the upper corner frequency while maintaining an input return loss below -10 dB. After steps were taken to improve the linearity, the IIP3 of the LNA is -14.5 dBm with only a small degradation in NF now 2.15 dB at the minimum. The power consumption of the respective LNAs are 12.75 mW and 23.25 mW and each LNA occupies a chip area of only 0.43 mm2. Measured results of the LNA fabricated in the IBM 7WL process had a gain of 10 dB compared to an expected simulated gain of 20 dB, however significant path loss was introduced by the IC package and PCB parasitics. The S11 tracked the simulated response very well and remained below -10 dB over the feasible frequency range. Reliable noise figure measurements could not be obtained. The measured P1dB compression point is -22 dBm. A 60 GHz LNA was also designed using this topology in a SiGe process with ƒT of 200 GHz. A simulated NF of 5.2 dB was achieved for a gain of 14.2 dB and an input return loss below -15 dB using three amplifier stages. The IIP3 of the LNA is -8.4 dBm and the power consumption 25.5 mW. Although these are acceptable results in the mm-wave range it was however found that the wideband nature of this configuration is redundant in the unlicensed 60 GHz band and results are often inconsistent with the design theory due to second order effects. The wideband results however prove that the LC-ladder and capacitive shunt-shunt feedback topology is a viable means for especially implementing LNAs that require a very wide operating frequency range and also very low NF over that range.Thesis (PhD(Eng))--University of Pretoria, 2011.
Electrical, Electronic and Computer Engineering
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Akhtar, Siraj. "Modeling of RF power transistors for power amplifier design /." The Ohio State University, 2000. http://rave.ohiolink.edu/etdc/view?acc_num=osu1488196781733682.
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Overstreet, William Patton. "VHF bipolar transistor power amplifiers: measurement, modeling, and design." Diss., Virginia Polytechnic Institute and State University, 1986. http://hdl.handle.net/10919/71166.
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Widely used design techniques for radio frequency power amplifiers yield results which are approximate; the initial design is usually refined by applying trial-and-error procedures in the laboratory. More accurate design techniques are complicated in their application and have not gained acceptance by practicing engineers. A new design technique for VHF linear power amplifiers using bipolar junction transistors is presented in this report. This design technique is simple in its application but yields accurate results.
The design technique is based upon a transistor model which is simple enough to be useful for design, but which is sufficiently accurate to predict performance at high frequencies. Additionally, the model yields insight into many of the processes which take place within the typical RF power transistor. The fundamental aspect of the model is the inclusion of charge storage within the transistor base. This charge storage effect gives rise to a nearly sinusoidal collector current waveform, even in a transistor which ostensibly is biased for class B or nonsaturating class C operation.
Methods of predicting transistor input and output impedances are presented. A number of other topics related to power amplifier measurement and design are also included. A unique measurement approach which is ideally suited for use with power amplifiers is discussed. This measurement approach is a hybrid of the common S-parameter measurement technique and the "load-pull" procedure. Practical considerations such as amplifier stability, bias network design, and matching network topology are also included in the report.Ph. D.
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Dupuy, Jean-Yves. "Théorie et Pratique de l'Amplificateur Distribué : Application aux Télécommunications Optiques à 100 Gbit/s." Thesis, Cergy-Pontoise, 2015. http://www.theses.fr/2015CERG0759/document.
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La théorie, la conception, l'optimisation et la caractérisation d'amplificateurs distribués en technologie TBDH InP 0,7 µm, pour les systèmes de communications optiques à 100 Gbit/s, sont présentés. Nous montrons comment l'exploitation adaptée du concept d'amplificateur distribué avec une technologie de transistors bipolaires à produit vitesse-amplitude élevé a permis la réalisation d'un driver de modulateur électro-optique fournissant une amplitude différentielle d'attaque de 6,2 et 5,9 Vpp, à 100 et 112 Gbit/s, respectivement, avec une qualité de signal élevée. Ce circuit établit ainsi le record de produit vitesse-amplitude à 660 Gbit/s.V sur tranche et 575 Gbit/s.V en module hyperfréquence. Dans le cadre du projet Européen POLYSYS, il a été associé à un laser accordable et un modulateur pour la réalisation d'un module transmetteur optoélectronique compact, démontrant des performances avançant l'état de l'art des communications optiques courtes distances à 100 Gbit/sThe theory, design, optimisation and characterisation of distributed amplifiers in 0.7-µm InP DHBT technology, for 100-Gbit/s optical communication systems, are presented. We show how the appropriate implementation of the distributed amplifier concept in a bipolar transistors technology with high swing-speed product has enabled the realisation of an electro-optic modulator driver with 6.2- and 5.9-Vpp differential driving amplitude at 100 and 112 Gb/s, respectively, with a high signal quality. This circuit thus establishes the swing-speed product record at 660 Gb/s.V on wafer and at 575 Gb/s.V in a microwave module. In the frame of the European project POLYSYS, it has been co-packaged with a tunable laser and a modulator to realise a compact optoelectronic transmitter module, which has demonstrated performances advancing the state of the art of short reach 100-Gb/s optical communications
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Raghavan, Arvind. "Bipolar large-signal modeling and power amplifier design." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/13294.
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Chunda, Jaime P. "Low voltage operational amplifier using parasitic bipolar transistors in CMOS." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1995. http://handle.dtic.mil/100.2/ADA303882.
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Kashif, Ahsan-Ullah. "Optimization of LDMOS Transistor in Power Amplifiers for Communication Systems." Doctoral thesis, Linköpings universitet, Halvledarmaterial, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-61599.
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The emergence of new communication standards has put a key challenge for semiconductor industry to develop RF devices that can handle high power and high data rates simultaneously. The RF devices play a key role in the design of power amplifiers (PAs), which is considered as a heart of base-station. From economical point of view, a single wideband RF power module is more desirable rather than multiple narrowband PAs especially for multi-band and multi-mode operation. Therefore, device modeling has now become much more crucial for such applications. In order to reduce the device design cycle time, the researchers also heavily rely on computer aided design (CAD) tools. With improvement in CAD technology the model extraction has become more accurate and device physical structure optimization can be carried out with less number of iterations. LDMOS devices have been dominating in the communication field since last decade and are still widely used for PA design and development. This thesis deals with the optimization of RFLDMOS transistor and its evaluation in different PA classes, such as linear, switching, wideband and multi-band applications. For accurate evaluation of RF-LDMOS transistor parameters, some techniques are also developed in technology CAD (TCAD) using large signal time domain computational load-pull (CLP) methods. Initially the RF-LDMOS is studied in TCAD for the improved RF performance. The physical intrinsic structure of RF-LDMOS is provided by Infenion Technologies AG. A reduced surface field (RESURF) of low-doped drain (LDD) region is considered in detail because it plays an important role in RF-LDMOS devices to obtain high breakdown voltage (BVDS). But on the other hand, it also reduces the RF performance due to high on-resistance (Ron). The excess interface state charges at the RESURF region are introduced to reduce the Ron, which not only increases the dc drain current, but also improve the RF performance in terms of power, gain and efficiency. The important achievement is the enhancement in operating frequency up to 4 GHz. In LDD region, the effect of excess interface charges at the RESURF is also compared with dual implanted-layer of p-type and n-type. The comparison revealed that the former provides 43 % reduction in Ron with BVDS of 70 V, while the later provides 26 % reduction in Ron together with BVDS of 64 - 68 V. In the second part of my research work, computational load pull (CLP) simulation technique is used in TCAD to extract the impedances of RF-LDMOS at different frequencies under large signal operation. Flexible matching is an issue in the design of broadband or multi-band PAs. Optimum impedance of RF-LDMOS is extracted at operating frequencies of 1, 2 and 2.5 GHz in class AB PA. After this, CLP simulation technique is further developed in TCAD to study the non-linear behavior of RF devices. Through modified CLP technique, non-linear effects inside the transistor structure are studied by conventional two-tone RF signals in time domain. This is helpful to detect and understand the phenomena, which can be resolved to improve the device performance. The third order inter-modulation distortion (IMD3) of RF- LDMOS was observed at different power levels. The IMD3 of −22 dBc is obtained at 1-dB compression point (P1-dB), while at 10 dB back off the value increases to −36 dBc. These results were also verified experimentally by fabricating a linear PA. Similarly, CLP technique is developed further for the analysis of RF devices in high efficiency operation by investigating the odd harmonic effects for the design of class-F PA. RF-LDMOS can provide a power added efficiency (PAE) of 81.2 % in class-F PA at 1 GHz in TCAD simulations. The results are verified by design and fabrication of class-F PA using large signal model of the similar device in ADS. In fabrication, a PAE of 76 % is achieved.
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Smithers, Colin R. "Linear and efficient bipolar transistor RF amplifiers using envelope feedback." Thesis, University of Surrey, 1985. http://epubs.surrey.ac.uk/843097/.
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After an introduction to amplifiers in communications and an exposition of the literature specifically relevant to high linearity power amplifiers, this study investigates more thoroughly various aspects of envelope feedback as applied to Bipolar Tuned Power Amplifiers at HF and VHP. It is discovered that under the correct conditions a new mode of linear operation exists where gain compression, AM-PM conversion and input impedance are simultaneously linearised, and in this region DC-RF power efficiency is also improved. Spectral measurements are presented from an envelope feedback amplifier constructed to operate over this region. A computerised system is described for measuring accurately the gain and phase shift of the test amplifier against variation of collector supply, quiescent bias current and RF drive power. The results from these measurements are presented as 3-dimensional projections and as contour plots. Subsequently the stored data is used to re-construct two-tone spectra, which is then analysed to show contributions to the spectrum from the gain compression and AM-PM conversion mechanisms separately. Conclusions are drawn with respect to effects of bias on these two mechanisms. A mechanism has been discovered which gives a symetric spectra without requiring AM-PM conversion at the fundamental frequencies. An attempt is made to model the amplifier with a non-linear circuit transient analysis program (SPICE). Good correlation is obtained for some parameters and these results are also plotted in 3-D and in contour.
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Barradas, Filipe Miguel Esturrenho. "RF parametric amplifiers." Master's thesis, Universidade de Aveiro, 2012. http://hdl.handle.net/10773/10198.
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Mestrado em Engenharia Electrónica e TelecomunicaçõesRecentemente tem-se feito um esforço no sentido de aumentar a eficiência em aplicadores de RF, no entanto, o transístor é um dispositivo intrinsecamente ineficiente. Utilizando amplificadores paramétricos pode-se teoricamente chegar a 100% de eficiência mesmo operando em modo linear. A razão desta elevada eficiência é o dispositivo activo utilizado, já que os amplificadores paramétricos utilizam uma reactância controlada, que não consome potência. Esta mudança de elemento activo modifica completamente o princípio de funcionamento dos amplificadores. Neste trabalho este tipo de amplificação é estudado, relações e transformações conhecidas são examinadas primeiro para obter propriedades limite gerais. Depois é feita análise de pequeno sinal para se obterem outras características importantes. Finalmente, um novo modelo de grande sinal é derivado e apresentado. Este modelo é capaz de prever algumas características do amplificador, tal como o AM/AM. Utilizando o modelo de grande sinal apresentado projecta-se um amplificador, sendo este posteriormente simulado.
In recent years a significant effort has been made towards efficiency increase in RF amplifiers. The transistor is, however, an intrinsically inefficient device. Parametric amplification can theoretically be 100% efficient even operating in linear mode. The reason behind this efficiency is the active device. These amplifiers forget the transistor to use a controlled reactance, which cannot consume power. This switch in active element changes the whole principle of operation of the amplifiers. In this work this type of amplification is studied. Known relations and transformations are first examined to obtain general limit properties of the used elements. Then small-signal analysis is performed to obtain other important characteristics. Finally, a novel large signal model is developed and presented. This model is capable of accurately predicting the non-linear responses of the amplifier, such as the AM/AM. Using the presented large-signal model, an amplifier is designed and simulated.
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Ross, Kyle Gene. "Distributed amplifier circuit design using a commercial CMOS process technology." Thesis, Montana State University, 2006. http://etd.lib.montana.edu/etd/2006/ross/RossK0806.pdf.
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Bengtsson, Olof. "Design and Characterization of RF-Power LDMOS Transistors." Doctoral thesis, Uppsala : University Library, Universitetsbiblioteket, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-9259.
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Dai, Wenhua. "Large signal electro-thermal LDMOSFET modeling and the thermal memory effects in RF power amplifiers." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1078935135.
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Thesis (Ph. D.)--Ohio State University, 2004.Title from first page of PDF file. Document formatted into pages; contains xix, 156 p.; also includes graphics (some col.). Includes bibliographical references (p. 152-156).
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Varanasi, Ravi Kumar. "Linearity optimization of power transistors utilizing harmonic terminations." [Tampa, Fla.] : University of South Florida, 2004. http://purl.fcla.edu/fcla/etd/SFE0000563.
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Iwamoto, Masaya. "Linearity characteristics of InGaP/GaAs heterojunction bipolar transistors and power amplifiers /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3091212.
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O'Sullivan, Tomás. "Design of millimeter-wave power amplifiers using InP heterojunction bipolar transistors." Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p3368992.
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Thesis (Ph. D.)--University of California, San Diego, 2009.Title from first page of PDF file (viewed September 17, 2009). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 118-123).