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Journal articles on the topic 'Transistor modelling'

Author: Grafiati

Published: 4 June 2021

Last updated: 5 February 2022

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1

Shuib, Umar Faruk, Khairul Anuar Mohamad, Afishah Alias, Tamer A. Tabet, Bablu K. Gosh, and Ismail Saad. "Modelling and Simulation Approach for Organic Thin-Film Transistors Using MATLAB Simulation." Advanced Materials Research 1107 (June 2015): 514–19. http://dx.doi.org/10.4028/www.scientific.net/amr.1107.514.

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As organic transistors are preparing to make improvements towards flexible and low cost electronics applications, the analytical models and simulation methods were demanded to predict the optimized performance and circuit design. In this paper, we investigated the analytical model of an organic transistor device and simulate the output and transfer characteristics of the device using MATLAB tools for different channel length (L) of the organic transistor. In the simulation, the Pool-Frenkel mobility model was used to represent the conductive channel of organic transistor. The different channel length has been simulated with the value of 50 μm, 10 μm and 5 μm. This research paper analyses the performance of organic thin film transistor (TFT) for top contact bottom gate device. From the simulation, drain current of organic transistor was increased as the channel length decreased. Other extraction value such sub-threshold and current on/off ratio is 0.41 V and 21.1 respectively. Thus, the simulation provides significant extraction of information about the behaviour of the organic thin film transistor.

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2

Fischer, Th, T. Nirschl, B. Lemaitre, and D. Schmitt-Landsiedel. "Modelling of the parametric yield in decananometer SRAM-Arrays." Advances in Radio Science 4 (September 6, 2006): 281–85. http://dx.doi.org/10.5194/ars-4-281-2006.

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Abstract. In today's decananometer (90 nm, 65 nm, ...), CMOS technologies variations of device parameters play an ever more important role. Due to the demand for low leakage systems, supply voltage is decreased on one hand and the transistor threshold voltage is increased on the other hand. This reduces the overdrive voltage of the transistors and leads to decreasing read and write security margins in static memories (SRAM). In addition, smaller dimensions of the devices lead to increasing variations of the device parameters, thus mismatch effects increase. It can be shown that local variations of the transistor parameters limit the functionality of circuits stronger than variations on a global scale or hard defects. We show a method to predict the yield for a large number of SRAM devices without time consuming Monte Carlo simulations in dependence of various parameters (Vdd, temperature, technology options, transistor dimensions, ...). This helps the designer to predict the yield for various system options and transistor dimensions, to choose the optimal solution for a specific product.

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3

Doja, M. N., Moinuddin, and Umesh Kumar. "High Speed Non-Linear Circuit Simulation of Bipolar Junction Transistors." Active and Passive Electronic Components 22, no. 1 (1999): 51–73. http://dx.doi.org/10.1155/1999/58424.

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This paper presents HIBTRA (High Speed Bipolar Transistor Analysis), a high speed non-linear bipolar transistor circuit simulation package. The paper discusses about the modelling of Bipolar Junction Transistor operated at high speed in the sinusoidal small signal and the transient region of operations. The package uses a high frequency model non-linear circuit elements for accurate analysis. The package also uses transistor's lumped circuit model to calculate devices electrical parameters, and it also does dynamic simulation. It also includes the conventional model as a special case. Model verification has also been done by simulation.

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4

AFZALI-KUSHAA, A., and M. EL-NOKALI. "Modelling the MOS transistor." International Journal of Electronics 74, no. 2 (February 1993): 213–29. http://dx.doi.org/10.1080/00207219308925828.

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5

Ahmad, Norhawati, S. S. Jamuar, M. Mohammad Isa, Siti Salwa Mat Isa, Muhammad Mahyiddin Ramli, N. Khalid, N. I. M. Nor, Shahrir Rizal Kasjoo, Sohiful Anuar Zainol Murad, and M. Missous. "Extrinsic and Intrinsic Modeling of InGaAs/InAlAs pHEMT for Wireless Applications." Applied Mechanics and Materials 815 (November 2015): 369–73. http://dx.doi.org/10.4028/www.scientific.net/amm.815.369.

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This paper presents the linear modelling of high breakdown InP pseudomorphic High Electron Mobility Transistors (pHEMT) that have been developed and fabricated at the University of Manchester (UoM) for low noise applications mainly for the Square Kilometre Array (SKA) project. The ultra-low leakage properties of a novel InGaAs/InAlAs/InP pHEMTs structure were used to fabricate a series of transistor with total gate width ranging from 0.2 mm to 1.2 mm. The measured DC and S-Parameters data from the fabricated devices were then used for the transistors’ modelling. The transistors demonstrated to operate up to frequencies of 25 GHz. These transistors models are used in the design of Low Noise Amplifiers (LNAs) using fully Monolithic Microwave Integrated Circuit (MMIC) technology.

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6

Daniel, M., M. Janicki, W. Wroblewski, A. Dybko, Z. Brzozka, and A. Napieralski. "Ion selective transistor modelling for behavioural simulations." Water Science and Technology 50, no. 11 (December 1, 2004): 115–23. http://dx.doi.org/10.2166/wst.2004.0679.

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Computer aided design and simulation of complex silicon microsystems oriented for environment monitoring requires efficient and accurate models of ion selective sensors, compatible with the existing behavioural simulators. This paper concerns sensors based on the back-side contact Ion Sensitive Field Effect Transistors (ISFETs). The ISFETs with silicon nitride gate are sensitive to hydrogen ion concentration. When the transistor gate is additionally covered with a special ion selective membrane, selectivity to other than hydrogen ions can be achieved. Such sensors are especially suitable for flow analysis of solutions containing various ions. The problem of ion selective sensor modelling is illustrated here on a practical example of an ammonium sensitive membrane. The membrane is investigated in the presence of some interfering ions and appropriate selectivity coefficients are determined. Then, the model of the whole sensor is created and used in subsequent electrical simulations. Providing that appropriate selectivity coefficients are known, the proposed model is applicable for any membrane, and can be straightforwardly implemented for behavioural simulation of water monitoring microsystems. The model has been already applied in a real on-line water pollution monitoring system for detection of various contaminants.

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7

Pronić-Rančić, Olivera, Zlatica Marinković, and Vera Marković. "Bias Dependant Noise Wave Modelling Procedure of Microwave Fets." Journal of Electrical Engineering 63, no. 2 (March 1, 2012): 120–24. http://dx.doi.org/10.2478/v10187-012-0018-6.

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Bias Dependant Noise Wave Modelling Procedure of Microwave Fets A new noise modelling procedure of microwave field-effect transistors (FETs) valid for various bias conditions is suggested in this paper. The proposed procedure is based on transistor noise wave model. With the aim to improve the noise wave model accuracy, the modification of the model is done by inclusion of the error correction functions into the noise wave model equations. It leads to significant reduction of deviations between measured and simulated noise parameters and therefore better noise prediction is achieved. It is also shown that once determined error correction functions can be applied for accurate noise modelling of the same device for various bias conditions. The validity of the presented noise modelling approach is exemplified by modelling of a specific MESFET device in packaged form.

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8

Hedayat, Seyed Norollah, and Seyedeh Sahar Hedayat. "Quantum Current Modelling of Single Electron Transistors with N Potential Barrier." Advanced Science, Engineering and Medicine 11, no. 12 (December 1, 2019): 1261–65. http://dx.doi.org/10.1166/asem.2019.2473.

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The single electron transistor is a new type of switching device that uses controlled electron tunneling to amplify current. In this paper, we focus on some basic device characteristics like, single electron tunneling effect on which this single electron transistor works. In this research, transmission coefficient model of a single electron transistor with quantum dot arrays constraints is checked. Then, the current of the transistor is modeled on quantum dots. Finally, current–voltage characteristic based on quantum transport and structural parameters are analyzed.

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9

Górecki, Paweł, and Krzysztof Górecki. "Modelling a Switching Process of IGBTs with Influence of Temperature Taken into Account." Energies 12, no. 10 (May 18, 2019): 1894. http://dx.doi.org/10.3390/en12101894.

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In this article the problem of modelling a switching process of Insulated Gate Bipolar Transistors (IGBTs) in the SPICE software is considered. The new form of the considered transistor model is presented. The model includes controlled voltage and current sources, resistors and voltage sources. In the model, influence of temperature on dc and dynamic characteristics of the IGBT is taken into account. A detailed description of the dynamic part of this model is included in the article and some results of experimental verification are shown. Verification is performed for a transistor IRG4PC40UD by International Rectifier. The presented results of computations and measurements show clearly influence of temperature on on-time and off-time, and additionally switching energy losses are observed. Moreover, the results of investigations performed with the use of the new model are compared to the results of computations performed with classical models of the considered device given in the literature. It is proved that the new model makes it possible to obtain a better match to the results of measurements than the considered models described in the literature.

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10

Hien, Dinh Sy, Huynh Lam Thu Thao, and Le Hoang Minh. "Modelling transport in single electron transistor." Journal of Physics: Conference Series 187 (September 1, 2009): 012060. http://dx.doi.org/10.1088/1742-6596/187/1/012060.

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11

Ghibaudo, G. "Analytical modelling of the MOS transistor." Physica Status Solidi (a) 113, no. 1 (May 16, 1989): 223–40. http://dx.doi.org/10.1002/pssa.2211130127.

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12

Litovski, V. B., J. I. Radjenovié, Ž M. Mrčarica, and S. Lj Milenkovié. "MOS transistor modelling using neural network." Electronics Letters 28, no. 18 (1992): 1766. http://dx.doi.org/10.1049/el:19921124.

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13

Bhatia, Veepsa, Neeta Pandey, and Asok Bhattacharyya. "Modelling and Design of Inverter Threshold Quantization based Current Comparator using Artificial Neural Networks." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 1 (February 1, 2016): 320. http://dx.doi.org/10.11591/ijece.v6i1.8700.

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<p>Performance of a MOS based circuit is highly influenced by the transistor dimensions chosen for that circuit. Thus, proper dimensioning of the transistors plays a key role in determining its overall performance. While choosing the dimension is critical, it is equally difficult, primarily due to complex mathematical formulations that come into play when moving into the submicron level. The drain current is the most affected parameter which in turn affects all other parameters. Thus, there is a constant quest to come up with techniques and procedure to simplify the dimensioning process while still keeping the parameters under check. This study presents one such novel technique to estimate the transistor dimensions for a current comparator structure, using the artificial neural networks approach. The approach uses Multilayer perceptrons as the artificial neural network architectures. The technique involves a two step process. In the first step, training and test data are obtained by doing SPICE simulations of modelled circuit using 0.18μm TSMC CMOS technology parameters. In the second step, this training and test data is applied to the developed neural network architecture using MATLAB R2007b.</p>

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14

Bhatia, Veepsa, Neeta Pandey, and Asok Bhattacharyya. "Modelling and Design of Inverter Threshold Quantization based Current Comparator using Artificial Neural Networks." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 1 (February 1, 2016): 320. http://dx.doi.org/10.11591/ijece.v6i1.pp320-329.

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<p>Performance of a MOS based circuit is highly influenced by the transistor dimensions chosen for that circuit. Thus, proper dimensioning of the transistors plays a key role in determining its overall performance. While choosing the dimension is critical, it is equally difficult, primarily due to complex mathematical formulations that come into play when moving into the submicron level. The drain current is the most affected parameter which in turn affects all other parameters. Thus, there is a constant quest to come up with techniques and procedure to simplify the dimensioning process while still keeping the parameters under check. This study presents one such novel technique to estimate the transistor dimensions for a current comparator structure, using the artificial neural networks approach. The approach uses Multilayer perceptrons as the artificial neural network architectures. The technique involves a two step process. In the first step, training and test data are obtained by doing SPICE simulations of modelled circuit using 0.18μm TSMC CMOS technology parameters. In the second step, this training and test data is applied to the developed neural network architecture using MATLAB R2007b.</p>

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15

Taube, Andrzej, Mariusz Sochacki, Jan Szmidt, Eliana Kaminska, and Anna Piotrowska. "Modelling and Simulation of Normally-Off AlGaN/GaN MOS-HEMTs." International Journal of Electronics and Telecommunications 60, no. 3 (October 28, 2014): 253–58. http://dx.doi.org/10.2478/eletel-2014-0032.

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Abstract The article presents the results of modelling and simulation of normally-off AlGaN/GaN MOS-HEMT transistors. The effect of the resistivity of the GaN:C layer, the channel mobility and the use of high-k dielectrics on the electrical characteristics of the transistor has been examined. It has been shown that a low leakage current of less than 10−6 A/mm can be achieved for the acceptor dopant concentration at the level of 5 X 1015 cm−3. The limitation of the maximum on-state current due to the low carrier channel mobility has been shown. It has also been demonstrated that the use of HfO2, instead of SiO2, as a gate dielectric increases on-state current above 0.7A/mm and reduces the negative influence of the charge accumulated in the dielectric layer.

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16

AL-AKHRAS, MOHAMMAD A., ANWAR A. KHAN, and ABDULRAHMAN M. ALAMOUD. "DC modelling of modified field-effect transistor." International Journal of Electronics 76, no. 3 (March 1994): 417–24. http://dx.doi.org/10.1080/00207219408925937.

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17

Sansen, W. "Modelling the MOS transistor at high frequencies." Electronics Letters 22, no. 15 (1986): 810. http://dx.doi.org/10.1049/el:19860556.

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18

METCALFE, J. G., R. C. HAYES, A. J. HOLDEN, and A. P. LONG. "MICROWAVE POWER GaAs/AlGaAs HETEROJUNCTION BIPOLAR TRANSISTOR MODELLING." Le Journal de Physique Colloques 49, no. C4 (September 1988): C4–579—C4–582. http://dx.doi.org/10.1051/jphyscol:19884122.

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19

Sahoo, R., and R. R. Mishra. "Graphical modelling of carbon nanotube field effect transistor." IOP Conference Series: Materials Science and Engineering 73 (February 17, 2015): 012089. http://dx.doi.org/10.1088/1757-899x/73/1/012089.

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20

Abu El-Seoud, A. K., M. El-Banna, and M. A. Hakim. "On modelling and characterization of single electron transistor." International Journal of Electronics 94, no. 6 (June 2007): 573–85. http://dx.doi.org/10.1080/00207210701295061.

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21

Sheng, Hanyu, and Soo-Jin Chua. "Proposing and modelling of a new unipolar transistor." Journal of Physics D: Applied Physics 27, no. 9 (September 14, 1994): 1946–51. http://dx.doi.org/10.1088/0022-3727/27/9/020.

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22

Marki, Rebiha, and Chérifa Azizi. "Physical modelling of carbon nanotube field effect transistor." International Journal of Nanoparticles 6, no. 2/3 (2013): 224. http://dx.doi.org/10.1504/ijnp.2013.054998.

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23

Rjoub, Abdoul, and Shihab AlKattab. "Modelling and simulation tools for nanoscale transistor sizing." International Journal of Simulation and Process Modelling 13, no. 3 (2018): 210. http://dx.doi.org/10.1504/ijspm.2018.093094.

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24

Rjoub, Abdoul, and Shihab AlKattab. "Modelling and simulation tools for nanoscale transistor sizing." International Journal of Simulation and Process Modelling 13, no. 3 (2018): 210. http://dx.doi.org/10.1504/ijspm.2018.10014178.

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25

McDonald, R. J. "Generalised partitioned-charge-based bipolar transistor modelling methodology." Electronics Letters 24, no. 21 (1988): 1302. http://dx.doi.org/10.1049/el:19880885.

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26

Sheng, H., and S. J. Chua. "Modelling of a resonant tunnelling hot electron transistor." Semiconductor Science and Technology 8, no. 8 (August 1, 1993): 1590–95. http://dx.doi.org/10.1088/0268-1242/8/8/017.

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27

Jiménez Tejada, J. A. "Editorial: Thin-film-transistor modelling for circuit simulation." IET Circuits, Devices & Systems 6, no. 2 (2012): 111. http://dx.doi.org/10.1049/iet-cds.2012.0047.

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28

Górecki, Paweł, Krzysztof Górecki, and Janusz Zarębski. "Accurate Circuit-Level Modelling of IGBTs with Thermal Phenomena Taken into Account." Energies 14, no. 9 (April 22, 2021): 2372. http://dx.doi.org/10.3390/en14092372.

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This paper proposes a new compact electrothermal model of the Insulated Gate Bipolar Transistors (IGBT) dedicated for SPICE (Simulation Program with Integrated Circuit Emphasis). This model makes it possible to compute the non-isothermal DC characteristics of the considered transistor and the waveforms of terminal voltages and currents of the investigated device and its internal temperature at transients. This model takes into account the nonlinearity of thermal phenomena in this device. The form of the formulated model is described and the problem of estimating its parameter values is discussed. The correctness of the proposed model was verified experimentally both at DC operation and at transients. The obtained results are compared to the results of computations performed with the use of the classical literature model. A very good agreement between the results of measurements and computations performed with the new model is obtained at different cooling conditions and in a wide range of changes of parameters characterising the electrical excitation of the tested device.

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29

Atamuratov, Atabek E., Mahkam M. Khalilloev, Ahmed Yusupov, A. J. García-Loureiro, Jean Chamberlain Chedjou, and Kyamakya Kyandoghere. "Contribution to the Physical Modelling of Single Charged Defects Causing the Random Telegraph Noise in Junctionless FinFET." Applied Sciences 10, no. 15 (August 1, 2020): 5327. http://dx.doi.org/10.3390/app10155327.

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In this paper, different physical models of single trap defects are considered, which are localized in the oxide layer or at the oxide–semiconductor interface of field effect transistors. The influence of these defects with different sizes and shapes on the amplitude of the random telegraph noise (RTN) in Junctionless Fin Field Effect Transistor (FinFET) is modelled and simulated. The RTN amplitude dependence on the number of single charges trapped in a single defect is modelled and simulated too. It is found out that the RTN amplitude in the Junctionless FinFET does not depend on the shape, nor on the size of the single defect area. However, the RTN amplitude in the subthreshold region does considerably depend on the number of single charges trapped in the defect.

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30

Chatzigeorgiou, A., and S. Nikolaidis. "Modelling the operation of pass transistor and CPL gates." International Journal of Electronics 88, no. 9 (September 2001): 977–1000. http://dx.doi.org/10.1080/00207210110066185.

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31

HAMED, S. A. "Modelling and design of transistor-controlled AC voltage regulators." International Journal of Electronics 69, no. 3 (September 1990): 421–34. http://dx.doi.org/10.1080/00207219008920328.

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32

Holden, A. J., C. G. Eddison, J. G. Metcalfe, and R. C. Hayes. "Bipolar heterojunction transistor integrated circuits: design, modelling and characterisation." Electronics Letters 22, no. 15 (1986): 815. http://dx.doi.org/10.1049/el:19860559.

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33

Schellin, R., and R. Mohr. "A monolithically-integrated transistor microphone: Modelling and theoretical behaviour." Sensors and Actuators A: Physical 37-38 (June 1993): 666–73. http://dx.doi.org/10.1016/0924-4247(93)80113-u.

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34

Lau, Jack, Ping K. Ko, and Philip C. H. Chan. "Modelling of split-drain magnetic field-effect transistor (MAGFET)." Sensors and Actuators A: Physical 49, no. 3 (July 1995): 155–62. http://dx.doi.org/10.1016/0924-4247(95)01025-4.

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35

Górecki, Krzysztof, and Paweł Górecki. "Modelling dynamic characteristics of the IGBT with thermal phenomena taken into account." Microelectronics International 34, no. 3 (August 7, 2017): 160–64. http://dx.doi.org/10.1108/mi-11-2016-0082.

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Purpose This paper aims to propose the electrothermal dynamic model of the insulated gate bipolar transistors (IGBT) for SPICE. Design/methodology/approach The electrothermal model of this device (IGBT), which takes into account both electrical and thermal phenomena, is described. Particularly, the sub-threshold operation of this device is considered and electrical, and thermal inertia of this device is taken into account. Attention was focused on the influence of electrical and thermal inertia on waveforms of terminal voltages of the considered transistor operating in the switching circuit and on waveforms of the internal temperature of this device. Findings The correctness of the presented model is verified experimentally and a good agreement of the calculated and measured electrical and thermal characteristics of the considered device is obtained. Research limitations/implications The presented model can be used for different types of IGBT, but it is dedicated for SPICE software only. Originality/value The form of the worked out model is presented and the results of experimental verification of this model are shown.

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36

Deen, M. Jamal. "High-frequency noise modelling and the scaling of the noise parameters of polysilicon emitter bipolar junction transistors." Canadian Journal of Physics 74, S1 (December 1, 1996): 195–99. http://dx.doi.org/10.1139/p96-858.

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This paper presents detailed results from modelling the four noise parameters: minimum noise figure (NFMIN), noise resistance (RN), optimal source resistance (RS,OPT), and reactance (XS,OPT) as functions of frequency and collector-biasing current. Compared to previous BJT (bipolar junction transistor) high-frequency noise models, we include the emitter resistance, which results in an increased input device impedance, and a degeneration of the device transconductance. We also give an explicit formula for the noise resistance. We present noise results for polysilicon emitter bipolar transistors as a function of emitter areas to demonstrate how the noise parameters scale with emitter areas over a range of frequencies. However, these results are given only for devices in which the pad impedances are much larger than the device input impedance, so that very little input signal is lost through the pads to ground.

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37

Sharma, Neha, and Rajeevan Chandel. "Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS." International Journal of Modeling, Simulation, and Scientific Computing 12, no. 04 (March 9, 2021): 2150029. http://dx.doi.org/10.1142/s179396232150029x.

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With technology scaling, stability, power dissipation, and device variability, the impact of process, voltage and temperature (PVT) variations has become dominant for static random access memory (SRAM) analysis for productivity and failure. In this paper, ten-transistors (10T) and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors (FGMOS). Power centric parameters viz. read power, write power, hold power and delay are the performance analysis metrics. Further, the stochastic parameter variation to study the variability tolerance of the redesigned cell, PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell. Stability has been illustrated with the conventional butterfly method giving read static noise margin (RSNM) and write static noise margin (WSNM) metrics for read stability and write ability, respectively. A comparative analysis with standard six-transistor SRAM cell is carried out. HSPICE simulative analysis has been carried out for 32[Formula: see text]nm technology node. The redesigned FGMOS SRAM cells provide improved performance. Also, these are robust and reliability efficient with comparable stability.

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38

Seoane, Natalia, Antonio García-Loureiro, and Karol Kalna. "Special Issue: Nanowire Field-Effect Transistor (FET)." Materials 13, no. 8 (April 14, 2020): 1845. http://dx.doi.org/10.3390/ma13081845.

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This Special Issue looks at recent developments in the research field of Nanowire Field-Effect Transistors (NW-FETs), covering different aspects of technology, physics, and modelling of these nanoscale devices. In this summary, we present seven outstanding articles on NW-FETs by providing a brief overview of the articles’ content.

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39

Puigcorbe´, J., S. Marco, S. Leseduarte, M. Carmona, O. Vendier, C. Devron, S. L. Delage, D. Floriot, and H. Blanck. "Finite Element Modelling of Flip Chip Gold-Gold Thermocompression Bonding." Journal of Electronic Packaging 125, no. 4 (December 1, 2003): 549–55. http://dx.doi.org/10.1115/1.1604157.

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The gold-gold thermocompression process for power heterostructure bipolar transistor (HBT) flip chip has been modelled and simulated by finite element method. A model for plated gold creep has been determined on the basis of empirical data and model comparison. This model seems suited for gold-gold thermocompression process optimization.

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40

Yamina, Berrichi, and Ghaffour Kherreddine. "Modelling Electronic Characteristic of InP/InGaAs Double Heterojunction Bipolar Transistor." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 3 (June 1, 2015): 525. http://dx.doi.org/10.11591/ijece.v5i3.pp525-530.

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In this paper, we are interested in studying InP/InGaAs heterojunction bipolar transistor NPN type. First and for most we should describe the structure of our simulation, then, we ploted at room temperature: Energy band diagram, Gummel plot, I<sub>C-</sub>V<sub>C</sub> characteristic and conduction bands for different values of V<sub>BE</sub>. The simulation of this structure has demonstrated the validity of our model and the method of the simulation.

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41

Besbes, Kamel. "Modelling an insulated gate bipolar transistor using bond graph techniques." International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 8, no. 1 (January 1995): 51–60. http://dx.doi.org/10.1002/jnm.1660080106.

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42

ŁUSZCZEK, Maciej. "Modelling of Graphene Field-Effect Transistor for electronic sensing applications." PRZEGLĄD ELEKTROTECHNICZNY 1, no. 10 (October 5, 2015): 172–74. http://dx.doi.org/10.15199/48.2015.10.34.

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43

Janicki, Marcin, Marcin Daniel, Michal Szermer, and Andrzej Napieralski. "Ion sensitive field effect transistor modelling for multidomain simulation purposes." Microelectronics Journal 35, no. 10 (October 2004): 831–40. http://dx.doi.org/10.1016/j.mejo.2004.06.015.

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44

Vidhate, Ashok D., and Shruti Suman. "Single Electron Transistor Based Current Mirror: Modelling and Performance Characterization." Journal of Nano- and Electronic Physics 13, no. 1 (2021): 01017–1. http://dx.doi.org/10.21272/jnep.13(1).01017.

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45

Jarndal, Anwar, Xuekun Du, and Yuehang Xu. "Modelling of GaN high electron mobility transistor on diamond substrate." IET Microwaves, Antennas & Propagation 15, no. 6 (March 22, 2021): 661–73. http://dx.doi.org/10.1049/mia2.12093.

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46

LINDBERG, ERIK, ARŪNAS TAMAŠEVIČIUS, GYTIS MYKOLAITIS, and SKAIDRA BUMELIENĖ. "TOWARDS THRESHOLD FREQUENCY IN CHAOTIC COLPITTS OSCILLATOR." International Journal of Bifurcation and Chaos 17, no. 10 (October 2007): 3449–53. http://dx.doi.org/10.1142/s0218127407019196.

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A novel version of chaotic Colpitts oscillator is described. Instead of a linear loss resistor, it includes an extra inductor and a diode in the collector circuit of the transistor. The modified circuit in comparison with the common Colpitts oscillator may generate chaotic oscillations at the fundamental frequency f* noticeably closer to the threshold frequency fT of the employed bipolar junction transistor, up to f* ≈ 0.6fT.

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Vimala, P., and N. R. Nithin Kumar. "Quantum Modelling of Nanoscale Silicon Gate-All-Around Field Effect Transistor." Journal of Nano Research 64 (November 2020): 115–22. http://dx.doi.org/10.4028/www.scientific.net/jnanor.64.115.

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The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.

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Patrzyk, Joanna, Damian Bisewski, and Janusz Zarębski. "Electrothermal Model of SiC Power BJT." Energies 13, no. 10 (May 21, 2020): 2617. http://dx.doi.org/10.3390/en13102617.

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This paper refers to the issue of modelling characteristics of SiC power bipolar junction transistor (BJT), including the self-heating phenomenon. The electrothermal model of the tested device is demonstrated and experimentally verified. The electrical model is based on the isothermal Gummel–Poon model, but several modifications were made including the improved current gain factor (β) model and the modified model of the quasi-saturation region. The accuracy of the presented model was assessed by comparison of measurement and simulation results of selected characteristics of the BT1206-AC SiC BJT manufactured by TranSiC. In this paper, a single device characterization has only been performed. The demonstrated results of research show the evident temperature impact on the transistor d.c. characteristics. A good compliance between the measured and calculated characteristics of the considered transistor is observed even in quasi-saturation mode.

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Marinkovic, Zlatica, Giovanni Crupi, Alina Caddemi, and Vera Markovic. "Two neural approaches for small-signal modelling of GaAs HEMTs." Journal of Automatic Control 20, no. 1 (2010): 39–44. http://dx.doi.org/10.2298/jac1001039m.

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Focus of this paper is on the neural approach in small-signal modelling of GaAs HEMTs. Two modelling approaches based on artificial neural networks are discussed and compared. The first approach is completely based on artificial neural networks, while the second is a hybrid approach putting together artificial neural networks and an equivalent circuit representation of a microwave transistor. Both models consider the device gate width and therefore both are scalable. Results of modelling of three different AlGaAs/GaAs HEMTs in a wide range of operating bias conditions using the considered approaches are given. Different modelling aspects are discussed. A special attention is paid to the model development procedure and accuracy of the models.

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CORRON, NED J., BUCKLEY A. HOPPER, and SHAWN D. PETHEL. "LIMITER CONTROL OF A CHAOTIC RF TRANSISTOR OSCILLATOR." International Journal of Bifurcation and Chaos 13, no. 04 (April 2003): 957–61. http://dx.doi.org/10.1142/s0218127403007035.

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We report experimental control of chaos in an electronic circuit at 43.9 MHz, which is the fastest chaos control reported in the literature to date. Limiter control is used to stabilize a periodic orbit in a tuned collector transistor oscillator modified to exhibit simply folded band chaos. The limiter is implemented using a transistor to enable monitoring the relative magnitude of the control perturbation. A plot of the relative control magnitude versus limiter level shows a local minimum at period-1 control, thereby providing strong evidence that the controlled state is an unstable periodic orbit (UPO) of the uncontrolled system.

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