Relevant bibliographies by topics / Transistor NMOS and PMOS

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Transistor NMOS and PMOS'

Author: Grafiati
Published: 4 June 2021
Last updated: 16 February 2022

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Journal articles on the topic "Transistor NMOS and PMOS"

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SHRIVAS, JAYRAM, SHYAM AKASHE, and NITESH TIWARI. "A HIGH-LEVEL TECHNIQUE FOR ESTIMATION AND OPTIMIZATION OF LEAKAGE POWER FOR FULL ADDER." International Journal of Nanoscience 12, no. 02 (2013): 1350011. http://dx.doi.org/10.1142/s0219581x13500117.

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Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turne
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Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with g
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Idris, Muhammad I., Ming Hung Weng, H. K. Chan, et al. "Electrical Stability Impact of Gate Oxide in Channel Implanted SiC NMOS and PMOS Transistors." Materials Science Forum 897 (May 2017): 513–16. http://dx.doi.org/10.4028/www.scientific.net/msf.897.513.

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Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (Dit), flatband voltage (VFB
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Reddy, M. Devendra, and P. Dass. "Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic." Alinteri Journal of Agriculture Sciences 36, no. 1 (2021): 635–41. http://dx.doi.org/10.47059/alinteri/v36i1/ajas21090.

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Aim: The aim of this work is to construct an innovative pMos logic based comparator and analyze the power consumption and compare with the nMos logic based comparator. Material and methods: The comparator is designed by using the Tanner tool version 16.01 for simulation and verification. By varying the length of a transistors in a circuit the power values were obtained. This experiment is performed for 20 different values of length. Results: The power consumption of a pMos logic based comparator was minimum (2.2656 ± 0.37933), followed by the nMos logic based comparator (7.7494 ± 0.41603), the
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Nam, Hyoungsik, Young-In Kim, Jina Bae, and Junhee Lee. "GateRL: Automated Circuit Design Framework of CMOS Logic Gates Using Reinforcement Learning." Electronics 10, no. 9 (2021): 1032. http://dx.doi.org/10.3390/electronics10091032.

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This paper proposes a GateRL that is an automated circuit design framework of CMOS logic gates based on reinforcement learning. Because there are constraints in the connection of circuit elements, the action masking scheme is employed. It also reduces the size of the action space leading to the improvement on the learning speed. The GateRL consists of an agent for the action and an environment for state, mask, and reward. State and reward are generated from a connection matrix that describes the current circuit configuration, and the mask is obtained from a masking matrix based on constraints
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Arnaud, F., H. Bernard, Alessio Beverina, et al. "Advanced Surface Cleaning Strategy for 65nm CMOS Device Performance Enhancement." Solid State Phenomena 103-104 (April 2005): 37–40. http://dx.doi.org/10.4028/www.scientific.net/ssp.103-104.37.

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This paper investigates low temperature cleaning steps solutions (T°<30°) developed to enhance the 65nm transistor performance. A complete cleaning recipes optimization is realized in term of silicon consumption and defectiveness for pre-furnace clean (RCA or HFRCA), post gate etch clean PGEC (HF-SPM-SC1) and post ash clean PAC (SPM–SC1) operations. The silicon recess and the dopants consumption are reduced by using low temperature SC1 steps. Transistor drivability is improved by 8% and 7% for NMOS and PMOS respectively.
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K. Castellani-Coulie, B. Sagnes. "Comparison of nmos and pmos transistor sensitivity to seu in srams by device simulation." IEEE Transactions on Nuclear Science 50, no. 6 (2003): 2239–44. http://dx.doi.org/10.1109/tns.2003.821583.

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Moisiadis, Y., I. Bouras, and A. Arapoyanni. "Charge Pump Circuits for Low-voltage Applications." VLSI Design 15, no. 1 (2002): 477–83. http://dx.doi.org/10.1080/1065514021000012084.

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In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several cross-connected NMOS voltage doubler stages. For very low-voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD-PMOS) in parallel to the cross-connected NMOS transistors, while
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Zainol Murad, Sohiful Anuar, Azizi Harun, Mohd Nazrin Md Isa, Saiful Nizam Mohyar, and Jamilah Karim. "A VERY LOW-DROPOUT VOLTAGE REGULATOR IN 0.18-M CMOS TECHNOLOGY FOR POWER MANAGEMENT SYSTEM." Jurnal Teknologi 82, no. 6 (2020): 11–19. http://dx.doi.org/10.11113/jurnalteknologi.v82.15031.

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This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results
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Neema, Vaibhav, Shailesh Singh Chouhan, and Sanjiv Tokekar. "Novel Circuit Technique for Reduction of Leakage Current in Series/Parallel PMOS/NMOS Transistor Stack." IETE Journal of Research 56, no. 6 (2010): 362–66. http://dx.doi.org/10.1080/03772063.2010.10876326.

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Dissertations / Theses on the topic "Transistor NMOS and PMOS"

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Cho, Hanho. "Optically Powered Logic Transistor." Diss., CLICK HERE for online access, 2008. http://contentdm.lib.byu.edu/ETD/image/etd2525.pdf.

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Kšica, Radim. "Návrh operačního zesilovače s proudovou zpětnou vazbou." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218578.

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This Master`s thesis deals with properties of current feedback operational amplifier. The main goal of this work is creation design process of current feedback operational amplifier by using CMOS technology AMIS 0,7 µm. Next goal of this work is attestation of funciton our design process. Last goal is creation the datasheet of our amplifier.
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Magierowski, Sebastian Claudiusz. "A PMOS transistor for a low-power 1 V CMOS process." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ28847.pdf.

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Bravaix, Alain. "Etudes des degradations du transistor pmos soumis aux injections de porteurs chauds." Paris 7, 1991. http://www.theses.fr/1991PA077217.

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Ce travail est consacre a l'etude des degradations du transistor pmos soumis aux injections de porteurs hautement energetiques generes par l'accroissement des champs electriques lies a la miniaturisation de sa geometrie. Ces mecanismes de degradations se manifestent par les derives temporelles des parametres electriques representatifs des performances du transistor, en raison de piegeage de charges dans l'oxyde et de la generation d'etats electroniques a l'interface oxyde-silicium. Cette etude presente tout d'abord un bref rappel des parametres de fonctionnement du transistor ainsi qu'un model
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Zbierska, Inga Jolanta. "Study of electrical characteristics of tri-gate NMOS transistor in bulk technology." Thesis, Lyon 1, 2014. http://www.theses.fr/2014LYO10282/document.

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Afin de dépasser la limite d'échelle, il existe une solution innovante qui permet de fabriquer des structures multi-grilles. Ainsi, un NMOSFET composé de trois grilles indépendantes fabriquées dans la technologie CMOS. En dehors de leur forme, géométrique, le transistor multi-grille est similaire à une structure classique. Une multi-grille NMOSFET peut être fabriquée par l'intégration de tranchées de polysilicium. Ces tranchées sont utilisées dans diverses applications telles que les mémoires DRAM, électronique de puissance ou de capteurs d'image. Les capteurs d'image présentent le problème de
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Raynaud, Christine. "Contribution à la caractérisation et à la modélisation de transistors NMOS submicroniques en haute fréquence." Grenoble INPG, 1988. http://www.theses.fr/1988INPG0124.

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Des transistors nmos submicroniques ont ete realises et caracterises par la mesure de leurs parametres s a haute frequence afin d'evaluer les performances limites apportees par des longueurs inferieures au micron
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Bizouerne, Maxime. "Développement de procédés de gravure plasma sans dommages pour l'intégration de l'InGaAs comme canal tridimensionnel de transistor nMOS non-planaire." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT030/document.

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L’augmentation des performances des dispositifs de la microélectronique repose encore pour une dizaine d’années sur une miniaturisation des circuits intégrés. Cette miniaturisation s’accompagne inévitablement d’une complexification des architectures et des empilements de matériaux utilisés. Au début de cette thèse, une des voies envisagées pour poursuivre la miniaturisation était de remplacer, dans une architecture finFET, le canal en silicium par un semi-conducteur à plus forte mobilité électronique, tel que l’In0,53Ga0,47As pour les transistors nMOS. Une étape essentielle à maitriser dans la
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Orhant, Philippe. "Etude de la dégradation du transistor NMOS due à l'injection d'électrons chauds dans l'oxyde de grille et à l'interface oxyde-silicium, proposition d'un test accélérant ce phénomène de vieillissement." Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37600143x.

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Orhant, Philippe. "Etude de la degradation du transistor nmos due a l'injection d'electrons chauds dans l'oxyde de grille et a l'interface oxyde-silicium : proposition d'un test accelerant ce phenomene de vieillissement." Rennes 1, 1986. http://www.theses.fr/1986REN10113.

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Apres un recensement des differents mecanismes d'injection d'electrons "chauds" dans l'oxyde de grille et a l'interface sisio2 d'un transistor nmos, une technologie originale de determination de la zone de degradation est developpee. Elle consiste en une comparaison de deux mesures de la tension de seuil obtenues, l'une par une "methode de saturation du drain", l'autre par une "methode de saturation de la source". Le fait d'inverser le role du drain et de la source permet de mettre en evidence la dyssimetrie du transistor degrade. Grace a cette nouvelle technique, nous avons pu suivre l'evolut
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YUN-HAO, LEE, and 李勻皓. "Model of indium diffusion and its application in deep submicron NMOS transistor." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/54549927896640166714.

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碩士<br>長庚大學<br>電機工程研究所<br>88<br>In the development of deep-submicron, because of scaling down of device, the process control in channel and junction depth is important. Indium has been used as an alternative channel implant in submicrometer channel Si MOSFET’s, Due to its high atomic mass, indium present a strong retrograde profile. In this paper, we investigated diffusion of indium in p Si substrate. From SIMS data and simulation (Tsuprem4), we can extract its diffusion coefficient, we found its diffusion model was dominated by neutral point defects, especially interstitials. Accord
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Books on the topic "Transistor NMOS and PMOS"

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Magierowski, Sebastian Claudiusz. A PMOS transistor for a low-power 1 V CMOS process. National Library of Canada = Bibliothèque nationale du Canada, 1999.

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Book chapters on the topic "Transistor NMOS and PMOS"

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Karmakar, Supriya. "Quantum Dot Gate NMOS Inverter." In Novel Three-state Quantum Dot Gate Field Effect Transistor. Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-1635-3_5.

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Sengupta, Sarmista, and Soumya Pandit. "Statistical Characterization of Flicker Noise Fluctuation of a Nano-Scale NMOS Transistor." In Springer Proceedings in Physics. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-34216-5_21.

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Charef, M., F. Dessenne, J. L. Thobel, L. Baudry, and R. Fauquembergue. "The Influence of Technological Parameters on Ultra-Short Gate Si-NMOS Transistor Performances." In Simulation of Semiconductor Devices and Processes. Springer Vienna, 1993. http://dx.doi.org/10.1007/978-3-7091-6657-4_75.

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Ni, Haiyan, Lifang Ye, and Jianping Hu. "Dual-Threshold CMOS Technique for Pass-Transistor Adiabatic Logic with PMOS Pull-Up Configuration." In Lecture Notes in Electrical Engineering. Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-19706-2_5.

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Tewari, Suchismita, Abhijit Biswas, and Abhijit Mallik. "Investigations on the Logic Circuit Behaviour of Hybrid CMOSFETs Comprising InGaAs nMOS and Ge pMOS Devices with Barrier Layers." In Proceedings of the International Conference on Microelectronics, Computing & Communication Systems. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-5565-2_13.

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Krishnamohan, Tejas, Christoph Jungemann, and Krishna C. Saraswat. "Very High Performance, Sub-20nm, Strained Si and Six Ge1-x, Hetero-structure, Center Channel (CC) NMOS and PMOS DGFETs." In Simulation of Semiconductor Processes and Devices 2004. Springer Vienna, 2004. http://dx.doi.org/10.1007/978-3-7091-0624-2_43.

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Bhowmik, Sonali, and Surajit Bari. "Design and Delay Analysis of Column Decoder Using NMOS Transistor at Nano Level for Semiconductor Memory Application." In Computational Advancement in Communication Circuits and Systems. Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2274-3_42.

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"Case Study — Pseudo PMOS Field Effect Transistor." In Circuit Design Techniques for Non-Crystalline Semiconductors. CRC Press, 2012. http://dx.doi.org/10.1201/b12683-17.

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Suzuki, Teruo. "ESD Protection Circuits Using NMOS Parasitic Bipolar Transistor." In Electrostatic Discharge Protection. CRC Press, 2017. http://dx.doi.org/10.1201/b18976-8.

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Conference papers on the topic "Transistor NMOS and PMOS"

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Teo, J. K. J., C. M. Chua, L. S. Koh, and J. C. H. Phang. "Characterization of MOS Transistors Using Dynamic Backside Reflectance Modulation Technique." In ISTFA 2011. ASM International, 2011. http://dx.doi.org/10.31399/asm.cp.istfa2011p0170.

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Abstract The channel of metal-oxide-semiconductor (MOS) transistors at different modes of operation has been characterized using dynamic backside laser reflectance modulation technique for different NMOS and PMOS transistors with different channel lengths. The reflectance modulations contain a primary peak near the drain-end when the MOS transistor is in saturation mode. Comparison studies with a Pseudo-Two-Dimensional analytical model support the hypothesis that the observed peak corresponds to the pinch-off point.
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Dawood, M. K., C. Chen, P. K. Tan, et al. "Utilizing Nanoprobing and Circuit Diagnostics to Identify Key Failure Mechanism of Otherwise Nonvisible Defects in 20 nm Logic Devices." In ISTFA 2014. ASM International, 2014. http://dx.doi.org/10.31399/asm.cp.istfa2014p0196.

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Abstract In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM
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Jiang, Chun, Chenming Hu, C. H. Chen, and P. N. Tseng. "Impact of Inter-Metal-Oxide Deposition Condition on NMOS & PMOS Transistor Hot Carrier Effect." In 30th International Reliability Physics Symposium. IEEE, 1992. http://dx.doi.org/10.1109/irps.1992.363285.

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Jiang, C., C. Hu, C. H. Chen, and P. N. Tseng. "Impact of inter-metal-oxide deposition condition on NMOS and PMOS transistor hot carrier effect." In 30th Annual Proceedings Reliability Physics 1992. IEEE, 1992. http://dx.doi.org/10.1109/relphy.1992.187635.

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Hirata, Francisco I., Murial Muller, Yang Ni, and Claude Gimenes. "A new empirical I-V model for NMOS and PMOS transistors." In 2007 International Conference on Microelectronics - ICM. IEEE, 2007. http://dx.doi.org/10.1109/icm.2007.4497728.

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Koh, L. S., H. Marks, L. K. Ross, C. M. Chua, and J. C. H. Phang. "Laser Timing Probe with Frequency Mapping for Locating Signal Maxima." In ISTFA 2009. ASM International, 2009. http://dx.doi.org/10.31399/asm.cp.istfa2009p0033.

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Abstract A Laser Timing Probe (LTP) system which uses a noninvasive 1.3 µm continuous wave (CW) laser with frequency mapping and single point measurement capabilities is described. The frequency mapping modes facilitate the localization of signal maxima for subsequent single point measurements. Measurements of waveforms with long delays and 50 ps response time from NMOS and PMOS transistors are also shown.
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Severi, S., E. Augendre, A. Falepin, et al. "NMOS and PMOS Metal Gate Transistors with Junctions Activated by Laser Annealing." In 2006 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA). IEEE, 2006. http://dx.doi.org/10.1109/vtsa.2006.251093.

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Welser, Hoyt, and Gibbons. "NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures." In Proceedings of IEEE International Electron Devices Meeting. IEEE, 1992. http://dx.doi.org/10.1109/iedm.1992.307527.

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Aristova, N. E., A. Y. Borisov, A. S. Tararaksin, L. N. Kessarinskiy, and A. V. Yanenko. "Automatic test complex for parametric control of power NMOS and PMOS transistors." In 2015 International Siberian Conference on Control and Communications (SIBCON). IEEE, 2015. http://dx.doi.org/10.1109/sibcon.2015.7146984.

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Doria, R. T., R. D. Trevisoli, M. de Souza, I. Ferain, S. Das, and M. A. Pavanello. "Low-Frequency Noise of nMOS and pMOS short channel junctionless nanowire transistors." In 2012 IEEE International SOI Conference. IEEE, 2012. http://dx.doi.org/10.1109/soi.2012.6404379.

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