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Journal articles on the topic 'Transistor NMOS and PMOS'

Author: Grafiati

Published: 4 June 2021

Last updated: 16 February 2022

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1

SHRIVAS, JAYRAM, SHYAM AKASHE, and NITESH TIWARI. "A HIGH-LEVEL TECHNIQUE FOR ESTIMATION AND OPTIMIZATION OF LEAKAGE POWER FOR FULL ADDER." International Journal of Nanoscience 12, no. 02 (2013): 1350011. http://dx.doi.org/10.1142/s0219581x13500117.

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Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turne

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2

Jiang, Jin Tao, Li Fang Ye, and Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration." Applied Mechanics and Materials 39 (November 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.

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Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with g

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3

Idris, Muhammad I., Ming Hung Weng, H. K. Chan, et al. "Electrical Stability Impact of Gate Oxide in Channel Implanted SiC NMOS and PMOS Transistors." Materials Science Forum 897 (May 2017): 513–16. http://dx.doi.org/10.4028/www.scientific.net/msf.897.513.

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Operation of SiC MOSFETs beyond 300°C opens up opportunities for a wide range of CMOS based digital and analogue applications. However the majority of the literature focuses only on the optimization of a single type of MOS device (either PMOS or more commonly NMOS) and there is a lack of a comprehensive study describing the challenge of optimizing CMOS devices. This study reports on the impact of gate oxide performance in channel implanted SiC on the electrical stability for both NMOS and PMOS capacitors and transistors. Parameters including interface state density (Dit), flatband voltage (VFB

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4

Reddy, M. Devendra, and P. Dass. "Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic." Alinteri Journal of Agriculture Sciences 36, no. 1 (2021): 635–41. http://dx.doi.org/10.47059/alinteri/v36i1/ajas21090.

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Aim: The aim of this work is to construct an innovative pMos logic based comparator and analyze the power consumption and compare with the nMos logic based comparator. Material and methods: The comparator is designed by using the Tanner tool version 16.01 for simulation and verification. By varying the length of a transistors in a circuit the power values were obtained. This experiment is performed for 20 different values of length. Results: The power consumption of a pMos logic based comparator was minimum (2.2656 ± 0.37933), followed by the nMos logic based comparator (7.7494 ± 0.41603), the

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5

Nam, Hyoungsik, Young-In Kim, Jina Bae, and Junhee Lee. "GateRL: Automated Circuit Design Framework of CMOS Logic Gates Using Reinforcement Learning." Electronics 10, no. 9 (2021): 1032. http://dx.doi.org/10.3390/electronics10091032.

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This paper proposes a GateRL that is an automated circuit design framework of CMOS logic gates based on reinforcement learning. Because there are constraints in the connection of circuit elements, the action masking scheme is employed. It also reduces the size of the action space leading to the improvement on the learning speed. The GateRL consists of an agent for the action and an environment for state, mask, and reward. State and reward are generated from a connection matrix that describes the current circuit configuration, and the mask is obtained from a masking matrix based on constraints

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Arnaud, F., H. Bernard, Alessio Beverina, et al. "Advanced Surface Cleaning Strategy for 65nm CMOS Device Performance Enhancement." Solid State Phenomena 103-104 (April 2005): 37–40. http://dx.doi.org/10.4028/www.scientific.net/ssp.103-104.37.

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This paper investigates low temperature cleaning steps solutions (T°<30°) developed to enhance the 65nm transistor performance. A complete cleaning recipes optimization is realized in term of silicon consumption and defectiveness for pre-furnace clean (RCA or HFRCA), post gate etch clean PGEC (HF-SPM-SC1) and post ash clean PAC (SPM–SC1) operations. The silicon recess and the dopants consumption are reduced by using low temperature SC1 steps. Transistor drivability is improved by 8% and 7% for NMOS and PMOS respectively.

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K. Castellani-Coulie, B. Sagnes. "Comparison of nmos and pmos transistor sensitivity to seu in srams by device simulation." IEEE Transactions on Nuclear Science 50, no. 6 (2003): 2239–44. http://dx.doi.org/10.1109/tns.2003.821583.

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Moisiadis, Y., I. Bouras, and A. Arapoyanni. "Charge Pump Circuits for Low-voltage Applications." VLSI Design 15, no. 1 (2002): 477–83. http://dx.doi.org/10.1080/1065514021000012084.

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In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several cross-connected NMOS voltage doubler stages. For very low-voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD-PMOS) in parallel to the cross-connected NMOS transistors, while

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9

Zainol Murad, Sohiful Anuar, Azizi Harun, Mohd Nazrin Md Isa, Saiful Nizam Mohyar, and Jamilah Karim. "A VERY LOW-DROPOUT VOLTAGE REGULATOR IN 0.18-M CMOS TECHNOLOGY FOR POWER MANAGEMENT SYSTEM." Jurnal Teknologi 82, no. 6 (2020): 11–19. http://dx.doi.org/10.11113/jurnalteknologi.v82.15031.

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This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results

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10

Neema, Vaibhav, Shailesh Singh Chouhan, and Sanjiv Tokekar. "Novel Circuit Technique for Reduction of Leakage Current in Series/Parallel PMOS/NMOS Transistor Stack." IETE Journal of Research 56, no. 6 (2010): 362–66. http://dx.doi.org/10.1080/03772063.2010.10876326.

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11

Dadoria, Ajay Kumar, Kavita Khare, Tarun Kumar Gupta, and R. P. Singh. "New Leakage Reduction Techniques for FinFET Technology with Its Application." Journal of Circuits, Systems and Computers 27, no. 07 (2018): 1850112. http://dx.doi.org/10.1142/s0218126618501128.

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This paper describes three novel techniques such as drain gating PMOS transistor (DGPT), drain gating NMOS transistor (DGNT) and drain gating NMOS–PMOS transistor (DGNPT) for mitigation of leakage power, which are proposed to be used for low-power (LP) applications. The proposed techniques have leakage controlling sleep transistor inserted with sleep signal between pull-up and pull-down networks for reducing the leakage power. Simulation results are derived by HSPICE tool with PTM model for FinFET process fabrication at 32[Formula: see text]nm technology node at 25[Formula: see text]C and 110[

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12

Weng, Ming Hung, Muhammad I. Idris, H. K. Chan, et al. "Analytical Evaluation of Thermally Oxidized and Deposited Dielectric in NMOS-PMOS devices." Materials Science Forum 858 (May 2016): 631–34. http://dx.doi.org/10.4028/www.scientific.net/msf.858.631.

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We demonstrate the influence of enhancing the dielectric film used to form the gate in complimentary MOS circuits, designed for high temperature operation. The data show that the characteristics of both n-MOS and p-MOS capacitors and transistors have degraded capacitance characteristics in terms of the trapped charge in the dielectric, although the interface state density is dictated by the underlying stub oxide, at around 5×1012 cm-2eV-1. The use of a deposited oxide also reduces the variability in the critical electric field in the oxide, whilst maintaining a value of approximately 10MV cm-1

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Rjoub, Abdoul, and Odysseas Koufopavlou. "Efficient Low Power/Low Swing Bus Design Architectures." VLSI Design 12, no. 3 (2001): 415–29. http://dx.doi.org/10.1155/2001/63230.

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Novel low-power circuits based on low swing voltage technique, in the internal nodes of bus architectures, are proposed. Different classes of driver/receiver and repeater circuits are presented. They are implemented on conventional CMOS technology. The proposed technique is based on inserting a variable number of MOSFET transistors in the driver circuits, causing variable low swing voltage levels in the output of the driver circuits. In order to re-pull up the low swing voltage to full swing, innovated high-speed, crosscoupled latch voltage receiver circuits are proposed. In applications havin

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Rotondaro, A. L. Pacheco, R. T. Laaksonen, and S. P. Singh. "Impact of the Nitrogen Concentration of Sub-1.3 nm Gate Oxides on 65 nm Technology Transistor Parameters." Journal of Integrated Circuits and Systems 2, no. 2 (2007): 63–66. http://dx.doi.org/10.29292/jics.v2i2.265.

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The nitrogen concentration of ultrathin gate oxides (sub-1.3 nm) was varied in a wide range (from 13 % to 23 %). The threshold voltage and the channel carrier mobility of advanced 65 nm technology CMOSFET transistors fabricated with these oxides were analyzed. It was observed that increasing the nitrogen concentration in the gate oxide results in a negative shift of the threshold voltage for both NMOS and PMOS devices and a degradation of the hole mobility. It was also observed that pchannel transistors are more sensitive to the nitrogen concentration of the gate oxide than n-channel transisto

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15

Puhan, Janez, Dušan Raič, Tadej Tuma, and Árpád Bűrmen. "Break-before-Make CMOS Inverter for Power-Efficient Delay Implementation." Scientific World Journal 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/349131.

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A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global opti

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16

Lee, Minjong, Joohoon Kang, and Young Tack Lee. "Melt Blown Fiber-Assisted Solvent-Free Device Fabrication at Low-Temperature." Micromachines 11, no. 12 (2020): 1091. http://dx.doi.org/10.3390/mi11121091.

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In this paper, we propose a solvent-free device fabrication method using a melt-blown (MB) fiber to minimize potential chemical and thermal damages to transition-metal-dichalcogenides (TMDCs)-based semiconductor channel. The fabrication process is composed of three steps; (1) MB fibers alignment as a shadow mask, (2) metal deposition, and (3) lifting-up MB fibers. The resulting WSe2-based p-type metal-oxide-semiconductor (PMOS) device shows an ON/OFF current ratio of ~2 × 105 (ON current of ~−40 µA) and a remarkable linear hole mobility of ~205 cm2/V·s at a drain voltage of −0.1 V. These resul

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17

Niitsu, Kiichi, Kazunori Sakuma, Naohiro Harigai, et al. "Design Methodology and Jitter Analysis of a Delay Line for High-Accuracy On-Chip Jitter Measurements." Key Engineering Materials 596 (December 2013): 176–80. http://dx.doi.org/10.4028/www.scientific.net/kem.596.176.

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This work presents the design methodology and jitter analysis of a delay line for high-accuracy on-chip jitter measurements. Jitter generated in the delay lines degrades the accuracy of on-chip jitter measurements, and required to be minimized. In order to analyze and the jitter generation in the delay lines, SPICE simulation was performed with 65 nm CMOS technology. Simulation results show that jitter due to thermal noise can be reduced by enlarging the transistor sizes of both PMOS and NMOS. Based on the results, design methodology of a delay line is introduced for minimizing the jitter gene

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18

Birla, Shilpi. "FinFET SRAM cell with improved stability and power for low power applications." Journal of Integrated Circuits and Systems 14, no. 2 (2019): 1–8. http://dx.doi.org/10.29292/jics.v14i2.57.

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In this paper, a new 11T SRAM cell using Double gate FET (FinFET technology) has been proposed, cell basic component is the 6T SRAM cell with 4 NMOS access transistors to improve the stability over CMOSFET circuits and also makes it a dual port memory cell. The proposed cell also used a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability which helps in reducing the leakage current, active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at threshold and subthreshold voltage

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19

Duraivel, A. N., B. Paulchamy, and K. Mahendrakan. "Proficient Technique for High Performance Very Large-Scale Integration System to Amend Clock Gated Dual Edge Triggered Sense Amplifier Flip-Flop with Less Dissipation of Power Leakage." Journal of Nanoelectronics and Optoelectronics 16, no. 4 (2021): 602–11. http://dx.doi.org/10.1166/jno.2021.2984.

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Clocked flip flops are used to memory in synchronous or clocked series networks, adjusting the individual clock signal status. Therefore, at these times of clock signal transfer, the state of the memory unit and the state of the whole electrical structure change. It’s only during signal transfer that the key to a flip-flop being correctly operated. Two transitions from 0 and 1 are followed by a clock pulse, and 1 to 0. The pulse shift is defined by the positive and negative sides of the pulse. The data on or off the clock cycle edges are recorded by a single-edge trigger flip flop (SETFF), but

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20

Pavan, Paolo, Enrico Zanoni, Bruno Bonati, Sergio Martion, and Giovanna Dalla Libera. "A study of ESD- induced defects in high-voltage nMOS and pMOS transistors." Microelectronics Journal 23, no. 1 (1992): 45–50. http://dx.doi.org/10.1016/0026-2692(92)90095-i.

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21

Behera, Truptimayee, and Ritisnigdha Das. "Design of Low Power CMOS Comparator using 180nm Technology for ADC Application." Circulation in Computer Science MCSP2017, no. 01 (2017): 11–13. http://dx.doi.org/10.22632/ccs-2017-mcsp027.

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In our design of CMOS comparator with high performance using GPDK 180nm technology we optimize these parameters. We analyse the transient response of the schematic design and the gain is calculated in AC analysis and also we measure the power dissipation. The circuit is built by using PMOS and NMOS transistor with a body effect. A plot of phase and gain also discussed in the paper. Finally a test schematic is built and transient analysis for an input voltage of 2V is measured using Cadence virtuoso. Simulation results are presented and it shows that this design can work under high speed clock

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22

Suvarna, S., K. Rajesh, and T. Radhu. "A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic." International Journal of Students' Research in Technology & Management 4, no. 1 (2016): 01–05. http://dx.doi.org/10.18510/ijsrtm.2016.411.

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High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transist

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23

Tan, Gim Heng, Roslina Mohd Sidek, Harikrishnan Ramiah, Wei Keat Chong, and De Xing Lioe. "Ultra-Low-Voltage CMOS-Based Current Bleeding Mixer with High LO-RF Isolation." Scientific World Journal 2014 (2014): 1–5. http://dx.doi.org/10.1155/2014/163414.

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This journal presents an ultra-low-voltage current bleeding mixer with high LO-RF port-to-port isolation, implemented on 0.13 μm standard CMOS technology for ZigBee application. The architecture compliments a modified current bleeding topology, consisting of NMOS-based current bleeding transistor, PMOS-based switching stage, and integrated inductors achieving low-voltage operation and high LO-RF isolation. The mixer exhibits a conversion gain of 7.5 dB at the radio frequency (RF) of 2.4 GHz, an input third-order intercept point (IIP3) of 1 dBm, and a LO-RF isolation measured to 60 dB. The DC p

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Jain, Prateek, and Amit Joshi. "Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration." Journal of Circuits, Systems and Computers 27, no. 06 (2018): 1850092. http://dx.doi.org/10.1142/s0218126618500925.

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An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the

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John, Kuruvilla, Vinod Kumar R S, and Kumar S S. "Design of low power and high speed implicit pulse flip-flop and its application." International Journal of Engineering & Technology 7, no. 3 (2018): 1893. http://dx.doi.org/10.14419/ijet.v7i3.12845.

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In this paper, a new power efficient and high speed pulsed-triggered flip-flop in implicit style with conditional pulse enhancement and signal feed-through (CPESFTFF) is proposed. This novel architecture is presented for the pulse-triggered D-FF in the CMOS 90-nm technology. Two important features are embedded in this flip-flop architecture. Firstly, a conditional enhancement in width and height of the triggering pulses by using an additional pMOS transistor in the structure is done. Secondly, a modified signal feed-through mechanism which directly samples the input to output by using an nMOS

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26

Flores, D., J. Rebollo, J. Fernández, X. Jordà, P. Godignon, and J. Millán. "Comparison of EST structures with NMOS and PMOS transistors for controlling the thyristor current." Microelectronics Journal 29, no. 11 (1998): 933–37. http://dx.doi.org/10.1016/s0026-2692(98)00062-7.

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Moon, H., and I. Nam. "1.3 V low close-in phase noise NMOS LC-VCO with parallel PMOS transistors." Electronics Letters 44, no. 11 (2008): 676. http://dx.doi.org/10.1049/el:20080404.

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Olmos, Alfredo, Fabricio Ferreira, Fernando Paixão Cortes, Fernando Chavez, and Marcelo Soares Lubaszewski. "A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference: Design and Application." Journal of Integrated Circuits and Systems 10, no. 2 (2015): 74–80. http://dx.doi.org/10.29292/jics.v10i2.408.

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This paper presents the design and application of a CMOS sub-1V voltage reference using a 2-transistor Self-Cascode MOSFET (SCM) structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. The two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a > 0.18mm standard

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29

Silva, Otávio Soares, Rodrigo Aparecido da Silva Braga, Dean Bicudo Karolak, and Paulo Marcio Moreira e. Silva. "Projeto de um OTA Baseado em Inversores em Processo CMOS de 130 nm." Research, Society and Development 9, no. 6 (2020): e51963334. http://dx.doi.org/10.33448/rsd-v9i6.3334.

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Nos processos de fabricação de amplificadores diferenciais integrados uma característica inerente é que os transistores nMOS e pMOS construídos possuam diferenças físicas em relação aos valores projetados, efeito conhecido como descasamento. Neste trabalho será avaliado o impacto que os processos de fabricação infligem em um amplificador operacional de transcondutância construído com transistores com canal uniformemente dopado e baixa tensão de threshold e transistores de canal uniformemente dopado com tensão de threshold regular utilizando uma pesquisa experimental quantitativa.

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KABBANI, ADNAN. "COMPLEX CMOS GATE COLLAPSING TECHNIQUE AND ITS APPLICATION TO TRANSIENT TIME." Journal of Circuits, Systems and Computers 19, no. 05 (2010): 1025–40. http://dx.doi.org/10.1142/s021812661000658x.

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In this paper we present a technique to collapse a CMOS gate into an equivalent inverter. This technique considers deep submicron effects such as mobility degradation and velocity saturation as well as operation regions of both the NMOS and PMOS networks of the considered CMOS gate. In addition, the model accounts for the effect of the gate's internodal capacitances on the behavior of the equivalent Series Connected MOSFET Structure. Depending on the CMOS inverter transition time model presented in Ref. 1, the developed model has accurately predicted the transition time of different CMOS gates

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Mannaert, G., L. Witters, Denis Shamiryan, et al. "Post Extension Ion Implant Photo Resist Strip for 32 nm Technology and beyond." Solid State Phenomena 145-146 (January 2009): 253–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.145-146.253.

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The most advanced technology nodes require ultra shallow extension implants (low energy) which are very vulnerable to ash related substrate oxidation, silicon and dopant loss, which can result in a dramatic increase of the source/drain resistance and shifted transistor threshold voltages. A robust post extension ion implant ash process is required in order to meet cleanliness, near zero Si loss and dopant loss specifications. This paper discusses a performance comparison between fluorine-free, reducing and oxidizing, ash chemistries and “as implanted – no strip” process conditions, for both st

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CHENG, KUO-HSING, SHUN-WEN CHENG, and WEN-SHIUAN LEE. "64-BIT PIPELINE CARRY LOOKAHEAD ADDER USING ALL-N-TRANSISTOR TSPC LOGICS." Journal of Circuits, Systems and Computers 15, no. 01 (2006): 13–27. http://dx.doi.org/10.1142/s0218126606002915.

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This paper proposes two improved circuit techniques of True Single-Phase Clocking (TSPC) logic, which called Nonfull Swing TSPC (NSTSPC) and All-N-TSPC (ANTSPC). The voltage of internal node of the NSTSPC is not full swing; it saves partial dynamic power dissipation. And the ANTSPC uses NMOS transistors to replace PMOS transistors, the output loading of Φ-section is therefore reduced and a higher layout density is obtained. Through postlayout simulation comparisons between number of stacked MOS transistors and delay time, and supply voltage vs maximum frequency, the proposed NSTSPC and ANTSPC

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Man Pio Lam and K. T. Kornegay. "Punchthrough behavior in short channel NMOS and PMOS 6H-silicon carbide transistors at elevated temperatures." IEEE Transactions on Components and Packaging Technologies 22, no. 3 (1999): 433–38. http://dx.doi.org/10.1109/6144.796547.

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ZHAN, CHENCHANG, and WING-HUNG KI. "A LOW DROPOUT REGULATOR WITH LOW QUIESCENT CURRENT AND HIGH POWER SUPPLY REJECTION OVER WIDE RANGE OF FREQUENCY FOR SOC." Journal of Circuits, Systems and Computers 20, no. 01 (2011): 1–13. http://dx.doi.org/10.1142/s0218126611007037.

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A CMOS low quiescent current low dropout regulator (LDR) with high power supply rejection (PSR) and without large output capacitor is proposed for system-on-chip (SoC) power management applications. By cascoding a power NMOS with the PMOS pass transistor, high PSR over a wide frequency range is achieved. The gate-drive of the cascode NMOS is controlled by an auxiliary LDR that draws only 1 μA from a small charge pump, thus helping in reducing the quiescent current. Adaptive biasing is employed for the multi-stage error amplifier of the core LDR to achieve high loop gain hence high PSR at low f

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Rastogi, Rumi, Sujata Pandey, and Mridula Gupta. "Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits." Nanoscience & Nanotechnology-Asia 10, no. 5 (2020): 696–708. http://dx.doi.org/10.2174/2210681209666190513120054.

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Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits. Objective: The objective of the paper was to prop

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El Boukili, Abderrazzak. "New physically based model for thermal induced initial stress in 3D for silicon germanium films after deposition." COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 33, no. 6 (2014): 2121–38. http://dx.doi.org/10.1108/compel-11-2013-0390.

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Purpose – The purpose of this paper is to provide a new three dimension physically based model to calculate the initial stress in silicon germanium (SiGe) film due to thermal mismatch after deposition. We should note that there are many other sources of initial stress in SiGe films or in the substrate. Here, the author is focussing only on how to model the initial stress arising from thermal mismatch in SiGe film. The author uses this initial stress to calculate numerically the resulting extrinsic stress distribution in a nanoscale PMOS transistor. This extrinsic stress is used by industrials

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Amat, E., T. Kauerauf, R. Degraeve, et al. "Channel hot-carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack." Microelectronic Engineering 87, no. 1 (2010): 47–50. http://dx.doi.org/10.1016/j.mee.2009.05.013.

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Ramakrishna, P., and K. Hari Kishore. "Design of low power 10GS/s 6-Bit DAC using CMOS technology." International Journal of Engineering & Technology 7, no. 1.5 (2017): 226. http://dx.doi.org/10.14419/ijet.v7i1.5.9151.

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A Low power 6-bit R-2R ladder Digital to Analog Converter is presented in this paper. Here the R-2 R network designed using resistors with only two values-R and 2xRand the switch is designed by using both NMOS and PMOS Transistors. This Digital to Analog Converters operated with low voltage, by applying dynamic threshold MOSFET (DTMOS) logic. This design achieved less INL and DNL which is 0.3 and 0.06 respectively. Power supply required to operate this device is only 1V with10GHzconversion rate. This design is implemented by using 0.18μm CMOS technology.

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Goyal, Candy, Jagpal Singh Ubhi, and Balwinder Raj. "A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise." Mathematical Problems in Engineering 2018 (December 16, 2018): 1–16. http://dx.doi.org/10.1155/2018/3501041.

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In this paper, an effective and reliable sleep circuit is proposed, which not only reduces leakage power but also shows significant reduction in ground bounce noise (GBN) in approximate full adder (FA) circuits. Four 1-bit approximate FA circuits are modified using proposed sleep circuit which uses one NMOS and one PMOS transistor. The design metrics such as average power, delay, power delay product (PDP), leakage power, and GBN are compared with nine other 1-bit FA circuits reported till date. All the comparisons are done using post-layout netlist at 45nm technology. The modified designs achi

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Pandey, Amit Kumar, Tarun Kumar Gupta, and Pawan Kumar Verma. "Sleep signal controlled footless domino circuit for low leakage current." Circuit World 44, no. 2 (2018): 87–98. http://dx.doi.org/10.1108/cw-06-2017-0030.

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Purpose This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents. Design/methodology/approach In the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state. Findings The authors simulate the propos

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Noulis, T., S. Siskos, and G. Sarrabayrouse. "Comparison between BSIM4.X and HSPICE flicker noise models in NMOS and PMOS transistors in all operating regions." Microelectronics Reliability 47, no. 8 (2007): 1222–27. http://dx.doi.org/10.1016/j.microrel.2006.09.021.

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Setiabudi, Agung, Hiroki Tamura, and Koichi Tanno. "High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 6 (2018): 4148. http://dx.doi.org/10.11591/ijece.v8i6.pp4148-4156.

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<p>A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and

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Gadlage, Matthew J., Jonathan R. Ahlbin, Balaji Narasimham, Bharat L. Bhuva, Lloyd W. Massengill, and Ronald D. Schrimpf. "Single-Event Transient Measurements in nMOS and pMOS Transistors in a 65-nm Bulk CMOS Technology at Elevated Temperatures." IEEE Transactions on Device and Materials Reliability 11, no. 1 (2011): 179–86. http://dx.doi.org/10.1109/tdmr.2010.2102354.

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Goff, Daniel T., Steve J. A. Majerus, and Walter Merrill. "A 200 °C Quad-Output Buck Type Switched Mode Power Supply IC." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, HITEC (2014): 000022–27. http://dx.doi.org/10.4071/hitec-ta16.

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A high temperature (&gt;200 °C), quad-output, buck type switched-mode power supply (SMPS) IC capable of operating over a wide input supply range of 6 V to 15 V is described. The IC is a compact power supply solution for multi-voltage microprocessors, sensors, and actuators. The SMPS topology is a 112 kHz fixed-frequency, synchronous buck converter with slope compensation. A novel internal feedback design enables the output voltages to be pin-programmed to one of three common supply voltages—5 V, 3.3 V, or 1.8 V—while an external resistor divider can also be used for arbitrary voltage progr

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Hu, Jian Ping, Li Fang Ye, and Li Su. "A New P-Type Clocked Adiabatic Logic for Nanometer CMOS Processes with Gate Oxide Materials." Applied Mechanics and Materials 29-32 (August 2010): 1930–36. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.1930.

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Leakage current is becoming a significant contributor to power dissipations in nanometer CMOS circuits due to the scaling of oxide thickness. This paper proposes a new P-type clocked adiabatic logic (P-CAL) to reduce gate leakage based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones in nanometer CMOS processes using gate oxide materials. Based on the power dissipation models of adiabatic circuits, the estimation technology for the active leakage dissipations of P-CAL circuits is proposed. The active leakage dissipations are estimated by testing

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Hamedi-Hagh, Sotoudeh, and Ahmet Bindal. "Design and Characterization of the Next Generation Nanowire Amplifiers." VLSI Design 2008 (February 3, 2008): 1–5. http://dx.doi.org/10.1155/2008/190315.

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Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd- and 3rd-order harmonic distortions of the amplifier are −40 d

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Francis, Sarah A., Aritra Dasgupta, and Daniel M. Fleetwood. "Effects of Total Dose Irradiation on the Gate-Voltage Dependence of the $\hbox{1}/f$ Noise of nMOS and pMOS Transistors." IEEE Transactions on Electron Devices 57, no. 2 (2010): 503–10. http://dx.doi.org/10.1109/ted.2009.2036297.

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Guo, Benqing, Jun Chen, Hongpeng Chen, and Xuebing Wang. "A 0.1–1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS." Modern Physics Letters B 32, no. 02 (2018): 1850009. http://dx.doi.org/10.1142/s0217984918500094.

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An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 [Formula: see text]m CMOS process, simulated results show that the proposed LNA provi

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Brennan, B., S. McDonnell, D. Zhernokletov, et al. "In Situ Studies of III-V Surfaces and High-K Atomic Layer Deposition." Solid State Phenomena 195 (December 2012): 90–94. http://dx.doi.org/10.4028/www.scientific.net/ssp.195.90.

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Atomic layer deposition (ALD) of high dielectric constant (high-k) materials for ULSI technologies is now widely adopted in Si-based CMOS production. Extending the scaling of integrated circuit technology has now resulted in the investigation of transistors incorporating alternative channel materials, such as III-V compounds. The control of the interfacial chemistry between a high-k dielectric and III-V materials presents a formidable challenge compared to that surmounted by Si-based technologies. The bonding configuration is obviously more complicated for a compound semiconductor, and thus an

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Zhang, Wei Qiang, Yu Zhang, and Jian Ping Hu. "P-Type ECRL Circuits for Gate-Leakage Reduction in Nanometer CMOS Processes with Gate Oxide Materials." Applied Mechanics and Materials 29-32 (August 2010): 1919–24. http://dx.doi.org/10.4028/www.scientific.net/amm.29-32.1919.

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With the decrease of the power supply voltage, the thickness of the gate oxide has been also scaled down in CMOS technologies using gate oxide materials. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. Base on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, this paper propose a P-type efficient charge recovery logic (P-ECRL) to reduce leakage dissipations in nanometer CMOS processes with gate oxide materials. For an examp

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