Academic literature on the topic 'Transistors à nanotube de carbone'

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Journal articles on the topic "Transistors à nanotube de carbone"

1

Cao, Qing, Jerry Tersoff, Damon B. Farmer, Yu Zhu, and Shu-Jen Han. "Carbon nanotube transistors scaled to a 40-nanometer footprint." Science 356, no. 6345 (2017): 1369–72. http://dx.doi.org/10.1126/science.aan2476.

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The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density—above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Fur
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2

Cao, Qing, Shu-Jen Han, Jerry Tersoff, et al. "End-bonded contacts for carbon nanotube transistors with low, size-independent resistance." Science 350, no. 6256 (2015): 68–72. http://dx.doi.org/10.1126/science.aac8006.

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Moving beyond the limits of silicon transistors requires both a high-performance channel and high-quality electrical contacts. Carbon nanotubes provide high-performance channels below 10 nanometers, but as with silicon, the increase in contact resistance with decreasing size becomes a major performance roadblock. We report a single-walled carbon nanotube (SWNT) transistor technology with an end-bonded contact scheme that leads to size-independent contact resistance to overcome the scaling limits of conventional side-bonded or planar contact schemes. A high-performance SWNT transistor was fabri
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3

Hamieh, S. "Improving the RF Performance of Carbon Nanotube Field Effect Transistor." Journal of Nanomaterials 2012 (2012): 1–7. http://dx.doi.org/10.1155/2012/724121.

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Compact model of single-walled semiconducting carbon nanotube field-effect transistors (CNTFETs) implementing the calculation of energy conduction subband minima under VHDLAMS simulator is used to explore the high-frequency performance potential of CNTFET. The cutoff frequency expected for a MOSFET-like CNTFET is well below the performance limit, due to the large parasitic capacitance between electrodes. We show that using an array of parallel nanotubes as the transistor channel combined in a finger geometry to produce a single transistor significantly reduces the parasitic capacitance per tub
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4

Sulpizio, J. A., Z. Z. Bandić, and D. Goldhaber-Gordon. "Nanofabrication of top-gated carbon nanotube-based transistors: Probing electron-electron interactions in one-dimensional systems." Journal of Materials Research 21, no. 11 (2006): 2916–21. http://dx.doi.org/10.1557/jmr.2006.0361.

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Carbon nanotubes are interesting for studying the remarkable electronic properties of one-dimensional (1D) quantum systems. Electron flow in such systems is not described by Fermi liquid theory—restricted dimensionality leads to the appearance of collective excitations—or Luttinger liquid behavior. Previous studies have probed Luttinger liquid behavior by tunneling into or between one-dimensional systems. We propose to extend these studies by using narrow top gates to introduce tunable tunnel barriers within nanotubes. We report on the scalable fabrication of carbon nanotube-based transistors
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5

Xu, Yao, Ashok Srivastava, and Ashwani K. Sharma. "Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance." VLSI Design 2010 (February 17, 2010): 1–8. http://dx.doi.org/10.1155/2010/864165.

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Current transport and dynamic models of carbon nanotube field-effect transistors are presented. A model of single-walled carbon nanotube as interconnect is also presented and extended in modeling of single-walled carbon nanotube bundles. These models are applied in studying the performances of circuits such as the complementary carbon nanotube inverter pair and carbon nanotube as interconnect. Cadence/Spectre simulations show that carbon nanotube field-effect transistor circuits can operate at upper GHz frequencies. Carbon nanotube interconnects give smaller delay than copper interconnects use
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6

YOUSEFI, REZA. "THE EFFECT OF CARBON NANOTUBE CHIRALITY ON THE PERFORMANCE OF THE STRAINED TUNNELING CARBON NANOTUBE FETs." Modern Physics Letters B 26, no. 03 (2012): 1150019. http://dx.doi.org/10.1142/s0217984911500199.

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In this paper, using the non-equilibrium Green's function formalism (NEGF), the effect of the chirality of carbon nanotube (CNT) on the performance of the strained tunneling carbon nanotube field effect transistors (T-CNTFETs) has been investigated. In this work, all evaluations are done by this assumption that the ON current, I ON , is the main performance metric in the T-CNTFETs. The uniaxial strain has been considered in this work. On the other hand, for constructing a transistor with a desired I ON , a variety of CNTs with the appropriate uniaxial strain could be used. The results of doing
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7

Шарапов, А. А. "КОНТАКТНЫЕ ЯВЛЕНИЯ В ПОЛЕВЫХ НАНОТРАНЗИСТОРАХ НА ОСНОВЕ УГЛЕРОДНЫХ НАНОТРУБОК". NANOINDUSTRY Russia 96, № 3s (2020): 758–60. http://dx.doi.org/10.22184/1993-8578.2020.13.3s.758.760.

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В настоящее время актуальна задача поиска и исследования новых материалов для формирования полевых транзисторов с характерной длиной канала менее 5 нм, обеспечивающих выполнение необходимых требований по энергопотреблению и быстродействию. В работе обоснована важность рассмотрения нанотранзисторов на основе углеродных нанотрубок в качестве конкурирующих приборов по отношению к полевым транзисторам на основе традиционных материалов. Определены необходимые параметры углеродных нанотрубок, позволяющие использовать структуры на их основе для формирования наноразмерных транзисторов. Рассмотрены мет
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8

Chikkadi, Kiran, Matthias Muoth, Cosmin Roman, Miroslav Haluska, and Christofer Hierold. "Advances in NO2 sensing with individual single-walled carbon nanotube transistors." Beilstein Journal of Nanotechnology 5 (November 20, 2014): 2179–91. http://dx.doi.org/10.3762/bjnano.5.227.

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The charge carrier transport in carbon nanotubes is highly sensitive to certain molecules attached to their surface. This property has generated interest for their application in sensing gases, chemicals and biomolecules. With over a decade of research, a clearer picture of the interactions between the carbon nanotube and its surroundings has been achieved. In this review, we intend to summarize the current knowledge on this topic, focusing not only on the effect of adsorbates but also the effect of dielectric charge traps on the electrical transport in single-walled carbon nanotube transistor
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9

DAI, HONGJIE, ALI JAVEY, ERIC POP, DAVID MANN, WOONG KIM, and YUERUI LU. "ELECTRICAL TRANSPORT PROPERTIES AND FIELD EFFECT TRANSISTORS OF CARBON NANOTUBES." Nano 01, no. 01 (2006): 1–13. http://dx.doi.org/10.1142/s1793292006000070.

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This paper presents a review on our recent work on carbon nanotube field effect transistors, including the development of ohmic contacts, high-κ gate dielectric integration, chemical functionalization for conformal dielectric deposition and pushing the performance limit of nanotube FETs by channel length scaling. Due to the importance of high current operations of electronic devices, we also review the high field electrical transport properties of nanotubes on substrates and in freely suspended forms. Owing to their unique properties originating from their crystalline 1D structure and the stro
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10

GHADIRY, MAHDIAR, MAHDIEH NADI, HOSEIN MOHAMMADI, and ASRULNIZAM BIN ABD MANAF. "ANALYSIS OF A NOVEL FULL ADDER DESIGNED FOR IMPLEMENTING IN CARBONE NANOTUBE TECHNOLOGY." Journal of Circuits, Systems and Computers 21, no. 05 (2012): 1250042. http://dx.doi.org/10.1142/s0218126612500429.

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A novel low power-delay product full adder circuit is presented in this paper. A new approach is used in order to design full-swing full adder with low number of transistors. The proposed full adder is implemented in MOSFET-like Carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that, there are substantial improvements in both power and performance of the proposed circuit compared to latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to estimate the advan
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