Relevant bibliographies by topics / Transistors MOSFET

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Academic literature on the topic 'Transistors MOSFET'

Author: Grafiati
Published: 4 June 2021
Last updated: 19 April 2025

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Journal articles on the topic "Transistors MOSFET"

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Hebali, Mourad, Menaouer Bennaoum, Mohammed Berka, Abdelkader Baghdad Bey, Mohammed Benzohra, Djilali Chalabi, and Abdelkader Saidane. "A high electrical performance of DG-MOSFET transistors in 4H-SiC and 6H-SiC 130 nm technology by BSIM3v3 model." Journal of Electrical Engineering 70, no. 2 (April 1, 2019): 145–51. http://dx.doi.org/10.2478/jee-2019-0021.

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Abstract In this paper, the electrical performance of double gate DG-MOSFET transistors in 4H-SiC and 6H-SiC technologies have been studied by BSIM3v3 model. In which the I–V and gm–V characteristics and subthreshold operation of the DGMOSFET have been investigated for two models (series and parallel) based on equivalent electronic circuits and the results so obtained are compared with the single gate SG-MOSFET, using 130 nm technology and OrCAD PSpice software. The electrical characterization of DG-MOSFETs transistors have shown that they operate under a low voltage less than 1.2 V and low power for both models like the SG-MOSFET transistor, especially the series DG-MOSFET transistor is characterized by an ultra low power. The different transistors are characterized by an ultra low OFF leakage current of pA order, very high ON/OFF ratio of and high subthreshold slope of order 0.1 V/dec for the transistors in 6H-SiC and 4H-SiC respectively. These transistors also proved higher transconductance efficiency, especially the parallel DG-MOSFET transistor.
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He, Xibin. "The Advantages and Applications of IGBT Compared with Conventional BJT and MOSFET." Journal of Physics: Conference Series 2386, no. 1 (December 1, 2022): 012054. http://dx.doi.org/10.1088/1742-6596/2386/1/012054.

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Abstract Nowadays, the power semiconductor devices have been used in many fields like wind power generation systems, the rail transit. Bipolar junction transistors (BJTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) as well as some other devices are the dominating the market. The insulated gate bipolar transistor (IGBT) as a mixed device of the BJT and the MOSFET, has a preeminent performance. In this paper, the characteristics of the punch through IGBT (PT-IGBT), the MOSFET and the BJT will be investigated by TCAD. Then the PT-IGBT is compared with the BJT and the MOSFET, for concluding its advantages. According to the simulation result, the PT-IGBT has the on-state current of 9*10-4A and the forward blocking voltage of 1200V, which are much higher than the other two devices. In the end of the paper, the development of the semiconductor devices is predicted, about the research trends.
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Chek Yee, Ooi, Mok Kai Ming, and Wong Pei Voon. "DEVICE AND CIRCUIT LEVEL SIMULATION STUDY OF NOR GATE LOGIC FAMILIES DESIGNED USING NANO-MOSFETs." Platform : A Journal of Science and Technology 4, no. 1 (May 31, 2021): 73. http://dx.doi.org/10.61762/pjstvol4iss1art11064.

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The investigation of silicon-based nano-MOSFETs logic circuits is helpful to gain more comprehensive knowledge about nanoscale transistors. Therefore, a simulation study has been performed on four logic families of two inputs NOR gate logic circuits, namely (i) nano-CMOS NOR gate, (ii) nano-MOSFET loaded n-type nano-MOSFET NOR gate, (iii) 733.8 Ω resistive loaded nano-MOSFET NOR gate, and finally (iv) pseudo-n-type nano-MOSFET NOR gate. The nano-MOSFET technology node studied in this paper is 10 nm. Device simulation is done using an online NanoMOS simulator, whereas circuit simulation is carried out using freeware WinSpice. The main obstacle encountered during downscaling of nano-MOSFETs is low power dissipation and high-speed nano-MOSFET logic circuits. Correct logical NOR operation has been proven by observing simulated timing waveforms. Transient timing analysis on nano-MOSFET loaded n-type nano-MOSFET NOR gate has shown that propagation delays calculated from theory and simulation are 66% matched. From the analysis, this 10 nm nano-MOSFET NOR logic circuit design exhibit a dynamic power reduction of 148 times and a propagation delay improvement of 33 times when benchmarked against a typical 120 nm MOSFET logic circuit. Keywords: nano transistor, electrical characteristics, channel length, channel width, benchmarking, power, speed
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Guran, Ionuț-Constantin, Adriana Florescu, and Lucian Andrei Perișoară. "A Novel ON-State Resistance Modeling Technique for MOSFET Power Switches." Mathematics 11, no. 1 (December 25, 2022): 72. http://dx.doi.org/10.3390/math11010072.

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Nowadays, electronic circuits’ time to market is essential, with engineers trying to reduce it as much as possible. Due to this, simulation has become the main testing concept used in the electronics domain. In order to perform the simulation of a circuit, a behavioral model must be created. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are semiconductor devices found in a multitude of electronic circuits, and they are also used as power switches in many applications, such as low-dropout linear voltage regulators, switching regulators, gate drivers, battery management systems, etc. A MOSFETs’ behavior is extremely complex to model, thus, creating high-performance models for these transistors is an imperative condition in order to emulate the exact real behavior of a circuit using them. An essential parameter of MOSFET power switches is the ON-state resistance (RDSON), because it determines the power losses during the ON state. Ideally, the power losses need to be zero. RDSON depends on multiple factors, such as temperature, load current, and gate-to-source voltage. Previous studies in this domain focus on the modeling of the MOSFET only in specific operating points, but do not cover the entire variation range of the parameters, which is critical for some applications. For this reason, in this paper, there was introduced for the first time a novel ON-state resistance modeling technique for MOSFET Power Switches, which solves the entire RDSON dependency on the transistor’s variables stated above. The novel RDSON modeling technique is based on modulating the transistor’s gate-to-source voltage such that the exact RDSON value is obtained in each possible operating point. The method was tested as a real-life example by creating a behavioral model for an N-channel MOSFET transistor and the chosen simulation environment was Oregon, USA, Computer-Aided Design (OrCAD) capture. The results show that the model is able to match the transistor’s RDSON characteristics with a maximum error of 0.8%. This is extremely important for applications in which the temperatures, voltages, and currents vary over a wide range. The new proposed modeling method covers a gap in the behavioral modeling domain, due to the fact that, until now, it was not possible to model the RDSON characteristics in all operating corners.
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Gowthaman, Naveenbalaji, and Viranjay Srivastava. "Analysis of <i>InN/La<sub>2</sub>O<sub>3</sub></i> Twosome for Double-Gate MOSFETs for Radio Frequency Applications." Materials Science Forum 1048 (January 4, 2022): 147–57. http://dx.doi.org/10.4028/www.scientific.net/msf.1048.147.

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The channel material of a gate describes the operating condition of the MOSFET. A suitable operating condition prevails in MOSFETs if the transistors are quite enough to observe and control at the nanometer regime. An efficient gate and channel material have been proposed in this work which is based on the electrical properties they exhibit at the temperature of 300K. The doping concentration for the electrons and holes is maintained to be 1Χ1019cm-3 for the entire electronic simulator. The simulation results show that using La2O3 along with Indium Nitride (InN) material for the designing of Double-Gate (DG) MOSFETs provides better controllability over the transistor at a channel length of 50nm. This proposed DG-MOSFET is more compliant than the conventional coplanar MOSFETs based on Silicon.
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Cha, Kyuhyun, and Kwangsoo Kim. "Asymmetric Split-Gate 4H-SiC MOSFET with Embedded Schottky Barrier Diode for High-Frequency Applications." Energies 14, no. 21 (November 4, 2021): 7305. http://dx.doi.org/10.3390/en14217305.

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4H-SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) with embedded Schottky barrier diodes are widely known to improve switching energy loss by reducing reverse recovery characteristics. However, it weakens the static characteristics such as specific on-resistance and breakdown voltage. To solve this problem, in this paper, an Asymmetric 4H-SiC Split Gate MOSFET with embedded Schottky barrier diode (ASG-MOSFET) is proposed and analyzed by conducting a numerical TCAD simulation. Due to the asymmetric structure of ASG-MOSFET, it has a relatively narrow junction field-effect transistor width. Therefore, despite using the split gate structure, it effectively protects the gate oxide by dispersing the high drain voltage. The Schottky barrier diode (SBD) is also embedded next to the gate and above the Junction Field Effect transistor (JFET) region. Accordingly, since the SBD and the MOSFET share a current path, the embedded SBD does not increase in RON,SP of MOSFET. Therefore, ASG-MOSFET improves both static and switching characteristics at the same time. As a result, compared to the conventional 4H-SiC MOSFET with embedded SBD, Baliga′s Figure of Merit is improved by 17%, and the total energy loss is reduced by 30.5%, respectively.
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Kunov, Georgi, Tihomir Brusev, and Elissaveta Gadjeva. "Power losses in the MOSFET transistors of switching-mode converters." IOP Conference Series: Materials Science and Engineering 1298, no. 1 (December 1, 2023): 012019. http://dx.doi.org/10.1088/1757-899x/1298/1/012019.

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Abstract The power losses in the MOSFET transistors of switching-mode converters are investigated and analyzed. The results presented in this paper are achieved using software Cadence OrCAD. The simulation model suitable for estimation of energy dissipations in MOSFET transistors is proposed. The power losses as a function of different circuit’s parameters, like switching frequency, power supply voltage and output current are evaluated. The PSpice model of MOSFET transistor “BSC020N03MS” of the company Infineon is used in the presented analysis. Control circuit, which realize the adaptive deadtime (ADT) control technique depending on the load current, is applied to reduce the switching power losses in the MOSFET transistor. Thus, the efficiency of the switching-mode converters can be increased.
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Bogatyrev, Yu V., D. A. Aharodnikau, S. B. Lastovsky, A. V. Ket’ko, M. M. Krechko, S. V. Shpakovsky, P. V. Rubanov, G. A. Protopopov, and P. A. Chubunov. "Influence of ionizing radiation on the parameters of p-channel MOS transistors." Proceedings of the National Academy of Sciences of Belarus, Physical-Technical Series 67, no. 4 (January 2, 2023): 402–8. http://dx.doi.org/10.29235/1561-8358-2022-67-4-402-408.

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The results of experimental studies of the influence of gamma radiation Co60 on the basic parameters of silicon epitaxial-planar p-channel MOSFET transistors under different electrical modes are presented. Transistors were manufactured according to radiation-resistant DMOS technology with design standards of 1.4 μm. As a result of transistor studies, it was established that the values of all basic parameters after the radiation dose D = 106 rads (SiO2) in active electrical irradiation modes remained within the limits of the performance criteria; the parameter, most sensitive to influence of a dose of irradiation by gamma-quanta is the threshold voltage; in the passive electrical irradiation mode the transistor’s radiations resistance in all parameters corresponds to a dose of 2,8·106 rads (SiO2). A sufficiently high radiation resistance of the studied p-channel MOSFETs makes it possible to recommend them for use in aviation and space equipment. The different degrees of radiation degradation of the studied parameters during irradiation are due to their dependence either on the effects of ionization in the layers of sub-gate and insulating dielectrics, or structural damage in the bulk silicon of the transistor active regions. The high radiation resistance of the studied p-channel MOSFETs allows recommending them for use in aviation and space equipment.
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Taberkit, Amine Mohammed, Ahlam Guen-Bouazza, and Benyounes Bouazza. "Modeling and Simulation of Biaxial Strained P-MOSFETs: Application to a Single and Dual Channel Heterostructure." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (February 1, 2018): 421. http://dx.doi.org/10.11591/ijece.v8i1.pp421-428.

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The objectives of this work are focused on the application of strained silicon on MOSFET transistor. To do this, impact and benefits obtained with the use of strained silicon technology on p-channel MOSFETs are presented. This research attempt to create conventional and two-strained silicon MOSFETs fabricated from the use of TCAD, which is a simulation tool from Silvaco. In our research, two-dimensional simulation of conventional MOSFET, biaxial strained PMOSFET and dual channel strained P-MOSFET has been achieved to extract their characteristics. ATHENA and ATLAS have been used to simulate the process and validate the electronic characteristics. Our results allow showing improvements obtained by comparing the three structures and their characteristics. The maximum of carrier mobility improvement is achieved with percentage of 35.29 % and 70.59 % respectively, by result an improvement in drive current with percentage of 36.54 % and 236.71 %, and reduction of leakage current with percentage of 59.45 % and 82.75 %, the threshold voltage is also enhaced with percentage of: 60 % and 61.4%. Our simulation results highlight the importance of incorporating strain technology in MOSFET transistors.
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Cho, Geunho. "A Study on the Design Method of Hybrid MOSFET-CNTFET Based SRAM – A Secondary Publication." Journal of Electronic Research and Application 8, no. 1 (February 20, 2024): 106–12. http://dx.doi.org/10.26689/jera.v8i1.6115.

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More than 10,000 carbon nanotube field-effect transistors (CNTFETs) have been successfully integratedinto one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Thesetransistors offer advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, andtransparency. The three-dimensional multilayer structure of the CNTFET semiconductor chip, along with ongoing researchin CNTFET manufacturing processes, increases the potential for creating a hybrid MOSFET-CNTFET semiconductorchip. This chip combines conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and CNTFETs inone integrated system. This paper discusses a methodology to design 6T binary static random-access memory (SRAM)using a hybrid MOSFET-CNTFET. This paper introduces a method for designing a hybrid MOSFET-CNTFET SRAMby leveraging existing MOSFET SRAM or CNTFET SRAM design approaches. Additionally, this paper compares itsperformance with conventional MOSFET SRAM and CNTFET SRAM designs.
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Dissertations / Theses on the topic "Transistors MOSFET"

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Bakhtiar, Hazri CHARLES JEAN PIERRE. "CARACTERISATION DE STRUCTURES MOS SUBMICRONIQUES ET ANALYSE DE DEFAUTS INDUITS PAR IRRADIATION GAMMA. EXTRAPOLATION AUX DEFAUTS INDUITS DANS LES OXYDES DE CHAMP DES TRANSISTORS BIPOLAIRES /." [S.l.] : [s.n.], 1999. ftp://ftp.scd.univ-metz.fr/pub/Theses/1999/Bakhtiar.Hazri.SMZ9934.pdf.

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Guérin, Chloé. "Etude de la dégradation par porteurs chauds des technologies CMOS avancées en fonctionnement statique et dynamique." Aix-Marseille 1, 2008. http://www.theses.fr/2008AIX11041.

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La miniaturisation des dernières technologies s’est effectuée à tension d’alimentation quasi constante. Cela se traduit par une augmentation du champ latéral du transistor MOSFET. Un risque important réapparaît en terme de fiabilité : la dégradation par porteurs chauds (HC). Pour garantir le meilleur compromis entre fiabilité et performance, il est important de comprendre toutes les causes physiques de la dégradation par porteurs chauds. Grâce à une étude menée pour des conditions de polarisation et de température variées, sur différentes épaisseurs d’oxyde et longueurs de canal, nous avons mis en place un formalisme physique s’appuyant à la fois sur l’énergie et le nombre de porteurs. Cette double dépendance se traduit par une compétition entre trois modes de dégradations, dominant chacun à leur tour en fonction de la gamme d’énergie des porteurs. A forte énergie, la dégradation s’explique par l’interaction d’un seul porteur avec une liaison Si-H (mode 1). Mais quand l’énergie des porteurs diminue, leur nombre est prépondérant tout d’abord pour l’interaction entre porteurs EES (mode 2) et surtout à très basse énergie, où nous avons montré que la dégradation peut être importante à cause d’interactions multiples entre les « porteurs froids » du canal et les liaisons d’interface (mode 3). On parle alors d’excitation multivibrationnelle des liaisons. Ce nouveau modèle assure une meilleure extrapolation de la durée de vie dans les conditions nominales. Appliqué à la dégradation sous signaux digitaux, il permet une estimation rigoureuse du rapport entre les dégradations en courant alternatif et continu (AC-DC) ainsi que l’élaboration de nouvelles consignes concernant les effets de fréquence, de charge et de temps de montée des signaux. Enfin, intégré au simulateur de Design-in Reliability, il autorise une simulation précise de la dégradation par porteurs chauds de blocs de circuits
In the last technologies, dimension reduction is performed at constant bias which means an increase of the MOSFET lateral electrical field. Reliability risks in term of hot carriers are coming back. It is very important to understand the hot carrier degradation physical root causes to insure the best compromise between performance and reliability. After studying numerous stress biases, temperatures, oxide thicknesses and lengths, we established a new physical formalism based on both carrier energy and number. This double effect translates in a three degradation mode competition dominated by each of the modes depending on the energy range. At high energy, the degradation is due to a single carrier interaction with Si-H bonds (mode 1). But when the energy decreases, carrier number begins to dominate first trough Electron-Electron interactions (mode 2) and particularly at very low energy where we put forward that degradation increases due to bond multiple vibrational excitation with cold carriers (mode 3). This new modelling allows a better lifetime extrapolation at nominal biases. Applied to degradation under digital signals, it also enables a rigorous estimation of the degradation ratio between alternative and continuous current (AC-DC). Then new design guidelines concerning frequency, fanOut and rise time have been evidenced. Finally, this new modelling is now included in Design-in Reliability simulators to know precisely circuit bloc hot carrier degradation
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Munteanu, Daniela. "Modélisation et caractérisation des transistors SOI : du pseudo-MOSFET au MOSFET submicronique ultramince." Grenoble INPG, 1999. http://www.theses.fr/1999INPG0104.

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L'objet de cette these est de contribuer a l'analyse et a l'optimisation des materiaux soi et au developpement de modeles physiques et de methodes de caracterisation adaptees aux dispositifs soi. Dans le premier chapitre, nous rappelons l'interet de la technologie soi, ses avantages et ses inconvenients par rapport a la technologie si massif. Le deuxieme chapitre est consacre a la caracterisation du materiau, en utilisant la technique -mosfet, methode tres appropriee pour comparer la qualite et les parametres electriques des differentes structures soi. Une analyse approfondie de la validite de cette technique est realisee par simulation numerique. La technique -mosfet est ensuite appliquee a l'analyse de plusieurs materiaux soi et de certains procedes technologiques. Le troisieme chapitre porte sur la caracterisation des dispositifs soi finis, avec une etude detaillee du fonctionnement en haute et basse temperature. Nous presentons une analyse de transistors soi ultimes : (a) le fonctionnement en basse temperature du dt-mos est etudie experimentalement et ses avantages par rapport aux structures classiques sont mis en evidence ; (b) des mesures sur des tmos ultra-minces demontrent leur fonctionnalite ainsi que l'impact de mecanismes physiques particuliers (inversion volumique, fort couplage des interfaces, effets quantiques). Le quatrieme chapitre est consacre a l'analyse et a la modelisation des mecanismes transitoires dans les tmos/soi. Differents types de transitoires du courant de drain (overshoot et undershoot, simple et double grille) sont mesures et simules avec atlas et soi-spice. Ces phenomenes sont utilises a l'extraction de la duree de vie des porteurs, parametre essentiel qui reflete la qualite du film soi.
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Rigaud, Fabrice. "Etude et conception des structures de test et méthodes d'analyse pour les technologies CMOS." Aix-Marseille 1, 2010. http://www.theses.fr/2010AIX1A083.

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Dans la course à la réduction des tailles de transistor, il devient de plus en plus difficile d'obtenir de bons rendements. Le but de cette thèse est de proposer des outils pour accélérer la montée en rendement des technologies CMOS. Ces outils passent par la conception de structures de test, associées à des méthodes de test et d'analyse de résultat. Trois types de structure sont ainsi étudiés : des TEG logiques, une macro-cellule de test et une TEG hybride. Les TEG logiques étudiées sont composées de chaines d'inverseurs et permettent ainsi de détecter les défauts et les variations du procédé de fabrication. La macro-cellule de test étudiée comporte un plan mémoire SRAM qui est capable d'osciller. Le mode mémoire SRAM permet de détecter et de localiser des défauts présents sur le plan mémoire. Le mode oscillation permet, grâce à différentes configurations d'interconnections des points mémoire, de caractériser les variations du procédé de fabrication. La dernière structure proposée est une TEG hybride composée de plusieurs oscillateurs en anneau avec différentes configurations de layout. Un bloc numérique est également implémenté, permettant de mesurer des fréquences d'oscillations jusqu'à 1,5GHz et de les restituer sur une sortie numérique. Une méthodologie d'analyse est alors développée dans le but d'obtenir les valeurs de paramètres préalablement choisis en fonction des fréquences d'oscillation. La méthode est dans un premier temps validée par simulation. Puis quelques plaquettes embarquant la TEG sont testées. Le test montre que l' apprentissage réalisé par simulation doit être reproduit sur silicium pour obtenir les résultats attendus
Because of the constant transistors size reduction, it becomes more and more difficult to obtain good yields. The aim of this work is to propose tools to speed up the yield ramp up of CMOS technologies. These tools consist of test circuit design, combined with test and analysis methods. Three kinds of test structure are analyzed in this work: logic TEG, a test macro-cell and a hybrid TEG. The analyzed logic TEG are compound of inverter chains and allow to detect defects and process variations. Defects can also be localized in order to ease their analysis. The test macro-ceIl studied contains an "oscillating" SRAM memory array which is able to oscillate. The SRAM mode allows detecting and localizing of defects present on the memory array. In comparison with logic TEG, the probability to catch defects is more important thanks to the structure size. The oscillating mode allows, thanks to different interconnection configurations of memory cells, to characterize process variations. The last proposed structure is a hybrid TEG which consists of several ring oscillators with different layout configurations. A numeric bloc is also embedded, allowing to measure oscillating frequencies up to 1. 5GHz and to restitute them on a numeric output. An analysis method is then developed in order to retrieve values of parameters previously chosen as a function of oscilIating frequencies. Ln a fust time, the method is validated by simulation. Then, some wafers with the TEG embedded on are tested. The test shows tbat the learning performed by simulation has to be executed on silicon to obtain expected results
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Tsormpatzoglou, Andreas. "Caractérisation et modélisation des composants MOS à multiples grilles nanométriques." Grenoble INPG, 2009. http://www.theses.fr/2009INPG0143.

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La thèse s'est développée autour de deux axes majeurs concernant des transistors MOS multi-grilles : i) le développement de modèles analytiques compacts décrivant la distribution du potentiel le long du canal et toutes les autres grandeurs caractéristiques du transistor ii) le développement de modèles analytiques compacts décrivant des caractéristiques de transfert d'un transistor DG et d’un transistor cylindrique gate-all-around iii) l'étude expérimentale et théorique à l'aide de simulations 3D d'un MOSFET multi-grille particulier, le FinFET. Plus particulièrement, les courants de fuites de grille et de drain sous le seuil ont été étudiés expérimentalement pour les FinFETs à triple grille. L'origine des courants de fuites de grille et de drain, ainsi que leur dépendance avec les caractéristiques géométriques du transistor ont été étudiées
The subject of the PhD is focused on theoretical and experimental studies ofnanoscale multi-gate Metal Oxide Semiconductor Field Effect Transistors. The theoretical part is orientated towards the derivation of analytical expressions for the potential distribution within the channel of the transistors, from which characteristic parameters ofthe transistors are derived. The final aim of the work is to obtain analytical compact expressions for the drain current, valid in aH regions of operation. First, symmetrical Double-Gate MOSFETs are studied, whereas the study of all other types of multi-gate MOSFETs (triple-gate and gate-all-around) is based on the derived model of DG MOSFETs. For the experimental part, the transfer characteristics of single-FinFETs and 5-FinFETs were measured at room temperature. For analysis of the experimental data, numerical simulations were performed to verify the theoretical speculations and optimize the device performance
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Yojo, Leonardo Shimizu. "Estudo, caracterização elétrica e modelagem de transistores BE (Back Enhanced) SOI MOSFET." Universidade de São Paulo, 2018. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-04052018-150633/.

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Este trabalho tem como objetivo o estudo, caracterização elétrica e modelagem do novo transistor desenvolvido e fabricado no Laboratório de Sistemas Integráveis (LSI) da Universidade de São Paulo (USP) chamado BE (Back Enhanced) SOI MOSFET. Trata-se de um dispositivo inovador que se destaca principalmente pela sua facilidade de fabricação (exigindo apenas processos bem conhecidos e nenhuma etapa de dopagem do semicondutor) e sua flexibilidade quanto ao modo de operação (pode atuar como um transistor MOS tipo n ou um transistor MOS tipo p, dependendo somente da polarização de substrato). Aplicando-se tensão no substrato (VGB) é possível formar um canal de elétrons (VGB>0) ou lacunas (VGB<0) na segunda interface da camada de silício, por onde a corrente entre fonte e dreno flui. Sua patente foi requerida junto ao INPI (Instituto Nacional da Propriedade Industrial) sob o número BR 10 2015 020974 6. Foram realizadas medidas elétricas e simulações numéricas para melhor compreender seu princípio de funcionamento e as características que tornam possível sua reconfigurabilidade. Duas fabricações distintas deste tipo de dispositivo foram analisadas. Além das espessuras distintas, a principal diferença entre elas é o metal utilizado nos eletrodos de fonte e dreno, sendo alumínio na primeira e níquel na segunda versão. O alumínio utilizado na primeira versão resultou em contatos Ôhmicos após o processamento térmico das lâminas, que favoreceram o funcionamento do dispositivo como transistor tipo p, devido à natureza do material utilizado. A análise em função da temperatura (de 25ºC até 125ºC) mostrou uma variação da tensão de limiar (até 1,52mV/ºC) e uma degradação da mobilidade dos portadores de carga (analisado através da transcondutância), resultando no surgimento de um ponto invariante com a temperatura, o chamado ZTC (Zero Temperature Coefficient). Já a segunda versão possui contatos Schottky, na qual foram obtidos níveis de corrente apreciáveis tanto para transistores tipo n (na ordem de nA para as condições de polarização utilizadas), quanto para transistores tipo p (na ordem de ?A). O comportamento da curva de corrente de dreno deste dispositivo apresentou uma estabilização a partir de determinado valor de tensão de porta. A partir deste ponto o BE SOI MOSFET deixa de atuar como um transistor convencional e passa a ter sua corrente de dreno proporcional a tensão de substrato. Medidas em função da temperatura nesta segunda versão permitiram comparar os resultados com os da primeira versão. Percebeu-se a ausência do ponto de ZTC, uma vez que foi observado o aumento da corrente devido à diminuição da resistência dos contatos de fonte e dreno para temperaturas mais elevadas. Por fim, a operação de um circuito inversor utilizando o BE SOI MOSFET foi implementada, mesmo quando alternando os tipos dos transistores, comprovando a flexibilidade de funcionamento dos transistores ao mudar seu tipo em função da polarização de substrato.
The aim of this work is the study, the electrical characterization and the modeling of the new transistor that was developed and fabricated in the Laboratório de Sistemas Integráveis (LSI) at University of Sao Paulo (USP). It was named BE (Back Enhanced) SOI MOSFET. This innovative device has the advantage of a simple fabrication (only well-known processes are required to build it and there is no need of any doping step) and it has a reconfigurable operation (it can act as a n-type MOS transistor or as a ptype MOS transistor depending only on substrate bias). The substrate voltage (VGB) is responsible for the formation of an electron (VGB>0) or a hole (VGB<0) channel at the back interface of the silicon, where the drain current flows. The patent for it was required at the National Industrial Property Institute under the number BR 10 2015 020974 6. Electrical measurements and numerical simulations were performed to better understand its functioning principle and the characteristics that enable its reconfigurability. Two different fabrication splits were analyzed. Beside their thicknesses, the main difference between them is the drain and source metal electrode (aluminum in the first split and nickel in the second one). The one with aluminum electrodes resulted in Ohmic contacts after thermal processing, that favored the formation on the p-type transistor because of the nature of the used element. It was observed a variation of the threshold voltage (up to 1.52mV/ºC) and a mobility degradation (seen through the transconductance behavior) as a function of the temperature (from 25ºC to 125ºC), resulting in a zero-temperature coefficient (ZTC) bias point in this device. In this bias condition point, the drain current is almost constant as a function of the temperature, which is a good characteristic especially for analog circuits. The second split has Schottky drain and source contacts, in which appreciable current levels were obtained for both n-type transistors (order of magnitude of nA in the measured bias conditions) and p-type transistors (order of magnitude of ?A). The drain current of this device showed a particular behavior where the drain current stabilizes from a certain gate voltage. In this condition, the BE SOI MOSFET does not act as a conventional transistor anymore and its current is proportional to the substrate bias. Measurements as a function of the temperature were performed in the device too. It was observed an increase of the drain current, differently from the first split, due to the reduction of the source and drain contacts resistances as a function of the temperature. This resulted in the absence of the ZTC point. Finally, the operation of an inverter circuit using BE SOI MOSFET transistors was implemented, even if the type of the transistors were switched. This result shows the flexibility of operation of the transistor, in other words, it is possible to change its type as a function of the substrate bias.
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Lin, Xinnan. "Double gate MOSFET technology and applications /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LIN.

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李華剛 and Eddie Herbert Li. "Narrow-channel effect in MOSFET." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1990. http://hub.hku.hk/bib/B31209312.

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Peters, Chris (Christopher Joseph) Carleton University Dissertation Engineering Electrical. "MOSFET based gamma radiation detector." Ottawa, 1992.

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Lallement, Christophe. "Modèle analytique à une dimension du transistor MOSFET de puissance prenant en compte les interactions thermoélectriques /." Paris : École nationale supérieure des Télécommunications, 1994. http://catalogue.bnf.fr/ark:/12148/cb35706674x.

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Books on the topic "Transistors MOSFET"

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Taylor, B. E. Power Mosfet design. Chichester, W. Sussex, England: Wiley, 1993.

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Baliga, B. Jayant. Advanced power MOSFET concepts. New York: Springer, 2010.

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Cherem, Schneider Márcio, ed. MOSFET modeling for circuit analysis and design. Singapore: World Scientific, 2007.

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Warner, R. M. MOSFET theory and design. New York: Oxford University Press, 1999.

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Cheng, Yuhua. MOSFET modeling & BSIM3 user's guide. New York: Kluwer Academic Publishers, 2002.

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Cheng, Yuhua. MOSFET modeling & BSIM3 user's guide. Boston: Kluwer Academic Publishers, 1999.

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Chenming, Hu, ed. MOSFET modeling & BSIM3 user's guide. Boston: Kluwer Academic Publishers, 1999.

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Hänsch, W. The drift diffusion equation and its applications in MOSFET modeling. Wien: Springer-Verlag, 1991.

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Hänsch, W. The drift diffusion equation and its applications in MOSFET modeling. Wien: Springer-Verlag, 1991.

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Foty, D. MOSFET modeling with SPICE: Principles and practice. Upper Saddle River, NJ: Prentice Hall PTR, 1997.

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Book chapters on the topic "Transistors MOSFET"

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Sivasankaran, K., and Partha Sharathi Mallick. "Radio Frequency Stability Performance of DG MOSFET." In Multigate Transistors for High Frequency Applications, 25–33. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-0157-9_3.

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Rauf, S. Bobby. "DC Circuit Analysis, Diodes, and Transistors – BJT, MOSFET, and IGBT." In Electrical Engineering Fundamentals, 47–86. First edition. | Boca Raton : CRC Press, 2021.: CRC Press, 2020. http://dx.doi.org/10.1201/9780429355233-2.

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Lallement, C., R. Bouchakour, and T. Maurel. "Modeling of Power Mosfet and Bipolar Transistors Taking into Account the Thermoelectrical Interactions." In Modeling in Analog Design, 121–43. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2333-8_5.

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Asadi, Farzin. "MOSFET Transistor Amplifiers." In Analog Electronic Circuits Laboratory Manual, 79–86. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-25122-1_3.

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N. Makarov, Sergey, Reinhold Ludwig, and Stephen J. Bitar. "MOS Field-Effect Transistor (MOSFET)." In Practical Electrical Engineering, 919–72. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-21173-2_18.

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Kolawole, Michael Olorunfunmi. "MOS Field-Effect Transistor (MOSFET) Circuits." In Electronics, 173–204. First edition. | Boca Raton, FL : CRC Press, 2020.: CRC Press, 2020. http://dx.doi.org/10.1201/9781003052913-5.

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Evstigneev, Mykhaylo. "Metal–Oxide–Semiconductor Field Effect Transistor (MOSFET)." In Introduction to Semiconductor Physics and Devices, 233–55. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-08458-4_10.

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Asadi, Farzin. "Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET)." In ABCs of Electronics, 123–31. Berkeley, CA: Apress, 2024. http://dx.doi.org/10.1007/979-8-8688-0134-1_8.

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Costa, Julio, Mike Carroll, G. Ali Rezvani, and Tom McKay. "Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)." In RF and Microwave Passive and Active Technologies, 18–1. Boca Raton: CRC Press, 2018. https://doi.org/10.1201/9781315221854-21.

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Langevelde, R. van, and G. Gildenblat. "PSP: An advanced surface-potential-based MOSFET model." In TRANSISTOR LEVEL MODELING FOR ANALOG/RF IC DESIGN, 29–66. Dordrecht: Springer Netherlands, 2006. http://dx.doi.org/10.1007/1-4020-4556-5_2.

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Conference papers on the topic "Transistors MOSFET"

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Lee, Sunah, Jihoon Son, Jihoon Park, Bohyeon Jeon, Seokmin Yun, Chaesoo Kim, Hagyeong Kwon, et al. "The Advanced Failure Analysis Methods Based on Dynamic Hot Electron Analyzer and IDD3P Measurements for HKMG Sub-nm DRAM." In ISTFA 2024, 5–8. ASM International, 2024. http://dx.doi.org/10.31399/asm.cp.istfa2024p0005.

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Abstract In this paper, we propose an advanced failure analysis method for specifying the location of gate-related fails in the High-k Metal Gate (HKMG) MOSFET. The test sample for this experiment is the sub-15nm technology DRAM (Dynamic Random Access Memory) which consists of high speed HKMG transistors. In terms of HKMG transistors, the modification of gate materials and process schemes provoke the various gate related failures in DRAM which makes it more difficult to examine the sample with conventional analyzing methods. So, IDD3P measurement methods along with dynamic Hot Electron Analyzer (HEA) were employed as an advanced fault localization method. IDD3P measurement data provides word-line (WL) dependent failure types which distinguishes the gate-related failures from other irrelevant failures. From the dynamic HEA with the MAGNUM tester, the accurate failure sites can be obtained. Newly combined two analytical methods that we present in this paper are effective in localizing the failure sites more accurate than previously suggested methods.
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Mysinski, Wojciech. "SiC mosfet transistors in power analog application." In 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe). IEEE, 2017. http://dx.doi.org/10.23919/epe17ecceeurope.2017.8099305.

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Takagi, S., D. H. Ahn, T. Gotow, K. Nishi, T. E. Bae, T. Katoh, R. Matsumura, R. Takaguchi, K. Kato, and M. Takenaka. "III-V/Ge-based tunneling MOSFET." In 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S). IEEE, 2017. http://dx.doi.org/10.1109/e3s.2017.8246157.

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Kovac, Dobroslav, and Andrii Gladyr. "Half Bridge Driver for MOSFET and IGBT Transistors." In 2019 IEEE International Conference on Modern Electrical and Energy Systems (MEES). IEEE, 2019. http://dx.doi.org/10.1109/mees.2019.8896665.

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Mulder, Randal. "Time Domain Nanoprobe Analysis of RTS Popcorn Noise in Analog Circuits." In ISTFA 2018. ASM International, 2018. http://dx.doi.org/10.31399/asm.cp.istfa2018p0403.

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Abstract Random Telegraph Signal (RTS), also described as popcorn noise in semiconductor analog circuits occurs when there is a sudden step in threshold voltage for a MOSFET or sudden step in base current for a bipolar transistor. The causes of popcorn noise can be process-related in semiconductor manufacturing. This paper presents a nanoprobe analysis methodology that was able to detect popcorn noise issues in discrete transistors causing analog circuit failure. The results presented for two different devices obtained similar results proving that the analysis methodology is viable for detecting popcorn noise issues in semiconductor MOSFET transistors. From a failure analysis perspective, the purpose of this paper is to provide the ability and a methodology to detect a signal that differentiates a failing transistor (popcorn noise) from a non-failing transistor (no popcorn noise). In this regard, the ability to obtain these results was not only unexpected but also very successful.
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Chvála, Aleš, Juraj Marek, Alexander Šatka, and Jue Chen. "Design of Power Transistor Embedded in PCB Supported by 3D Simulations." In ASME 2023 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. American Society of Mechanical Engineers, 2023. http://dx.doi.org/10.1115/ipack2023-111389.

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Abstract This paper presents an analysis and design of a power MOSFET transistor embedded in a printed circuit board (PCB). The analysis and design are supported by 3D electro-thermo-mechanical simulations. The analysis is focused on a comparison of the properties of a discrete power MOSFET transistor mounted on the surface of a PCB and a power MOSFET transistor embedded in a PCB. The conventional technology of packaged transistors exhibits significantly higher values of parasitic inductance, resistance, and thermal impedance compared to the embedded technology. 3D numerical finite element method simulations are effectively used for the design and optimization of the embedded technology in order to improve the electrical, thermal, and mechanical reliability performance of the device.
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Spasova, Mariya, Tihomir Brusev, George Angelov, Rossen Radonov, and Marin Hristov. "Low Power Ramp Generator with MOSFET and CNTFET Transistors." In 2019 IEEE XXVIII International Scientific Conference Electronics (ET). IEEE, 2019. http://dx.doi.org/10.1109/et.2019.8878567.

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Krutchinsky, S. G., E. I. Starchnko, and A. I. Gavlicky. "Analogous voltage multiplier based on bipolar transistors and MOSFET." In 2008 4th European Conference on Circuits and Systems for Communications (ECCSC. IEEE, 2008. http://dx.doi.org/10.1109/eccsc.2008.4611663.

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Rjoub, Abdoul, Nedal Al Taradeh, and Mamoun F. Al-Mistarihi. "Gate leakage current accurate models for nanoscale MOSFET transistors." In 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE, 2014. http://dx.doi.org/10.1109/patmos.2014.6951880.

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Simonot, T., H. X. Nguyen, N. Rouger, J. C. Crebier, A. Bourennane, L. Gerbaud, and J. L. Sanchez. "Towards reduced threshold voltages for vertical power Mosfet transistors." In 2011 IEEE 20th International Symposium on Industrial Electronics (ISIE). IEEE, 2011. http://dx.doi.org/10.1109/isie.2011.5984199.

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Reports on the topic "Transistors MOSFET"

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Ogunniyi, Aderinto, Heather O’Brien, and Miguel Hinojosa. Sub-Millisecond Pulse Power Evaluation of High-Voltage Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and High-Voltage SiC Insulated Gate Bipolar Translator. Aberdeen Proving Ground, MD: DEVCOM Army Research Laboratory, September 2022. http://dx.doi.org/10.21236/ad1181629.

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Yagci, Mustafa. Global Chip Shortage and Implications for Developing Countries. Islamic Development Bank Institute, March 2022. http://dx.doi.org/10.55780/re24021.

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Semiconductors, commonly known as chips, are crucial parts of our daily lives. In every electronic device we use, from smartphones to computers and automobiles to coffee machines, chips constitute one of the most critical components. Chips are packed with thousands or billions of transistors on a piece of small, coin-sized silicon or germanium. They function as the brains of electronic devices by storing, moving, and processing data. With the onset of the Covid-19 pandemic, the surge in demand for electronic devices and the shock in the global supply of chips have resulted in a global chip shortage. Many industries, such as automotive, computer and smartphone, were negatively affected by the global chip shortage and had to cut down their production capacity. This recent development, along with the great rivalry on technological development between the United States and China, necessitates developing countries to have a long-term strategy to access chips for their domestic industries.
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