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Journal articles on the topic 'Transistors MOSFET'
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1
Hebali, Mourad, Menaouer Bennaoum, Mohammed Berka, Abdelkader Baghdad Bey, Mohammed Benzohra, Djilali Chalabi, and Abdelkader Saidane. "A high electrical performance of DG-MOSFET transistors in 4H-SiC and 6H-SiC 130 nm technology by BSIM3v3 model." Journal of Electrical Engineering 70, no. 2 (April 1, 2019): 145–51. http://dx.doi.org/10.2478/jee-2019-0021.
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Abstract In this paper, the electrical performance of double gate DG-MOSFET transistors in 4H-SiC and 6H-SiC technologies have been studied by BSIM3v3 model. In which the I–V and gm–V characteristics and subthreshold operation of the DGMOSFET have been investigated for two models (series and parallel) based on equivalent electronic circuits and the results so obtained are compared with the single gate SG-MOSFET, using 130 nm technology and OrCAD PSpice software. The electrical characterization of DG-MOSFETs transistors have shown that they operate under a low voltage less than 1.2 V and low power for both models like the SG-MOSFET transistor, especially the series DG-MOSFET transistor is characterized by an ultra low power. The different transistors are characterized by an ultra low OFF leakage current of pA order, very high ON/OFF ratio of and high subthreshold slope of order 0.1 V/dec for the transistors in 6H-SiC and 4H-SiC respectively. These transistors also proved higher transconductance efficiency, especially the parallel DG-MOSFET transistor.
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He, Xibin. "The Advantages and Applications of IGBT Compared with Conventional BJT and MOSFET." Journal of Physics: Conference Series 2386, no. 1 (December 1, 2022): 012054. http://dx.doi.org/10.1088/1742-6596/2386/1/012054.
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Abstract Nowadays, the power semiconductor devices have been used in many fields like wind power generation systems, the rail transit. Bipolar junction transistors (BJTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) as well as some other devices are the dominating the market. The insulated gate bipolar transistor (IGBT) as a mixed device of the BJT and the MOSFET, has a preeminent performance. In this paper, the characteristics of the punch through IGBT (PT-IGBT), the MOSFET and the BJT will be investigated by TCAD. Then the PT-IGBT is compared with the BJT and the MOSFET, for concluding its advantages. According to the simulation result, the PT-IGBT has the on-state current of 9*10-4A and the forward blocking voltage of 1200V, which are much higher than the other two devices. In the end of the paper, the development of the semiconductor devices is predicted, about the research trends.
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Chek Yee, Ooi, Mok Kai Ming, and Wong Pei Voon. "DEVICE AND CIRCUIT LEVEL SIMULATION STUDY OF NOR GATE LOGIC FAMILIES DESIGNED USING NANO-MOSFETs." Platform : A Journal of Science and Technology 4, no. 1 (May 31, 2021): 73. http://dx.doi.org/10.61762/pjstvol4iss1art11064.
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The investigation of silicon-based nano-MOSFETs logic circuits is helpful to gain more comprehensive knowledge about nanoscale transistors. Therefore, a simulation study has been performed on four logic families of two inputs NOR gate logic circuits, namely (i) nano-CMOS NOR gate, (ii) nano-MOSFET loaded n-type nano-MOSFET NOR gate, (iii) 733.8 Ω resistive loaded nano-MOSFET NOR gate, and finally (iv) pseudo-n-type nano-MOSFET NOR gate. The nano-MOSFET technology node studied in this paper is 10 nm. Device simulation is done using an online NanoMOS simulator, whereas circuit simulation is carried out using freeware WinSpice. The main obstacle encountered during downscaling of nano-MOSFETs is low power dissipation and high-speed nano-MOSFET logic circuits. Correct logical NOR operation has been proven by observing simulated timing waveforms. Transient timing analysis on nano-MOSFET loaded n-type nano-MOSFET NOR gate has shown that propagation delays calculated from theory and simulation are 66% matched. From the analysis, this 10 nm nano-MOSFET NOR logic circuit design exhibit a dynamic power reduction of 148 times and a propagation delay improvement of 33 times when benchmarked against a typical 120 nm MOSFET logic circuit.
Keywords: nano transistor, electrical characteristics, channel length, channel width, benchmarking, power, speed
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Guran, Ionuț-Constantin, Adriana Florescu, and Lucian Andrei Perișoară. "A Novel ON-State Resistance Modeling Technique for MOSFET Power Switches." Mathematics 11, no. 1 (December 25, 2022): 72. http://dx.doi.org/10.3390/math11010072.
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Nowadays, electronic circuits’ time to market is essential, with engineers trying to reduce it as much as possible. Due to this, simulation has become the main testing concept used in the electronics domain. In order to perform the simulation of a circuit, a behavioral model must be created. Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are semiconductor devices found in a multitude of electronic circuits, and they are also used as power switches in many applications, such as low-dropout linear voltage regulators, switching regulators, gate drivers, battery management systems, etc. A MOSFETs’ behavior is extremely complex to model, thus, creating high-performance models for these transistors is an imperative condition in order to emulate the exact real behavior of a circuit using them. An essential parameter of MOSFET power switches is the ON-state resistance (RDSON), because it determines the power losses during the ON state. Ideally, the power losses need to be zero. RDSON depends on multiple factors, such as temperature, load current, and gate-to-source voltage. Previous studies in this domain focus on the modeling of the MOSFET only in specific operating points, but do not cover the entire variation range of the parameters, which is critical for some applications. For this reason, in this paper, there was introduced for the first time a novel ON-state resistance modeling technique for MOSFET Power Switches, which solves the entire RDSON dependency on the transistor’s variables stated above. The novel RDSON modeling technique is based on modulating the transistor’s gate-to-source voltage such that the exact RDSON value is obtained in each possible operating point. The method was tested as a real-life example by creating a behavioral model for an N-channel MOSFET transistor and the chosen simulation environment was Oregon, USA, Computer-Aided Design (OrCAD) capture. The results show that the model is able to match the transistor’s RDSON characteristics with a maximum error of 0.8%. This is extremely important for applications in which the temperatures, voltages, and currents vary over a wide range. The new proposed modeling method covers a gap in the behavioral modeling domain, due to the fact that, until now, it was not possible to model the RDSON characteristics in all operating corners.
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Gowthaman, Naveenbalaji, and Viranjay Srivastava. "Analysis of <i>InN/La<sub>2</sub>O<sub>3</sub></i> Twosome for Double-Gate MOSFETs for Radio Frequency Applications." Materials Science Forum 1048 (January 4, 2022): 147–57. http://dx.doi.org/10.4028/www.scientific.net/msf.1048.147.
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The channel material of a gate describes the operating condition of the MOSFET. A suitable operating condition prevails in MOSFETs if the transistors are quite enough to observe and control at the nanometer regime. An efficient gate and channel material have been proposed in this work which is based on the electrical properties they exhibit at the temperature of 300K. The doping concentration for the electrons and holes is maintained to be 1Χ1019cm-3 for the entire electronic simulator. The simulation results show that using La2O3 along with Indium Nitride (InN) material for the designing of Double-Gate (DG) MOSFETs provides better controllability over the transistor at a channel length of 50nm. This proposed DG-MOSFET is more compliant than the conventional coplanar MOSFETs based on Silicon.
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Cha, Kyuhyun, and Kwangsoo Kim. "Asymmetric Split-Gate 4H-SiC MOSFET with Embedded Schottky Barrier Diode for High-Frequency Applications." Energies 14, no. 21 (November 4, 2021): 7305. http://dx.doi.org/10.3390/en14217305.
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4H-SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) with embedded Schottky barrier diodes are widely known to improve switching energy loss by reducing reverse recovery characteristics. However, it weakens the static characteristics such as specific on-resistance and breakdown voltage. To solve this problem, in this paper, an Asymmetric 4H-SiC Split Gate MOSFET with embedded Schottky barrier diode (ASG-MOSFET) is proposed and analyzed by conducting a numerical TCAD simulation. Due to the asymmetric structure of ASG-MOSFET, it has a relatively narrow junction field-effect transistor width. Therefore, despite using the split gate structure, it effectively protects the gate oxide by dispersing the high drain voltage. The Schottky barrier diode (SBD) is also embedded next to the gate and above the Junction Field Effect transistor (JFET) region. Accordingly, since the SBD and the MOSFET share a current path, the embedded SBD does not increase in RON,SP of MOSFET. Therefore, ASG-MOSFET improves both static and switching characteristics at the same time. As a result, compared to the conventional 4H-SiC MOSFET with embedded SBD, Baliga′s Figure of Merit is improved by 17%, and the total energy loss is reduced by 30.5%, respectively.
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Kunov, Georgi, Tihomir Brusev, and Elissaveta Gadjeva. "Power losses in the MOSFET transistors of switching-mode converters." IOP Conference Series: Materials Science and Engineering 1298, no. 1 (December 1, 2023): 012019. http://dx.doi.org/10.1088/1757-899x/1298/1/012019.
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Abstract The power losses in the MOSFET transistors of switching-mode converters are investigated and analyzed. The results presented in this paper are achieved using software Cadence OrCAD. The simulation model suitable for estimation of energy dissipations in MOSFET transistors is proposed. The power losses as a function of different circuit’s parameters, like switching frequency, power supply voltage and output current are evaluated. The PSpice model of MOSFET transistor “BSC020N03MS” of the company Infineon is used in the presented analysis. Control circuit, which realize the adaptive deadtime (ADT) control technique depending on the load current, is applied to reduce the switching power losses in the MOSFET transistor. Thus, the efficiency of the switching-mode converters can be increased.
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Bogatyrev, Yu V., D. A. Aharodnikau, S. B. Lastovsky, A. V. Ket’ko, M. M. Krechko, S. V. Shpakovsky, P. V. Rubanov, G. A. Protopopov, and P. A. Chubunov. "Influence of ionizing radiation on the parameters of p-channel MOS transistors." Proceedings of the National Academy of Sciences of Belarus, Physical-Technical Series 67, no. 4 (January 2, 2023): 402–8. http://dx.doi.org/10.29235/1561-8358-2022-67-4-402-408.
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The results of experimental studies of the influence of gamma radiation Co60 on the basic parameters of silicon epitaxial-planar p-channel MOSFET transistors under different electrical modes are presented. Transistors were manufactured according to radiation-resistant DMOS technology with design standards of 1.4 μm. As a result of transistor studies, it was established that the values of all basic parameters after the radiation dose D = 106 rads (SiO2) in active electrical irradiation modes remained within the limits of the performance criteria; the parameter, most sensitive to influence of a dose of irradiation by gamma-quanta is the threshold voltage; in the passive electrical irradiation mode the transistor’s radiations resistance in all parameters corresponds to a dose of 2,8·106 rads (SiO2). A sufficiently high radiation resistance of the studied p-channel MOSFETs makes it possible to recommend them for use in aviation and space equipment. The different degrees of radiation degradation of the studied parameters during irradiation are due to their dependence either on the effects of ionization in the layers of sub-gate and insulating dielectrics, or structural damage in the bulk silicon of the transistor active regions. The high radiation resistance of the studied p-channel MOSFETs allows recommending them for use in aviation and space equipment.
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Taberkit, Amine Mohammed, Ahlam Guen-Bouazza, and Benyounes Bouazza. "Modeling and Simulation of Biaxial Strained P-MOSFETs: Application to a Single and Dual Channel Heterostructure." International Journal of Electrical and Computer Engineering (IJECE) 8, no. 1 (February 1, 2018): 421. http://dx.doi.org/10.11591/ijece.v8i1.pp421-428.
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The objectives of this work are focused on the application of strained silicon on MOSFET transistor. To do this, impact and benefits obtained with the use of strained silicon technology on p-channel MOSFETs are presented. This research attempt to create conventional and two-strained silicon MOSFETs fabricated from the use of TCAD, which is a simulation tool from Silvaco. In our research, two-dimensional simulation of conventional MOSFET, biaxial strained PMOSFET and dual channel strained P-MOSFET has been achieved to extract their characteristics. ATHENA and ATLAS have been used to simulate the process and validate the electronic characteristics. Our results allow showing improvements obtained by comparing the three structures and their characteristics. The maximum of carrier mobility improvement is achieved with percentage of 35.29 % and 70.59 % respectively, by result an improvement in drive current with percentage of 36.54 % and 236.71 %, and reduction of leakage current with percentage of 59.45 % and 82.75 %, the threshold voltage is also enhaced with percentage of: 60 % and 61.4%. Our simulation results highlight the importance of incorporating strain technology in MOSFET transistors.
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Cho, Geunho. "A Study on the Design Method of Hybrid MOSFET-CNTFET Based SRAM – A Secondary Publication." Journal of Electronic Research and Application 8, no. 1 (February 20, 2024): 106–12. http://dx.doi.org/10.26689/jera.v8i1.6115.
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More than 10,000 carbon nanotube field-effect transistors (CNTFETs) have been successfully integratedinto one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Thesetransistors offer advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, andtransparency. The three-dimensional multilayer structure of the CNTFET semiconductor chip, along with ongoing researchin CNTFET manufacturing processes, increases the potential for creating a hybrid MOSFET-CNTFET semiconductorchip. This chip combines conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and CNTFETs inone integrated system. This paper discusses a methodology to design 6T binary static random-access memory (SRAM)using a hybrid MOSFET-CNTFET. This paper introduces a method for designing a hybrid MOSFET-CNTFET SRAMby leveraging existing MOSFET SRAM or CNTFET SRAM design approaches. Additionally, this paper compares itsperformance with conventional MOSFET SRAM and CNTFET SRAM designs.
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Noll, Stefan, Dick Scholten, Michael Grieb, Anton J. Bauer, and Lothar Frey. "Electrical Impact of the Aluminum P-Implant Annealing on Lateral MOSFET Transistors on 4H-SiC N-Epi." Materials Science Forum 740-742 (January 2013): 521–24. http://dx.doi.org/10.4028/www.scientific.net/msf.740-742.521.
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In this work we investigate the effect of the aluminum p-well implant annealing process on the electrical properties of lateral 4H-SiC MOSFET transistors. The interface trap concentration was measured by quasi-static capacitive voltage (QSCV) and negative bias stress measurements on MOSFETs. We found that higher annealing temperatures significantly reduce the trap density in the lower bandgap, and as a consequence the threshold voltage drift of the transistor after negative stress is reduced.
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Li, Hui, Renze Yu, Yi Zhong, Ran Yao, Xinglin Liao, and Xianping Chen. "Design of 400 V Miniature DC Solid State Circuit Breaker with SiC MOSFET." Micromachines 10, no. 5 (May 10, 2019): 314. http://dx.doi.org/10.3390/mi10050314.
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Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have the advantages of high-frequency switching capability and the capability to withstand high temperatures, which are suitable for switching devices in a direct current (DC) solid state circuit breaker (SSCB). To guarantee fast and reliable action of a 400 V DC SSCB with SiC MOSFET, circuit design and prototype development were carried out. Taking 400V DC microgrid as research background, firstly, the topology of DC SSCB with SiC MOSFET was introduced. Then, the drive circuit of SiC MOSFET, fault detection circuit, energy absorption circuit, and snubber circuit of the SSCB were designed and analyzed. Lastly, a prototype of the DC SSCB with SiC MOSFET was developed, tested, and compared with the SSCB with Silicon (Si) insulated gate bipolar transistor (IGBT). Experimental results show that the designed circuits of SSCB with SiC MOSFET are valid. Also, the developed miniature DC SSCB with the SiC MOSFET exhibits faster reaction to the fault and can reduce short circuit time and fault current in contrast with the SSCB with Si IGBT. Hence, the proposed SSCB can better meet the requirements of DC microgrid protection.
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Ahn, Tae Jun, and Yun Seop Yu. "Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter." Journal of Nanoscience and Nanotechnology 21, no. 8 (August 1, 2021): 4252–57. http://dx.doi.org/10.1166/jnn.2021.19388.
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We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.
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Melnyk, Kyrylo, Lu Yang Zhang, Peter Michael Gammon, Arne Benjamin Renz, and Marina Antoniou. "Analysis of On-State and Short-Circuit Capability in 3D Trench SiC MOSFET Designs." Solid State Phenomena 358 (August 21, 2024): 97–102. http://dx.doi.org/10.4028/p-zb9gva.
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Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are successfully replacing traditional silicon insulated gate bipolar transistors (Si IGBTs) in power applications. Nonetheless, two crucial challenges persist: gate-oxide reliability and a reduced short circuit (SC) withstand time. This paper explores a novel MOSFET structure, which is designed to address these concerns and compares it with existing designs through extensive 3D TCAD simulations. The proposed MOSFET structure features a p-region under the gate, providing a unique configuration for improved performance during SC events. This novel structure is then compared to two commercially realized MOSFET structures. Our structure has a superior on-state performance with a specific resistance of 1.48 mΩ /cm2, showing an improvement by 25 % and 15 %, respectively. It also increases the blocking capability by 100 V and SC withstand time in comparison to the double-trench MOSFET.
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Wang, Qingyu. "Application of the quantum effects of single-electron transistors in low-power." Applied and Computational Engineering 130, no. 1 (January 13, 2025): 102–7. https://doi.org/10.54254/2755-2721/2025.20293.
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As the feature size of transistors approaches the 2nm limit, quantum effects become more pronounced as a result of devices that cannot work properly. Conventional MOSFET architectures are difficult to solve the problems. Therefore, new transistor architectures need to be developed. As a new transistor architecture, the single-electron transistor (SET) working based on quantum effects and has a very low power consumption. This paper analyzed working principle of single-electron transistor (SET) and compared the advantages of its extremely low power consumption in quantum computing with MOSFET. Although single-electron transistors (SET) have many advantages, there still are some challenges. Such as manufacturing technology, stability and reliability issues. As technology advances, single-electron transistor (SET) is expected to play an important role in the future of electronics.
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Hasan, Ghanim Thiab, Ali Hlal Mutlaq, and Kamil Jadu Ali. "Comparative evaluation of SiC/GaN “MOSFET” transistors under different switching conditions." Bulletin of Electrical Engineering and Informatics 11, no. 2 (April 1, 2022): 681–90. http://dx.doi.org/10.11591/eei.v11i2.3445.
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The aim of this paper is to conduct a mutual comparison of switching energy losses in cascade gallium nitride (GaN) and silicon "super junction" MOSFET” transistor, in both cases designed for a maximum operating voltage of (650 V). For the analysis of switching characteristics of transistors used double pulse test method by using detailed SPICE simulation model. Data on transient on and off processes were generated using the “LTspice” simulation package in a wide range of drain currents with two different gate resistance values of the tested transistors. The total energy losses in the GaN have been simulated during one transistor at (on and off cycle). The obtained results indicate that the superior switching characteristics of GaN devices for a drain current of (30 A) is five to eight times less than the switching characteristics of silicon “MOSFET” transistor when compared to silicon components, especially during operation of transistors with high drain currents.
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Chaudhry, Amit, and Nath Roy. "A comparative study of hole and electron inversion layer quantization in MOS structures." Serbian Journal of Electrical Engineering 7, no. 2 (2010): 185–93. http://dx.doi.org/10.2298/sjee1002185c.
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In this paper, an analytical model has been developed to study inversion layer quantization in nanoscale Metal Oxide Semiconductor Field Effect Oxide p-(MOSFET). n-MOSFETs have been studied using the variation approach and the p-MOSFETs have been studied using the triangular well approach. The inversion charge density and gate capacitance analysis for both types of transistors has been done. There is a marked decrease in the inversion charge density and the capacitance of the p-MOSFET as compared to n-MOSFETs. The results are compared with the numerical results showing good agreement.
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Rajesh Rao J R, Nachiappan D, Dr. Nitinkumar D Banker, and Dr. Ashok S. "Simulation Workflow Evaluation and Validation of Power Converter’s Electro Thermal Performance and Framework For Physics Based Prediction Model." International Research Journal on Advanced Engineering and Management (IRJAEM) 2, no. 08 (August 19, 2024): 2710–19. http://dx.doi.org/10.47392/irjaem.2024.0392.
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A power MOSFET is a specific type of metal–oxide–semiconductor field-effect transistor (MOSFET) designed to handle significant power levels. Compared to the other power semiconductor devices, such as an insulated-gate bipolar transistor (IGBT) or a thyristor, its main advantages are high switching speed and good efficiency at low voltages. It shares with the IGBT an isolated gate that makes it easy to drive. Power converters are pivotal components in modern electronic systems, facilitating the transformation of electrical energy from one form to another. Among the crucial elements within these converters, Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) play a central role due to their efficiency and versatility. Understanding and optimizing the electro-thermal performance of MOSFETs in power converters is paramount for enhancing efficiency, reliability, and overall system performance. It delves into the fundamental principles governing MOSFET operation, emphasizing their pivotal role in power conversion circuits. Furthermore, it elucidates the intricate interplay between electrical and thermal characteristics in MOSFETs, highlighting the challenges and opportunities in achieving optimal performance. It discusses advanced techniques for thermal management and heat dissipation, crucial for mitigating thermal stresses and ensuring device longevity. Additionally, the study explores innovative approaches for enhancing MOSFET reliability and efficiency through optimized thermal design and material selection. Overall, this abstract provides valuable insights into the electro-thermal performance of MOSFETs in power converters and well-defined workflow process to identify the passage of heat flow from IC till heat sink. MOSFETs exhibit lower on-state resistance (RDS (on)) at lower temperatures. Effective thermal design ensures that MOSFETs operate at optimal temperatures, minimizing conduction losses and maximizing power conversion efficiency. Based on the available test data and simulation model, Training the AI model with algorithm based on detecting the Maximum temperature of each critical components. Providing the prediction and indication for each band by displaying the maximum temperature of the components. This physics-based prediction model helps not reduce overall time invested for power converters development
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Vikulin, I. М., L. F. Vikulina, V. М. Litvinenko, V. E. Gorbachev, and P. Y. Markolenko. "DETECTORS BASED ON FIELD EFFECT TRANSISTORS." Photoelectronics, no. 30 (December 24, 2021): 46–57. http://dx.doi.org/10.18524/0235-2435.2021.30.262855.
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The possibility of using the method of combining several sensor elements with opposite sensitivity to various external influences to obtain new designs of sensors for light, temperature and magnetic field has been experimentally investigated. Standard industrial samples of FEJT and a MOSFET in saturation mode with two-pole connection, when the gate is closed with the source, were used as sensor elements in the work. It is shown that the FEJT has a negative temperature coefficient of current change, while the MOSFET has a positive one. At the same time, the sign of the radiative action factor of the MOSFET is determined by the initial value of the drain current before irradiation. It has been experimentally confirmed that the use of four transistors in a bridge measurement circuit increases the sensitivity of the sensor tenfold compared to one transistor due to the internal mechanism of increasing the sensitivity for series-connected pairs of transistors.
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Choi, Yang-Kyu, and Myung-Su Kim. "Revolutionising electronic power consumption." Impact 2022, no. 1 (February 4, 2022): 31–33. http://dx.doi.org/10.21820/23987073.2022.1.31.
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Transistors play a key role in everyday life and there is a growing need to reduce their power consumption. Although there have been efforts to create more sustainable transistors, a consistent design has yet to be developed. Myung-Su Kim and his supervisor Professor Yang-Kyu Choi who are with the School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Republic of Korea, are working to develop such a transistor. The most common transistor is the metal-oxide-semiconductor field-effect transistor (MOSFET), which has been adapted and improved upon over the 60 years. Kim and Choi have been redesigning the archetypal MOSFET by adding different structures as well as additional layers over the electrode for the gate. In doing this, the researchers have developed a device that can reduce the voltage change required to change the state of the transistor. This means that their altered MOSFET, called a gamma-FET (Γ-FET), can consume less power than the standard MOSFET. Using a variety of electronic and physical experiments involving the focused ion beam (FIB) technique, split experiments and comparative studies, the researchers are verifying the physical structure and electrical performance of the device. Ultimately, Kim and Choi have developed a transistor that can consume less power whilst in standby, which has significant potential to increase battery life across a variety of different devices. This could be beneficial both for usability and in terms of environmentally friendliness.
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Natarajamoorthy, Mathan, Jayashri Subbiah, Nurul Ezaila Alias, and Michael Loong Peng Tan. "Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design." Journal of Nanotechnology 2020 (April 30, 2020): 1–7. http://dx.doi.org/10.1155/2020/7608279.
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The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.
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Ahn, Tae Jun, and Yun Seop Yu. "Electrical Coupling of Monolithic 3D Inverters (M3INVs): MOSFET and Junctionless FET." Applied Sciences 11, no. 1 (December 30, 2020): 277. http://dx.doi.org/10.3390/app11010277.
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In this paper, we investigated the electrical coupling between the top and bottom transistors in a monolithic 3-dimensional (3D) inverter (M3INV) stacked vertically with junctionless field-effect transistor (JLFET), which is one of candidates to replace metal-oxide-semiconductor field-effect transistors (MOSFET). Currents, transconductances, and gate capacitances of the top N-type transistor at the different gate voltages of the bottom P-type transistor as a function of thickness of inter-layer dielectric (TILD) and gate channel length (Lg) are simulated using technology computer-aided-design (TCAD). In M3INV stacked vertically with MOSFET (M3INV-MOS) and JLFET (M3INV-JL), the variations of threshold voltage, transconductance, and capacitance increase as TILD decreases and they increase as Lg increases, and thus there is a strong coupling in M3INV at the range of TILD ≤ 30 nm. In M3INV, the coupling between stacked JLFETs in M3INV-JL is larger than that between MOSFETs in M3INV-MOS at the same TILD and Lg. The switching threshold voltage (Vm) and noise margins (NMs) of M3INV are calculated from the voltage transfer characteristics (VTC) simulated with TCAD mixed-mode. As the gate lengths of M3INV-MOS and M3INV-JL increase, the Vm variations increase and decrease, respectively. The smaller the gate lengths of M3INV-NOS and M3INV-JL, the larger and smaller the variation of Vm, respectively. The noise margin of M3INV-MOS is larger and better for inverter characteristics than one of M3INV-JL. M3INV-MOS has less electrical coupling than M3INV-JL.
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Umegami, Hirokatsu, Toshikazu Harada, and Ken Nakahara. "Performance Comparison of Si IGBT and SiC MOSFET Power Module Driving IPMSM or IM under WLTC." World Electric Vehicle Journal 14, no. 4 (April 17, 2023): 112. http://dx.doi.org/10.3390/wevj14040112.
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The cumulative inverter losses and power consumption of a silicon insulated gate bipolar transistor (Si IGBT) and three types of silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) were evaluated on an electric motor test bench under a worldwide harmonized light vehicles test cycle (WLTC). SiC MOSFETs showed higher performance than Si IGBT regardless of the motor type and test vehicles. In the case of driving an interior permanent magnet synchronous motor (IPMSM), the latest 4th generation SiC MOSFET (SiC-4G) in ROHM has the lowest inverter loss and energy consumption compared with the other generations. In the case of driving an induction motor (IM), on the other hand, the 2nd generation SiC MOSFET (SiC-2G) in ROHM has the best energy consumption despite the fact that the inverter losses of SiC-2G are slightly larger than the loss of SiC-4G. The latest or later generation power device does not necessarily contribute to better performance in a total system by simply replacing early power devices.
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Murakami, Eiichi, Tatsuya Takeshita, and Kazuhiro Oda. "Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs." Materials Science Forum 1062 (May 31, 2022): 642–46. http://dx.doi.org/10.4028/p-xz45c3.
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Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been produced by several vendors for commercial applications. SiC-MOSFET reliability was assessed using bias-temperature instability (BTI) and time-dependent dielectric breakdown (TDDB) characteristics. Here, we compared two planar SiC-MOSFET samples (A and B) from different vendors. The samples exhibited significantly different positive and negative BTI, time-dependent gate-current, TDDB lifetime statistics, and temperature dependence. These differences suggest NO (nitric oxide)-annealing variations.
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BLALOCK, BENJAMIN J., SORIN CRISTOLOVEANU, BRIAN M. DUFRENE, F. ALLIBERT, and MOHAMMAD M. MOJARRADI. "THE MULTIPLE-GATE MOS-JFET TRANSISTOR." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 511–20. http://dx.doi.org/10.1142/s0129156402001423.
Full textAbstract:
A new SOI device, the MOS-JFET, has been developed that combines two different transistors, JFET and MOSFET, superimposed in a single silicon island so that they share the same body. A unique attribute of the MOS-JFET is that it can be viewed as a four gate transistor (two side junction-based gates, the top MOS gate, and the back gate activated by SOI substrate biasing). Each of these four gates can control the conduction characteristics of the transistor. This novel transistor's multiple gate inputs give rise to exciting circuit opportunities for analog, RF, mixed-signal, and digital applications. Measured results of MOS-JFET transistors, fabricated in a conventional partially-depleted SOI technology, demonstrate that the device is fully operational. From the experiments and systematic 2-D simulations, typical regions of operation are identified. These results indicate that optimum performance is reached when the MOS and junction field-effects are combined.
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Darmis, Naimah, AHM Zahirul Alam, and Muhaimin Mohd Hashim. "Ferroelectric behavior and NCFETs - TCAD Simulation." Asian Journal of Electrical and Electronic Engineering 1, no. 1 (March 31, 2021): 30–41. http://dx.doi.org/10.69955/ajoeee.2021.v1i1.14.
Full textAbstract:
With the miniaturization of transistors, the current leakage also increases due to the increasing tunnelling effect. Plus, Boltzmann’s tyranny limits the subthreshold swing to be best and ideal at 60 mV/decade. Due to these, the power consumption in transistors keeps soaring up. Therefore, in this paper, the Negative Capacitance Effect Field Transistor (NCFET) is discussed as it possesses excellent potentials in reducing the power consumption in transistors. The negative capacitance induced in NCFET enables the internal voltage amplification and reduces the required voltage for the transistor to operate, and therefore, the power consumption is reduced. The literature reviews are done to gain knowledge on the structure and behavior of the NCFET. Next, the process and device simulation of NMOS are studied using Silvaco TCAD to get the idea of developing a circuit simulator model of NCFET. After that, we developed the circuit model of NCFET and MOSFET. Next, the ferroelectric parameters are varied to study how it will affect the ferroelectric material's polarization and capacitance. The ferroelectric thickness and source-drain doping concentration of the proposed NCFET model is also varied to study the NCFET behaviors in peak current, subthreshold slope, saturation current and saturation slope. Lastly, the performances of NCFET and MOSFET are compared. It is found that the NCFET has better performance as compared to the MOSFET as the NCFET can achieve a steeper subthreshold slope.
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Khvitia, Badri, Anna Gheonjian, Zviadi Kutchadze, and Roman Jobava. "A SPICE Model for IGBTs and Power MOSFETs Focusing on EMI/EMC in High-Voltage Systems." Electronics 10, no. 22 (November 17, 2021): 2822. http://dx.doi.org/10.3390/electronics10222822.
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We describe two models of Power Transistors (IGBT, MOSFET); both were successfully used for the analysis of electromagnetic interference (EMI) and electromagnetic compatibility (EMC) while modeling high-voltage systems (PFC, DC/DC, inverter, etc.). The first semi-mathematical–behavioral insulated-gate bipolar transistor (IGBT) model introduces nonlinear negative feedback generated in the semiconductor’s p+ and n+ layers, which are located near the metal contact of the IGBT emitter, to better describe the dynamic characteristics of the transistor. A simplified model of the metal–oxide-semiconductor field-effect transistor (MOSFET) in the IGBT is used to simplify this IGBT model. The second simpler behavioral model could be used to model both IGBTs and MOSFETs. Model parameters are obtained from datasheets and then adjusted using results from a single measurement test. Modeling results are compared with measured turn-on and turn-off waveforms for different types of IGBTs. To check the validation of the models, a brushless DC electric motor test setup with an inverter was created. Despite the simplicity of the presented models, a comparison of model predictions with hardware measurements revealed that the model accurately forecasted switch transients and aided EMI–EMC investigations.
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Satyanarayana, B. V. V., and M. Durga Prakash. "Design and Analysis of Heterojunction Tunneling Transistor (HETT) based Standard 6T SRAM Cell." International Journal of Engineering & Technology 7, no. 3.29 (August 24, 2018): 8. http://dx.doi.org/10.14419/ijet.v7i3.29.18450.
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Subthreshold Swing (SS) of MOSFETs, which determines the low voltage operation of portable mobile devices, cannot reduce below 60mV/dec that restricts MOSFETs for ultra-low power applications. This work presents design and implementation of high ON current, improved Miller capacitance and reduced Subthreshold Swing heterojunction tunneling transistors (HETTs) for portable electronic systems. The performance of HETT with MOSFET has been compared. In this work, the overlapping of gate/oxide on to source can increase the band to band tunneling (BTBT) and improves the ON current of the transistor. Miller capacitance effect can be reduced by the use of low band offset materials and low energy states of materials like Ge or SiGe. This, in turn, results in better performance characteristics for the transistor.The Proposed design and implementation of HETT include both N-type HETT (NHETT) and P-type HETT (PHETT) fabrications and the performance characteristics analysis of both NHETT and PHETT are provided. The advantages and limitations of both NHETT and PHETT for beyond CMOS technologies, in addition to the basic and structural differences between HETTs and conventional MOSFETs to facilitate the use of HETT in place of MOSFET have been elaborated in detail. The construction process of HETT is not at all completely different which is suitable to MOS Design process and is applicable for portable mobile applications. The power analysis of HETT based standard 6T SRAM cell is provided and the performance is verified with the conventional MOSFET based 6T SRAM cell.
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Arul, P., and K. Helen Prabha. "A Comprehensive Analysis of Short Channel Effects on Carbon Nano Tube Field Effect Transistors." Journal of Nanoelectronics and Optoelectronics 16, no. 12 (December 1, 2021): 1905–12. http://dx.doi.org/10.1166/jno.2021.3144.
Full textAbstract:
As the direction of World health organization (WHO) report the diseases like male infertility, brain tumor, hearing impairment, fetus issues, effect on eyes and other various parts of the human body caused by harmful radiations released by portable electronic devices. To reduce radiation and size, a deep scaling has been applied on MOSFETs. Due to this aggressive scaling MOSFET devices are affected by Short Channel Effects (SCE) in Nanometer regime (<10 nm). The Short Channel Effects Such as Subthreshold Swing (SS), Drain Induced barrier Lowering (DIBL) and threshold voltage roll-off (VT), plays a key role in determining the performance of CMOS devices. At Nano-meter scale Carbon Nano Tube FETs (CNTFETs) devices might be furnished with good control on leakage current and power consumption. The comparative analysis of Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL) and Ion/Ioff ratio on Conventional Single Gate MOSFET (C-MOSFET), Double Gate MOSFET (DG-MOSFET) and CNTFET devices are presented in this paper. The results of comparative analysis show that CNTFET exhibits 133% times more Ion/Ioff ratio than MOSFET and very less change in Subthreshold swing and DIBL.
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Das, Sanat, Bibek Chettri, Prasanna Karki, Bhakta Kunwar, Pronita Chettri, and Bikash Sharma. "Impact of high-k metal oxide as gate dielectric on the certain electrical properties of silicon nanowire field-effect transistors: A simulation study." Facta universitatis - series: Electronics and Energetics 36, no. 4 (2023): 553–65. http://dx.doi.org/10.2298/fuee2304553d.
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Standard Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are gaining prominence in low-power nanoscale applications. This is largely attributed to their proximity to physical and thermal limits, rendering them a compelling option for energy-efficient electronic devices. In this study, we hypothesized that the high-? HfO2 in a quasi-ballistic SiNW MOSFET acts as the gate dielectric. In this case, the data from the TCAD simulation and the model demonstrated exceptional agreement. The proposed model for a SiNW MOSFET with high-? HfO2 exhibits a consistently increasing drain current, albeit with a smaller magnitude compared to a quasi-ballistic device (QBD). Additionally, it shows reduced mobility and decreased transconductance when considering the combined effects of scattering and temperature. As gate voltage increases, temperatureinduced transconductance decline in SiNW MOSFETs becomes significant. Our method is suitable for modeling scattered SiNW MOSFETs with temperature effects, as TGF values are similar in the subthreshold region for both Near Ballistic and Scattered SiNW MOSFET models.
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Nerubatskyi, Volodymyr Pavlovych, Olexandr Andrievych Plakhtii, Denys Anatoliiovych Hordiienko, Hryhorii Anatoliiovych Khoruzhevskyi, and Maryna Vitaliyivna Philipjeva. "RESEARCH THE ACCURACY OF MODELING POWER LOSSES IN POWER DIODES AND TRANSISTORS." Collection of Scientific Works of the Ukrainian State University of Railway Transport, no. 203 (March 27, 2023): 73–87. http://dx.doi.org/10.18664/1994-7852.203.2023.277905.
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The methodology for modeling static and dynamic power losses in power IGBT and MOSFET transistors in the Matlab and Multisim software environments is given. It is shown that when modeling switching processes in power transistors, Matlab / Simulink does not allow determining the dynamic components of power losses, namely, the energy of turning on the transistor, the energy of turning off the transistor, as well as the recovery energy of power diodes. At the same time, the simulation of static power losses of power diodes and transistors in Matlab/Simulink is carried out with a significant error due to incorrect representation of the current-voltage characteristics. It is shown that for a more correct and accurate simulation of the operation of power transistors, including power losses in power switches, it is more appropriate to conduct simulations in the Multisim software environment, which takes into account more than 47 parameters during simulation, including temperature characteristics, parasitic input and output capacitances and inductances, nonlinearities of current-voltage characteristics and others. In Multisim, a circuit of a half-bridge inverter with power MOSFETs controlled by the IR2104PBF driver has been developed. It is shown that the switching of power transistors is significantly influenced by the parameters of the driver microcircuit, namely the size of the storage capacitor of the driver, as well as the value of the active resistance of the gate resistor. It is shown that the simulation in Multisim correctly displays the transient processes of turning on and off power transistors and reverse recovery of diodes, which allows determining the dynamic losses of power transistors and power diodes.
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Radamson, Henry H., Xiaobin He, Qingzhu Zhang, Jinbiao Liu, Hushan Cui, Jinjuan Xiang, Zhenzhen Kong, et al. "Miniaturization of CMOS." Micromachines 10, no. 5 (April 30, 2019): 293. http://dx.doi.org/10.3390/mi10050293.
Full textAbstract:
When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.
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Duan, Haoyuan. "From MOSFET to FinFET to GAAFET: The evolution, challenges, and future prospects." Applied and Computational Engineering 50, no. 1 (March 25, 2024): 113–20. http://dx.doi.org/10.54254/2755-2721/50/20241285.
Full textAbstract:
With the swift progression of semiconductor technology, the transition from Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) to Fin Field-Effect Transistors (FinFETs) and further to Gate-All-Around Field-Effect Transistors (GAAFETs) presents significant potential for the future of electronic devices and systems. This article delves into the intricate applications, challenges, and prospective evolutions associated with FinFET and GAAFET technologies. Findings suggest that these technologies are particularly apt for low-power logic systems, high-performance computing, and artificial intelligence domains. However, as dimensions shrink, challenges pertaining to heat dissipation, leakage, and manufacturing consistency become prominent. Despite these hurdles, the horizon for semiconductor technology remains bright, encompassing exploration of alternative materials such as Germanium and 2D compositions and innovative designs like U-shaped Field-Effect Transistors and Complementary Field-Effect Transistors. As the industry continues its relentless pursuit of even more efficient, smaller transistors, the exploration of alternative materials and diversification in architecture may play a pivotal role in future developments. In essence, while the semiconductor sphere confronts challenges, relentless innovation promises a future brimming with even more efficient and compact transistor technologies.
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Na, Jaeyeop, Minju Kim, and Kwangsoo Kim. "High Performance 3.3 kV SiC MOSFET Structure with Built-In MOS-Channel Diode." Energies 15, no. 19 (September 22, 2022): 6960. http://dx.doi.org/10.3390/en15196960.
Full textAbstract:
Built-in freewheeling diode metal–oxide–semiconductor field-effect transistors (MOSFETs) that ensure high performance and reliability at high voltages are crucial for chip integration. In this study, a 4H–SiC built-in MOS-channel diode MOSFET with a center P+ implanted structure (CIMCD–MOSFET) is proposed and simulated via technology computer-aided design (TCAD). The CIMCD–MOSFET contains a P+ center implant region, which protects the gate oxide edge from high electric field crowding. Moreover, the region also makes it possible to increase the junction FET (JFET) and N-drift doping concentration of the device by dispersing the high electric field. Consequently, the CIMCD–MOSFET is stable even at a high voltage of 3.3 kV without static degradation and gate oxide reliability issues. The CIMCD–MOSFET also has higher short-circuit withstanding capability owing to the low saturation current and improved switching characteristics due to the low gate-drain capacitance, compared to the conventional MOSFET (C–DMOSFET) and the built-in Schottky barrier diode MOSFET (SBD–MOSFET). The total switching time of a CIMCD–MOSFET is reduced by 52.2% and 42.2%, and the total switching loss is reduced by 67.8% and 41.8%, respectively, compared to the C–DMOSFET and SBD–MOSFET.
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Hajare, Raju, and C. Lakshminarayana. "Design and software characterization of finFET based full adders." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 1 (February 11, 2019): 51. http://dx.doi.org/10.11591/ijres.v8.i1.pp51-60.
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Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.
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Jadli, Utkarsh, Faisal Mohd-Yasin, Hamid Amini Moghadam, Peyush Pande, Mayank Chaturvedi, and Sima Dimitrijev. "A Method for Selection of Power MOSFETs to Minimize Power Dissipation." Electronics 10, no. 17 (September 3, 2021): 2150. http://dx.doi.org/10.3390/electronics10172150.
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A balance between static and dynamic losses of a power MOSFET is always desirable for accomplishing the maximum efficiency for a specific power converter. The standard semiconductor theory suggests that a minimum power dissipation in a MOSFET can be achieved by selecting a specific device active area. However, for power circuit designers, the active device area is unknown given that only datasheet parameters are available. Hence, in this paper, we propose a simple method, based on semiconductor theory, to select optimum power MOSFET from a family of MOSFETs using only datasheet parameters. By applying this optimization method to the specific power supply circuit under development, power engineers can select the best transistors to yield lowest power losses for the systems under development.
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Zhou, Huimei. "An Overview of Hot Carrier Degradation on Gate-All-Around Nanosheet Transistors." Micromachines 16, no. 3 (March 6, 2025): 311. https://doi.org/10.3390/mi16030311.
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Gate-All-Around (GAA) Nanosheet (NS) transistors have been identified as the device architecture for 3 nm and beyond as they provide additional scaling benefits. The Hot Carrier (HC) effect cannot be ignored in the development of metal oxide semiconductor field effect transistors (MOSFETs). In this article, we present a comprehensive review of Hot Carrier Degradation (HCD) studies on GAA NS transistors including geometry dependencies, surface orientation impacts, corner effects, characterization methodologies, process impacts and self-heating impacts from different researchers, together with the challenges and outlook, providing an insightful and valuable HCD reliability discussion and review on the cutting-edge technology in continuous MOSFET scaling.
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Swailim Muhawwis, Abdulgaffar. "Performance of Sensitivity of Direct Detection Optical Receiver Incorporating MOSFET-Based Transimpedance-Type Amplifier." University of Thi-Qar Journal for Engineering Sciences 1, no. 2 (December 1, 2010): 116–28. http://dx.doi.org/10.31663/utjes.v1i2.131.
Full textAbstract:
Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) offer many advantages due to their low noise and high associated gain at microwave frequencies. Therefore, they are well suited to the amplifier requirements of broadband light-wave receivers, through providing a high dynamic range and wide bandwidths. In this work, the performance of integrated optical receiver consisting of PIN-photodiode and MOSFET-based transimpedence type amplifier is analyzed. The effect of various device parameters on receiver performance is investigated in details. The simulation results show that the sensitivity (Psen) of an optical receiver is approximately constant if it is based on well-designed MOSFET.
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Mohammad, Hameed Pasha, H. C. Hadimani, Udara Yedukondalu, and Srinivasa Rao Udara. "Distinct ρ-based model of silicon N-channel double gate MOSFET." International Journal of Reconfigurable and Embedded Systems (IJRES) 11, no. 1 (March 1, 2022): 71. http://dx.doi.org/10.11591/ijres.v11.i1.pp71-83.
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<span lang="EN-US">Growing endless demand for digital processing technology, to perform high speed computations with low power utilization and minimum propagation delay, the metal-oxide-semiconductor (MOS) technology is implemented in the areas of very large scale integrated (VLSI) circuit technology. But MOS technology is facing the challenges in linear scaling the transistors with different channel modelling for the present day microelectronic regime. Linear scaling of MOSFET is restricted through short-channel-effects (SCEs). Use of silicon N-channel double gate MOSFETs (DG MOSFETs) in present day microelectronic regime features the short channel effect of MOSFET through a reasaonable forward transfer admittance with the characteristics of varying input capacitance values ratio. In this research paper, a distinct ρ-based model is designed to simulate SCEs through the designed silicon N-channel double gate MOSFETs with the varying front and back gate doping level and surface regions to estimate the varying junction capacitances can limit the intrusion detection systems (IDS) usage in VLSI applications. Analytical model for channel length and simulated model for total internal device capacitance through distinct ρ-based model are presented. The proposed distinct ρ-based model is suitable for silicon nanowire transistors and the effectiveness of the proposed model is validated through comparative results.</span>
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Tanehira, Takafumi, T. Nakano, and Motoi Nakao. "Electrical Characteristics of MOSFETs Using 3C-SiC with Buried Insulating Layer." Materials Science Forum 645-648 (April 2010): 1009–12. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1009.
Full textAbstract:
Metal oxide semiconductor field effect transistors (MOSFETs) using SiC on insulator (SiC-OI) substrate with the structure of 3C-SiC (100)/SiO2/Si have been fabricated. SiC-OI substrates with SiC thicknesses of 100 nm and 600 nm are employed as starting materials and aluminum ions are implanted for p-regions or channel regions with a multi-implantation technique. Afterward, to form the source and drain regions, phosphorus ions are implanted. The gate oxide layer is grown in dry thermal oxidation, followed by post-oxidation annealing. Nickel is used as a contact material for the source and drain region, and aluminum is used for the gate material. From Id-Vd characteristics, 600 nm SiC-OI MOSFET is superior to 100 nm SiC-OI MOSFET. It is might that the crystalline quality of surface SiC layers affects the performance of MOSFET. SiC-OI MOSFET is operated successfully for the first time.
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Shin, Kanghee, Dongkyun Kim, Minu Kim, Junho Park, and Changho Han. "Enhanced Short-Circuit Robustness of 1.2 kV Split Gate Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistors for High-Frequency Applications." Electronics 14, no. 1 (January 3, 2025): 163. https://doi.org/10.3390/electronics14010163.
Full textAbstract:
Split Gate SiC MOSFETs (SG-MOSFETs) have been demonstrated to exhibit excellent power dissipation at high operating frequencies due to their low specific reverse transfer capacitance (Crss,sp); however, there are several reliability issues of SG-MOSFETs, including electric field crowding at the gate oxide and insufficient short-circuit (SC) robustness. In this paper, we propose a device structure to enhance the short-circuit withstand time (SCWT) of 1.2 kV SG-MOSFETs. The proposed P-shielded SG-MOSFETs (PSG-MOSFETs) feature a P-shielding region that expands the depletion region within the JFET region under both blocking mode and SC conditions. Compared to the conventional structure, this reduces the maximum electric field in the gate oxide, enabling a higher doping concentration in the JFET region, which can reduce the specific on-resistance (Ron,sp) to minimize power dissipation during device operation. The SC robustness of PSG-MOSFETs, with an Ron,sp identical to those of SG-MOSFETs, was investigated by adjusting the width of the P-shielding region (WP). Furthermore, the Crss,sp of PSG-MOSFETs was compared with that of SG-MOSFETs to analyze the relationship between the WP and high-frequency figure of merit (HF-FOM), defined as Ron,sp × Crss,sp. These results demonstrated that the PSG-MOSFET achieved an enhanced SC robustness and HF-FOM in comparison to the SG-MOSFET. Thus, the proposed PSG-MOSFET is a highly suitable candidate for high-frequency and reliable applications.
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Mrvić, Jovan, and Vladimir Vukić. "Comparative analysis of the switching energy losses in GaN HEMT and silicon MOSFET power transistors." Zbornik radova Elektrotehnicki institut Nikola Tesla 30, no. 30 (2020): 93–109. http://dx.doi.org/10.5937/zeint30-29318.
Full textAbstract:
The subject of this paper is the mutual comparison of switching energy losses in cascode gallium nitride HEMT and silicon "superjunction" MOSFET transistor, both designed for a maximum operating voltage of 650 V. For the purpose of analysis the transistor switching characteristics, the double pulse test method was implemented. Detailed computer simulation models developed in programs of the SPICE family were used. Data on transient turn -on and turn-off processes were generated by LTspice simulation tool, in a wide range of drain currents, using two different gate resistance values for driving the transistors under test. The obtained results indicate superior switching characteristics of gallium nitride devices in comparison to silicon components, especially during the high drain current transistor operation. During the one transistor switching cycle, the total energy losses in the GaN HEMT were simulated, for a drain current of 30 A, and found to be five to eight times lower when compared to tested Si MOSFET transistor.
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SPEDO, SERGIO, and CLAUDIO FIEGNA. "SIMULATION OF THERMAL NOISE IN SCALED MOSFETS." Fluctuation and Noise Letters 02, no. 02 (June 2002): L109—L116. http://dx.doi.org/10.1142/s0219477502000683.
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In this work, hydrodynamic device simulations and a post-processor for the simulation of noise in MOSFETs are applied in order to evaluate the impact of scaling on the thermal noise of transistors representative of technologies with minimum gate length scaled from 0.25 μm down to 0.1 μm. The dependences on bias and technology scaling of the spectral densities of the equivalent drain- and induced gate-noise currents are anayzed in details. The effect of technology scaling on the two-port noise parameters of the intrinsic MOSFET is studied as well. The results of this work confirm that the transistor's noise performance tend to improve as the technology is scaled down, making CMOS a suitable technological option for the implementation of advanced low-power RF systems.
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Ataseven, Ismail, Ilker Sahin, and Salih Baris Ozturk. "Design and Implementation of a Paralleled Discrete SiC MOSFET Half-Bridge Circuit with an Improved Symmetric Layout and Unique Laminated Busbar." Energies 16, no. 6 (March 21, 2023): 2903. http://dx.doi.org/10.3390/en16062903.
Full textAbstract:
Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) have many advantages compared to silicon (Si) MOSFETs: low drain-source resistance, high thermal conductivity, low leakage current, and high switching frequency. As a result, Si MOSFETs are replaced with SiC MOSFETs in many industrial applications. However, there are still not as many SiC modules to customize for each application. To meet the high-power requirement for custom applications, paralleling discrete SiC MOSFETs is an essential solution. However, it comes with many technical challenges; inequality in current sharing, different switching losses, different transient characteristics, and so forth. In this paper, the detailed MATLAB®/Simulink® Simpscape model of the SiC MOSFET from the datasheet and the simulation of the half-bridge circuit are investigated. Furthermore, this paper proposes the implementation of the four-paralleled SiC MOSFET half-bridge circuit with an improved symmetric gate driver layout. Moreover, a unique laminated busbar connected directly to the printed circuit board (PCB) is proposed to increase current and thermal capacity and decrease parasitic effects. Finally, the experimental and simulation results are presented using a 650 V SiC MOSFET (CREE) double-pulse test (DPT) circuit. The voltage overshoot problems and applied solutions are also presented.
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Casady, J. B., D. C. Sheridan, A. Ritenour, V. Bondarenko, and R. Kelley. "High Temperature Performance of Normally-off SiC JFET's Compared to Competing Approaches." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (January 1, 2010): 000152–59. http://dx.doi.org/10.4071/hitec-jcasady-tp23.
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Normally-off Silicon Carbide (SiC) power Junction Field Effect Transistors (JFETs) were compared with competing power transistor technology at temperatures from 25 °C to 150 °C as limited by the packaging. Switching energies were measured from 1200 V, 125 mΩ and 50 mΩ (room temperature) rated SiC power JFETs and compared with 900 V silicon (Si) super-junction Metal Oxide Semiconductors (MOSFETs) and 1200 V Si Insulated Gate Bipolar Transistors (IGBTs). For both comparisons, measured performance for the SiC power JFET was advantageous at all temperatures when switching at 50 kHz, including a total switching energy (ESW) of 97 μJ for the SiC JFET, compared with 158 μJ for the Si super-junction MOSFET, and 550 μJ for the Si IGBT at 25 °C. At 150°C, the ESW was 138 μJ for the SiC power JFET, 413 μJ for the Si super-junction MOSFET, and 1020 μJ for the Si IGBT. Increasing the die size of the 1200 V, normally-off SiC JFET by 2.25 resulted in an measured increase in switching energy of 2.7 and 2.37 at 25 °C and 150 °C, respectively, a quasi-linear relationship. Higher power preview products of the SiC normally-off JFET technology were also examined including a 1200 V, 25 mΩ (room-temperature rating) power JFET characterized up to 250 °C, and a module capable of 1200 V, 120 A DC performance at 25 °C.
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Al-Hadithi, Basil Mohammed, and Miguel Jimenez. "IGBT Overcurrent Capabilities in Resonant Circuits." Sensors 24, no. 23 (November 29, 2024): 7631. https://doi.org/10.3390/s24237631.
Full textAbstract:
The control of IGBT (insulated gate bipolar transistor) and MOSFET (metal oxide semiconductor field effect transistor) is of great interest nowadays as they are widely used in electric vehicles, photovoltaic applications, and a multitude of systems. The field of power electronics and their correct activation ensures that the transistors are operated without being destroyed. In this work, a double resonant transformer was built and used to produce very high currents. These currents are switched by a full bridge of resonant IGBT transistors to demonstrate the feasibility of exceeding the maximum permissible transistor currents in a resonant system. The system is controlled by the feedback from two current sensors. In this case the currents exceed in a 170% the peak current of the transistor without problems. In this way, resonant circuits with IGBT transistors can be designed with currents lower than the maximum currents of the resonant circuit, therefore reducing the cost of the circuit and reducing the switching losses to nearly zero.
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Wei, Xiaofeng, Hongxin Zhang, Lei Shu, Zhi Sun, Yuanzhen Wang, Yejing Wu, and Shichu Guan. "Analysis of electromagnetic radiation characteristics under TID radiation effects of trench-gate SiC MOSFETs." Journal of Instrumentation 20, no. 04 (April 1, 2025): P04005. https://doi.org/10.1088/1748-0221/20/04/p04005.
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Abstract This article is focused on the electromagnetic radiation effects of Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) under total ionizing dose (TID) effect. A 650V trench-gate SiC MOSFET was selected as the experimental subject. The variations in the electronic characteristics of SiC MOSFETs were explained from the perspective of crystal defects. Furthermore, an analysis of the trends in the electromagnetic radiation characteristics of the device was conducted based on the changes in the electrical properties of SiC devices. A broad network model for electromagnetic radiation signals from SiC MOSFETs was proposed. This model facilitates the prediction and assessment of the damage extent and operational status of SiC MOSFET power devices through electromagnetic radiation signals. Additionally, a method for evaluating the on-orbit cycle of SiC devices was introduced based on this network model, presenting a new approach for predicting the lifespan and reliability analysis of SiC MOSFETs operating in space.
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Kim, Chaeyun, Hyowon Yoon, Dong-Seok Kim, and Ogyun Seok. "Comparison Analysis of Radiation Effects on 1.2 kV SiC Metal-Oxide-Semiconductor Field-Effect Transistors with Gamma-Ray and Proton Irradiation." Electronics 13, no. 7 (April 3, 2024): 1352. http://dx.doi.org/10.3390/electronics13071352.
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TID effects occur in MOS-gated transistors in radiation environments where proton and gamma-rays irradiate the devices. TID effects seriously affect the electrical characteristics of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). They can eventually result in the malfunction of power systems when exposed to long-term radiation conditions. We irradiated gamma-rays and protons into 1.2 kV SiC MOSFETs and evaluated the change in electrical properties to analyze the TID’s effects. As a result of the experiment, the threshold voltage (VT) and on-resistance (Ron) of 1.2 kV SiC MOSFETs decreased because positive fixed charges inside the oxide increased depending on the radiation dose of the gamma-ray and fluence of the proton irradiations. The degradation of breakdown voltage (BV) occurred owing to a change in the depletion curvature at the edge of termination regions owing to the trapping of the charge in the field’s oxide.
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Priyanka Kumari, B. S., and Sobhit Saxena. "Design and Implementation of Efficient MOSFET’s Utilization Based Proposed Voltage Controlled Oscillator." Journal of Physics: Conference Series 2089, no. 1 (November 1, 2021): 012073. http://dx.doi.org/10.1088/1742-6596/2089/1/012073.
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Abstract Ring oscillator is a device which consists of NOT gates connected in the form of ring. This ring oscillator’s output oscillates between the true and false stages controlled by applied voltage. Now days this voltage controlled oscillator (VCO) becomes the heart of modern electronic devices and communication systems. Earlier five-stage complementary metal oxide semiconductor (CMOS) based VCO for the Phase Locked Loop (PLL) was implemented. High frequency oscillations are required for many applications and further it is observed that a very general technique is normally adopted by researchers to achieve high frequency that if number of transistors is increased then the frequency can be increased. But the consequences of increase in number of transistors are the increase in delay and more number of MOSFET occupies more area and more power dissipation. So, in this paper VCO is designed with efficient utilization of MOSFETs. There is a balance between frequency and number of transistors, so that the area and power dissipation can be reduced. From the obtained results it can observed that the number of MOSFET’s, Independent Nodes, boundary nodes total nodes and power are reduced compared to five stage VCO and VCO based Ring oscillator.
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Takeda, Hironori, Takuji Hosoi, Takayoshi Shimura, and Heiji Watanabe. "Evaluation of the Impact of Al Atoms on SiO2/ SiC Interface Property by Using 4H-SiC n+-Channel Junctionless MOSFET." Materials Science Forum 963 (July 2019): 171–74. http://dx.doi.org/10.4028/www.scientific.net/msf.963.171.
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To investigate the impact of Al atoms on channel mobility at SiO2/SiC interface, we fabricated the junctionless metal-oxide-semiconductor field-effect transistors (MOSFETs), in which thin n+-SiC epitaxial layers with and without Al+ ion implantation were used as a channel, and compared their electrical characteristics. The effective mobility (meff) of n+-channel junctionless MOSFET without Al doping was estimated to be 14.9 cm2/Vs, which is higher than inversion-mode MOSFET fabricated with the same gate oxidation condition (3.1 cm2/Vs). The meff values of the MOSFETs with low Al doping concentration (5´1017 and 1´1018 cm-3) were almost the same as that of Al-free MOSFET, and the device with the highest Al doping (5´1018 cm-3) exhibited slight mobility degradation of about 15% compared to the other devices. Hall mobility in thick n+ layer with the highest Al doping was also slightly degraded, suggesting that Al atoms in the channel are not the major cause of degraded SiO2/SiC interface property.