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Dissertations / Theses on the topic 'Tunnel FETs'

Author: Grafiati

Published: 6 September 2023

Last updated: 31 July 2025

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1

Horst, Fabian. "Compact DC Modeling of Tunnel-FETs." Doctoral thesis, Universitat Rovira i Virgili, 2019. http://hdl.handle.net/10803/668957.

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En l'última dècada, el transistor d'efecte de camp amb efecte túnel (TFET) ha guanyat molt interès i es maneja com un possible successor de la tecnologia MOSFET convencional. El transport de càrrega en un TFET es basa en el mecanisme de túnel de banda a banda (B2B) i, per tant, el pendent sub-llindar a temperatura ambient pot superar el límit de 60 mV / dec. Per descriure i analitzar el comportament del TFET en les simulacions de circuits, aquesta dissertació introdueix un model compacte de CC per TFET de doble comporta. L'enfocament de modelatge considera l'efecte túnel B2B amb l'efecte p

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Gräf, Michael. "Two-Dimensional Analytical Modeling of Tunnel-FETs." Doctoral thesis, Universitat Rovira i Virgili, 2017. http://hdl.handle.net/10803/450516.

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Basat en un mecanisme de transport de corrent de banda a banda, el túnel-FET és capaç de superar la limitació de pendent sub-llindar física del MOSFET de 60 mV /dec. Per tant, s'ha convertit en un dels dispositius més prometedors per ser el successor del MOSFET clàssic en els últims anys. Aquesta tesi descriu tots els passos necessaris per modelar analíticament un Túnel-FET de doble porta. El model inclou una solució electrostàtica de dues dimensions en totes les regions del dispositiu, el que permet fins i tot simulacions hetero-unió del dispositiu. Per a un comportament més realista del dis

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3

Yu, Tao Ph D. Massachusetts Institute of Technology. "InGaAs/GaAsSb type-Il heterojunction vertical tunnel-FETs." Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84857.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 59-62).<br>The supply voltage (VDD) scaling of conventional CMOS technology is approaching its limit due to the physical limit of 60 mV/dec subthreshold swing (SS) at room temperature and the requirement for controlled leakage current. In order to continue VDD scaling for low power applications, novel device structures with steep SS have been proposed. Tunnel-FETs (TFETs) are among the most attra

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Farokhnejad, Atieh. "Compact Modeling of Intrinsic Capacitances in Double-Gate Tunnel-FETs." Doctoral thesis, Universitat Rovira i Virgili, 2020. http://hdl.handle.net/10803/669806.

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La miniaturització dels MOSFET en els circuits integrats ha elevat la tecnologia microelectrònica. Aquesta tendència també augmenta el grau de complexitat d'aquests circuits i els seus components bàsics. En els MOSFET convencionals, el corrent es basa en l'emissió termoiònica de portadors de càrrega, que per això limita el pendent subumbral en aquests transistors a 60 mV / dec. Per tant, per superar aquest límit i continuar amb la miniaturització per mantenir el ritme de la llei de Moore, es requereixen estructures alternatives. Entre aquestes, el transistor d'efecte de camp per túnel (TFET) e

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5

Yu, Tao Ph D. Massachusetts Institute of Technology. "InGaAs/GaAsSb quantum-well Tunnel-FETs for ultra-low power applications." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/106101.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references.<br>The Tunnel-FET (TFET), where carrier injection is determined by gate-controlled tunneling from the source to the channel, has been attractive as one of the promising candidates for future ultra-low power applications. In this thesis, inline-TFETs with tunneling direction aligned to the gate electric field are designed, fabricated and analyzed based on InGaAs/GaAsSb material. Using ultrathin In

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6

Cavalheiro, David. "Ultra-low power circuits based on tunnel FETs for energy harvesting applications." Doctoral thesis, Universitat Politècnica de Catalunya, 2017. http://hdl.handle.net/10803/406391.

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There has been a tremendous evolution in integrated circuit technology in the past decades. With the scaling of complementary metal-oxide-semiconductor (CMOS) transistors, faster, less power consuming and more complex chips per unit area have made possible electronic gadgets to evolve to what we see today. The increasing demand in electronic portability imposes low power consumption as a key metric to analog and digital circuit design. While dynamic power consumption decreases quadratically with the decrease of power supply voltage, leakage power presents a limitation due to the inverse sub-t

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7

Richter, Simon [Verfasser]. "Strained silicon and silicon-germanium nanowire tunnel FETs and inverters / Simon Richter." Aachen : Hochschulbibliothek der Rheinisch-Westfälischen Technischen Hochschule Aachen, 2014. http://d-nb.info/1059533189/34.

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8

Narimani, Keyvan [Verfasser], Joachim [Akademischer Betreuer] Knoch, and Siegfried [Akademischer Betreuer] Mantl. "Silicon tunnel FETs for digital and analogue applications / Keyvan Narimani ; Joachim Knoch, Siegfried Mantl." Aachen : Universitätsbibliothek der RWTH Aachen, 2018. http://d-nb.info/121148758X/34.

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9

Narimani, Keyvan Verfasser], Joachim [Akademischer Betreuer] [Knoch, and Siegfried [Akademischer Betreuer] Mantl. "Silicon tunnel FETs for digital and analogue applications / Keyvan Narimani ; Joachim Knoch, Siegfried Mantl." Aachen : Universitätsbibliothek der RWTH Aachen, 2018. http://d-nb.info/121148758X/34.

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10

Blaeser, Sebastian Verfasser], Siegfried [Akademischer Betreuer] [Mantl, and Christoph [Akademischer Betreuer] Stampfer. "Strained Silicon-Germanium/Silicon Heterostructure Tunnel FETs for Low Power Applications / Sebastian Blaeser ; Siegfried Mantl, Christoph Stampfer." Aachen : Universitätsbibliothek der RWTH Aachen, 2016. http://d-nb.info/1126646431/34.

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11

Riederer, Felix [Verfasser]. "Skalierung von Tripel & Multi Backgate Bauteilen für die Herstellung von Tunnel- & Superlattice-FETs / Felix Riederer." München : Verlag Dr. Hut, 2018. http://d-nb.info/1164293710/34.

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12

Blaeser, Sebastian [Verfasser], Siegfried [Akademischer Betreuer] Mantl, and Christoph [Akademischer Betreuer] Stampfer. "Strained Silicon-Germanium/Silicon Heterostructure Tunnel FETs for Low Power Applications / Sebastian Blaeser ; Siegfried Mantl, Christoph Stampfer." Aachen : Universitätsbibliothek der RWTH Aachen, 2016. http://d-nb.info/1126646431/34.

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13

Luong, Gia Vinh Verfasser], Joachim [Akademischer Betreuer] [Knoch, and Siegfried [Akademischer Betreuer] Mantl. "Gate-All-Around Silicon Nanowire Tunnel FETs for Low Power Applications / Gia Vinh Luong ; Joachim Knoch, Siegfried Mantl." Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://d-nb.info/1162559780/34.

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14

Sterkel, Martin. "Ultra-Kurzkanal Tunnel-Feldeffekt-Transistoren auf Silizium- und SOI-Substraten." Göttingen Cuvillier, 2008. http://d-nb.info/990746445/04.

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15

Ramesh, Anisha. "TUNNELING BASED QUANTUM FUNCTIONAL DEVICES AND CIRCUITS FOR LOW POWER VLSI DESIGN." The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1338315073.

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16

Haffner, Thibault. "Elaboration et intégration de nanofils GeSn pour la réalisation de dispositifs nanoélectroniques basse consommation." Thesis, Université Grenoble Alpes, 2020. https://tel.archives-ouvertes.fr/tel-03066536.

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Depuis les années 60, le développement technologique est principalement porté par la miniaturisation des composants et suit la fameuse conjoncture de Moore. En effet, la miniaturisation apportait, au début, de nombreux avantages. Temps de commutation plus faible, systèmes plus compacts, tension d'alimentation plus faible, et donc, transistors consommant moins, etc. Seulement, cette approche a commencé à s'essouffler ces dernières années. En effet , les limites de la miniaturisation ont commencés à apparaitre et la puissance consommée globale des circuits a commencé à augmenter ce qui limite la

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17

Brouzet, Virginie. "Réalisation et étude des propriétés électriques d'un transistor à effet tunnel 'T-FET' à nanofil Si/SiGe." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT120/document.

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La demande d’objets connectés dans notre société est très importante, au vu du marché florissant des smartphones. Ces nouveaux objets technologiques ont pour avantage de regrouper plusieurs fonctions en un seul objet ultra compact. Cette diversité est possible grâce à l’avènement des systèmes-sur-puce (SoC, System-on-Chip) et à la miniaturisation extrême des composants. Les SoC s’intègrent dans l’approche « More than Moore » et demande une superficie importante des puces. Celle-ci peut-être réduite par l’utilisation d’une autre approche appelée « More Moore » qui fut largement utilisée ces der

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18

Fu, Yen-Chun. "Realisation of III-V Tunnel-FET with in-situ ultimate scaled gate stack for high performance power efficient CMOS." Thesis, University of Glasgow, 2018. http://theses.gla.ac.uk/30588/.

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The main objective of this thesis is realising a non-planar III-V Tunnel-FET for low power device applications. The differentiating aspect of this work is based around clustered inductively coupled plasma (ICP) etch and atomic layer deposition (ALD) tools. This approach was intended to mitigate native oxide formation on etched III-V surfaces prior to gate stack deposition by ALD. The use of a cluster tool also offers the benefit of cleaning III-V surfaces “in-situ” using low damage plasma based approaches. In addition, activity on scaling the equivalent oxide thickness of the gate stack and ev

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19

Wan, Jing. "Dispositifs innovants à pente sous le seuil abrupte : du TEFT au Z²-FET." Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00845632.

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Tunnel à effet de champ (TFET) et un nouveau composant MOS à rétroaction que nous avons nommé le Z2-FET.Le Z2-FET est envisagé pour la logique faible consommation et pour les applications mémoire compatibles avecles technologies CMOS avancées. Nous avons étudié de manière systématique des TFETs avec différents oxydesde grille, matériaux et structures de canal, fabriqués sur silicium sur isolant totalement déserté (FDSOI). Lesmesures de bruit à basse fréquence (LFN) sur TFETs montrent la prédominance d'un signal aléatoiretélégraphique (RTS), qui révèle sans ambiguïté le mécanisme d'effet tunnel

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20

Revelant, Alberto. "Modélisation, simulation et caractérisation de dispositifs TFET pour l'électronique à basse puissance." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT022.

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Dans les dernières années, beaucoup de travail a été consacré par l’industrie électronique pour réduire la consommation d’énergie des composants micro-électroniques qui représente un fardeau important dans la spécification des nouveaux systèmes.Afin de réduire la consommation d’énergie, nombreuses stratégies peuvent être adoptées au niveau des systèmes micro-électroniques et des simples dispositifs nano-électroniques. Récemmentle Transistor Tunnel `a effet de champ (Tunnel-FET) s’est imposé comme un candidat possible pour remplacer les dispositifs MOSFET conventionnels pour applications de tr`

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21

Viereck, Cornelius. "A computer-controlled passive multi-harmonic tuner used to optimise a power FET up to the third harmonic." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0006/MQ42929.pdf.

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22

Diaz, llorente Carlos. "Caractérisation de transistors à effet tunnel fabriqués par un processus basse température et des architectures innovantes de TFETs pour l’intégration 3D." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT096/document.

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Cette thèse porte sur l’étude de transistor à effet tunnel (TFET) en FDSOI à géométries planaire et triple grille/nanofils. Nous rapportons pour la première fois des TFETs fabriqués par un processus basse température (600°C), qui est identique à celui utilisé pour l’intégration monolithique 3D. La méthode “Dual IDVDS” confirme que ces TFETs fonctionnent par effet tunnel et non pas par effet Schottky. Les résultats des mesures électriques montrent que l’abaissement de la température de fabrication de 1050°C (HT) à 600°C (LT) ne dégrade pas les propriétés des TFETs. Néanmoins, les dispositifs ré

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23

Pallempati, Mallikarjunarao. "Investigation on Spacer Engineered Multigate Tunnel FETs." Thesis, 2016. http://ethesis.nitrkl.ac.in/9274/1/2016_MT_MPallempati.pdf.

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In this modern era of semiconductor technology, the number of transistors per chip are increasing continuously for designing a computing system to perform innumerable of functions with tremendous speed. Thus, the electronics industry is constantly facing the challenge of miniaturization of transistors to increase the package density. Hence scaling of CMOS technology is essential in nano-electronic regime which leads to increase of static power consumption and thus conventional MOSFETs are unsuitable in this situation due to Short Channel Effects (SCEs). Hence the non-conventional devices becam

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Mathew, S. "Performance analysis of Dual Material Gate (DMG) Silicon on Insulator (SOI) tunnel fets." Thesis, 2014. http://ethesis.nitrkl.ac.in/6167/1/E-46.pdf.

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As modern day computing systems are designed to perform innumerable number of functions with tremendous speed, the number of circuits to be accommodated in a chip keeps increasing day by day. Hence electronics industry constantly faces the challenge of miniaturization of transistors to increase the package density and thus linear scaling of CMOS technology has become a necessity in the present day microelectronic and nano-electronic regime. This leads to a major crisis of static power consumption and hence conventional MOSFETs fail to be a suitable candidate to handle the situation. Also Short

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Wang, Chiu-Ting, and 王秋婷. "Performance Enhancement of III-V Tunnel FETs considering Line Tunneling and Non-uniform Channel Thickness." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/wh3py3.

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碩士<br>國立中央大學<br>電機工程學系<br>106<br>Power scaling is one of the major challenges in modern CMOS technology for ultra-low power applications, such as emerging IoT (Internet of Things) technologies and wearable devices. Lowering the supply voltage (Vdd) is an efficient technique to achieve ultra-low power consumption for circuits. Device with steep subthreshold slope is essential in order to achieve energy-efficient switching and low leakage power as supply voltage scaling. Conventional MOSFET exhibits the lower-bound limitation of subthreshold swing (SS) which is about 60 mV/dec at room temperatur

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Palle, Dharmendar Reddy. "Modeling of graphene-based FETs for low power digital logic and radio frequency applications." 2013. http://hdl.handle.net/2152/22008.

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There are many semiconductors with nominally superior electronic properties compared to silicon. However, silicon became the material of choice for MOSFETs due to its robust native oxide. With Moore's observation as a guiding principle, the semiconductor industry has come a long way in scaling the silicon MOSFETs to smaller dimensions every generation with engineering ingenuity and technological innovation. As per the 2012 International Technology Roadmap for Semiconductors (ITRS), the MOSFET is expected to be scaled to near 6 nm gate length by 2025. However, materials, design and fabrication

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Wang, Yu-Wei, and 王佑瑋. "Theoretical Investigation of Optimized Nanowire Diameter and Short Channel Effects for Gate-All-Around III-V Tunnel FETs." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/44732999900811713543.

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碩士<br>國立交通大學<br>電子研究所<br>105<br>This thesis investigates the diameter dependence for III-V gate-all-around homojunction and heterojunction TFET using TCAD numerical simulation. The optimized diameter has been shown due to the counterbalance of the gate control and the quantum confinement effect. In addition, model calculation for the homojunction TFET is proposed and verified with TCAD numerical simulation. Source and drain depletion is very important in modeling of TFET. The diameter dependence by model calculation also shows the same trend with TCAD numerical simulation. Finally, the short c

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Bhattacharjee, Shubhadeep. "Materials, Processes and Device Design for High Performance, Sub-thermionic MoS2 FETs." Thesis, 2018. https://etd.iisc.ac.in/handle/2005/4268.

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The shrinking of the field-effect transistor (FET), commonly termed CMOS scaling, has revolutionised the semiconductor industry and impacted most aspects of human life. However, this decades-long successful trend of scaling the FET is now facing serious fundamental and technological challenges resulting in diminishing economic returns. The first challenge is that, as device dimensions shrink, electric fields in close proximity start to interfere with each other and disrupt the transistor’s operations. This phenomenon is called the short channel effect (SCE). Second, concurrent (quadratic) redu

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Lin, Po-Shao, and 林柏劭. "A Study on Performance Evaluation of Fin Epitaxial Tunnel Layer Tunnel FET and Performance Improvement of n-type Epitaxial Tunnel Layer Tunnel FET." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/tf69y7.

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碩士<br>國立交通大學<br>電子研究所<br>105<br>Epitaxial tunnel layer (ETL) tunnel FET (TFET) has been considered to be one of the promising devices in ultra-low power applications. In this study, the performance of the planar ETL TFET and fin ETL TFET for both n-type and p-type, respectively, are evaluated by Sentaurus TCAD simulation. In addition, TFET that is doped by solid-phase diffusion (SPD) instead of ions implantation was proposed and fabricated. In the previous research, the n-type and p-type ETL TFET show the steep subthreshold swing and high on-state current in the planar structure by TCAD simula

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Wang, Pei-Yu, and 王培宇. "A Study on Tunnel FET with Epitaxial Tunnel Layer Structure." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/90836541544090748423.

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博士<br>國立交通大學<br>電子工程學系電子研究所<br>104<br>In this dissertation, tunnel field-effect-transistor (TFET) utilizing band-to-band tunneling (BTBT) as the operation mechanism is studied. To realize the basic characteristics and the design issues for the novel device, the effects of the source junction profiles and the trap-assisted tunneling (TAT) on the bulk TFET are investigated. To further improve the TFET performance, a CMOS process compatible TFET with epitaxial tunnel layer (ETL) structure is proposed. Various device parameters of complementary ETL TFETs (CTFETs) are studied and discussed in deta

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Kumar, S., and K. K. Majhi. "Atlas simulation based study of SOI tunnel fet." Thesis, 2014. http://ethesis.nitrkl.ac.in/5615/1/e-63.pdf.

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It is observed that there are basically two limitations with the conventional mosfet, especially sub-threshold swing swings. Its minimum value being 60 mv/decade. But we cannot decrease it lesser. In order to decrease sub-threshold further, we use tunnel fet to reduce swing to some-what less value than conventional mosfet. It works on tunnelling effect.

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32

Teng, Chien-Hong, and 鄧建鴻. "TCAD Design of InAs Gate-All-Around Nanowire Tunnel FET Structures." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/g73uyt.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>105<br>The electrical characteristics of InAs-Si heterojunction GAA NW TFET are simulated using Sentaurus TCAD produced by Synopsys. Results show that InAs-Si heterojunction can enlarge the on-state current compared with Si homo-junction and GAA structure can improve the subthreshold slope compared with single gate structure. The reasons are that the tunnel barrier width of InAs-Si heterojunction is smaller than Si homo-junction and the GAA structure has better gate control than single gate structure. Besides, the diameter of nanowire scarcely affects the performan

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Medhi, S. "Atlas based simulation study of junctionless double gate (DG) tunnel FET." Thesis, 2014. http://ethesis.nitrkl.ac.in/5613/1/E-62.pdf.

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Tunnel Field Effect Transistor has recently attracted the attention of many researchers through its high Ion/Ioff ratio and a very less subthreshold slope. In this work Junction-less double gate tunnel field effect transistor’s performance has been studied which has been designed using charge plasma concept which can form the source and drain regions without the need for any doping by choosing appropriate work functions for the source and drain metal electrodes. A very important parameter of this device has been studied, i.e. the threshold voltage of this device. It has been seen that the vari

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Lin, Yu-cheng, and 林鈺城. "Investigation of Drain Lapping Effect on Tunnel-FET With Poly-Si Channel Film." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/60553590438101130651.

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碩士<br>國立中山大學<br>電機工程學系研究所<br>104<br>The purpose of the research was to study the drain lapping effect of tunneling field-effect transistors (TFETs) with polycrystalline-silicon (poly-Si) channel. The transfer characteristics of source to gate overlap 2m and different drain to gate lapping length indicated that overlap is not sensitive to overlap length and measurement temperature. For this reason, the TFETs with poly-Si channel device have strong immunity against the short channel effect. When the tunneling field-effect transistors reverse turn on, the carrier transport behavior starts with

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Chang, Kang, and 張綱. "Impacts of Ammonia Plasma Treatment on Tunnel-FET With Poly-Si Channel Film." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/13814733054789780118.

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碩士<br>國立中山大學<br>電機工程學系研究所<br>104<br>To obtain the faster operation speed and lower cost in fabrication，Channel length is continuously scaling down. However, negligible short channel effect(SCE) are observed and lead to increased of leakage current and reduce gate control ability. Tunnel Field-effect transistor is proposed to replace MOSFET in future. Unlike traditional inversion mode transistors, band-to-band tunneling is the mainly carrier transport mechanism. The subthreshold swing(S.S.) of T-FET can overcome the limitation of 60mV/dec of MOSFET.T-FET can also suppressed the leakage current

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Hsu, Chie-Wei, and 徐誌緯. "Simulation and Investigation of Random Variations for III-V Broken-Gap Heterojunction Tunnel FET." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/75704934585062201395.

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碩士<br>國立交通大學<br>電子工程學系電子研究所<br>103<br>This thesis compares and investigates the impacts of metal-gate work-function variation (WFV) and source random-dopant-fluctuation (source RDF) for III-V broken-gap heterojunction TFET (HTFET), homojunction TFET and FinFET devices using 3-D atomistic Monte Carlo simulation. Our study indicates that the HTFET exhibts higher susceptibility to WFV near OFF state due to its broken-gap nature. For ON current variation, both the HTFET and homojunction TFET show better immunity to WFV than the III-V FinFET. Device design using source-side underlap to mitigate th

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Gupta, Akancha, and 古璦卡. "Design of Low Voltage Vertical Channel-Tunnel FET (VC-TFET) Using Ge/SiGe Materials." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/k3s7eq.

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碩士<br>國立交通大學<br>電機資訊國際學程<br>107<br>Abstract In this thesis, tunneling field-effect-transistor (TFET) based on the mechanism of band-to-band tunneling (BTBT), has been studied extensively. TFET is considered as a potential low voltage and low power transistors in certain applications for next generation transistors. Since the operating mechanism of TFET and MOSFET are different, hence, TFET is able to avoid many of the reliability and short channel issues. TFFT has the capability of achieving the sub-threshold slope of less than 60 mV/decade and small leakage current. These characteristics all

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Lee, Ko-Chun, and 李克駿. "Investigation and Comparison of Important Analog Figures of Merit for Tunnel FET and FinFET Considering Random Variations." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/01098490544975302839.

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碩士<br>國立交通大學<br>電子工程學系電子研究所<br>102<br>This thesis investigates and compares the impacts of metal-gate work function variation (WFV) and fin line edge roughness (fin LER) on the important analog FOMs (figures of merit) for TFET and FinFET devices using atomistic TCAD simulations. Our study indicates that under similar devices structure and comparable IOFF, the variability comparison between TFET and FinFET may yield different results depending on the dominant variation source for a given analog FOM. Under WFV, TFET exhibits better immunity to WFV than FinFET regarding gm/ID, Rout and intrinsic

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Chen, Yin-Nien, and 陳盈年. "Design and Analysis of Nanoscale FinFET and Tunnel FET Devices for Ultra-Low-Power SRAM, Logic and Analog Applications." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/03420513770720030664.

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博士<br>國立交通大學<br>電子工程學系電子研究所<br>104<br>The goal of this dissertation is to provide an extensive assessment of nanoscale FinFET and TFET devices for ultra-low-power application in SRAM, logic and analog. Device-circuit interactions and co-optimizations are considered to demonstrate the advantages and concerns of these emerging devices based circuits from both the device and circuit point of view. Through our analysis, impacts of device characteristics and low-VDD operation on the leakage/delay and stability/performance of logic circuits and SRAMs, on the power/performance of analog circuits are

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Su, Yen-So, and 蘇彥守. "Design and Simulation of Improved Swing and Ambipolar Effect for Tunnel FET by Band Engineering Using Metal at Drain Side." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/bfs697.

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Ramesha, A. "Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor." Thesis, 2008. https://etd.iisc.ac.in/handle/2005/792.

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The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). U

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Ramesha, A. "Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor." Thesis, 2008. http://hdl.handle.net/2005/792.

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The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). U

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Fan, Ming-Long, and 范銘隆. "Design and Analysis of Nanoscale FinFET, Tunnel FET and Hetero-Channel 3D Integrated Ultra-Thin-Body Devices for Ultra-Low-Power SRAM and Logic Circuits." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/25878819945473509609.

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博士<br>國立交通大學<br>電子工程學系電子研究所<br>103<br>This dissertation provides an extensive assessment of nanoscale FinFET, Tunnel FET (TFET) and hetero-channel 3D integrated Ultra-Thin-Body (UTB) MOSFET for ultra-low-power applications. Device-circuit interactions and co-optimizations are considered to demonstrate the potential and concerns of these emerging devices from the device/circuit point of view. Through our analysis, the impacts of device variability and low-VDD operation on the leakage/delay and stability/performance of logic circuits and SRAM cells are evaluated to offer insights for future low

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Hanna, Amir. "Non-Planar Nanotube and Wavy Architecture Based Ultra-High Performance Field Effect Transistors." Diss., 2016. http://hdl.handle.net/10754/621933.

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This dissertation presents a unique concept for a device architecture named the nanotube (NT) architecture, which is capable of higher drive current compared to the Gate-All-Around Nanowire architecture when applied to heterostructure Tunnel Field Effect Transistors. Through the use of inner/outer core-shell gates, heterostructure NT TFET leverages physically larger tunneling area thus achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. We discuss the physics of p-type (Silicon/Indium Arsenide) and n-type (Silicon/Germanium hetero-structure) based

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(7025126), Ahmedullah Aziz. "Device-Circuit Co-Design Employing Phase Transition Materials for Low Power Electronics." Thesis, 2019.

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<div> <div> <p>Phase transition materials (PTM) have garnered immense interest in concurrent post-CMOS electronics, due to their unique properties such as - electrically driven abrupt resistance switching, hysteresis, and high selectivity. The phase transitions can be attributed to diverse material-specific phenomena, including- correlated electrons, filamentary ion diffusion, and dimerization. In this research, we explore the application space for these materials through extensive device-circuit co-design and propose new ideas harnessing their unique electrical properties. The abrupt transi

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