Relevant bibliographies by topics / Tunnel field-effect-transistor

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Tunnel field-effect-transistor'

Author: Grafiati
Published: 4 June 2021
Last updated: 13 June 2025

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Journal articles on the topic "Tunnel field-effect-transistor"

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Ghosh, Bahniman, and Mohammad Waseem Akram. "Junctionless Tunnel Field Effect Transistor." IEEE Electron Device Letters 34, no. 5 (2013): 584–86. http://dx.doi.org/10.1109/led.2013.2253752.

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Bhuwalka, K. K., S. Sedlmaier, A. K. Ludsteck, C. Tolksdorf, J. Schulze, and I. Eisele. "Vertical Tunnel Field-Effect Transistor." IEEE Transactions on Electron Devices 51, no. 2 (2004): 279–82. http://dx.doi.org/10.1109/ted.2003.821575.

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Fahad, M. S., A. Srivastava, A. K. Sharma, C. Mayberry, and K. M. Mohsin. "Silicene Nanoribbon Tunnel Field Effect Transistor." ECS Transactions 75, no. 5 (2016): 175–81. http://dx.doi.org/10.1149/07505.0175ecst.

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Ilatikhameneh, Hesameddin, Tarek A. Ameen, Gerhard Klimeck, Joerg Appenzeller, and Rajib Rahman. "Dielectric Engineered Tunnel Field-Effect Transistor." IEEE Electron Device Letters 36, no. 10 (2015): 1097–100. http://dx.doi.org/10.1109/led.2015.2474147.

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Katkov, V. L., and V. A. Osipov. "Planar graphene tunnel field-effect transistor." Applied Physics Letters 104, no. 5 (2014): 053102. http://dx.doi.org/10.1063/1.4863820.

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Lee, Won Joo, Hee Tae kwon, Hyun-Suk Choi, Deahoon Wee, Sangwan Kim, and Yoon Kim. "Reconfigurable U-shaped tunnel field-effect transistor." IEICE Electronics Express 14, no. 20 (2017): 20170758. http://dx.doi.org/10.1587/elex.14.20170758.

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Park, Jaesoo, and Changhwan Shin. "Tunnel Field-Effect Transistor With Segmented Channel." IEEE Journal of the Electron Devices Society 7 (2019): 621–25. http://dx.doi.org/10.1109/jeds.2019.2919331.

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Harvey-Collard, Patrick, Dominique Drouin, and Michel Pioro-Ladrière. "A silicon nanocrystal tunnel field effect transistor." Applied Physics Letters 104, no. 19 (2014): 193505. http://dx.doi.org/10.1063/1.4876765.

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Convertino, C., C. B. Zota, H. Schmid, A. M. Ionescu, and K. E. Moselund. "III–V heterostructure tunnel field-effect transistor." Journal of Physics: Condensed Matter 30, no. 26 (2018): 264005. http://dx.doi.org/10.1088/1361-648x/aac5b4.

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Nam, Hyohyun, Min Hee Cho, and Changhwan Shin. "Symmetric tunnel field-effect transistor (S-TFET)." Current Applied Physics 15, no. 2 (2015): 71–77. http://dx.doi.org/10.1016/j.cap.2014.11.006.

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Dissertations / Theses on the topic "Tunnel field-effect-transistor"

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Zhu, Yan. "Mixed As/Sb and tensile strained Ge/InGaAs heterostructures for low-power tunnel field effect transistors." Diss., Virginia Tech, 2014. http://hdl.handle.net/10919/47791.

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Reducing supply voltage is a promising way to address the power dissipation in nano-electronic circuits. However, the fundamental lower limit of subthreshold slope (SS) within metal-oxide-semiconductor field-effect transistors (MOSFETs) is a major obstacle to further scaling the operation voltage without degrading ON/OFF-ratio in today's integrated circuits. Tunnel field-effect transistors (TFETs) benefit from steep switching characteristics due to the quantum-mechanical tunneling injection of carriers from source to channel, rather than by conventional thermionic emission in MOSFETs. TFETs based on group III-V compound semiconductor and Ge heterostructures further improve the ON-state current and reduce SS due to the low bandgap energies and smaller carrier tunneling mass. The mixed arsenide/antimonide (As/Sb) InxGa1-xAs/GaAsySb1-y and Ge/InxGa1-xAs heterostructures allow a wide range of bandgap energies and various band alignments depending on the alloy compositions in the source and channel materials. Band alignments at source/channel heterointerface can be well modulated by carefully controlling the compositions of the InxGa1-xAs or GaAsySb1-y. In particular, this research systematically investigate the development and optimization of low-power TFETs using mixed As/Sb and Ge/InxGa1-xAs based heterostructures including: basic working principles, design considerations, material growth, interface engineering, material characterization, band alignment determination, device fabrication, device performance investigation, and high-temperature reliability. A comprehensive study of TFETs using mixed As/Sb and Ge/InxGa1-xAs based heterostructures shows superior structural properties and distinguished device performances, both of which indicate the mixed As/Sb and Ge/InxGa1-xAs based TFET as a promising option for high performance, low standby power and energy efficient logic circuit application.<br>Ph. D.
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Clavel, Michael Brian. "Tensile-Strained Ge/InₓGa₁₋ₓAs Heterostructures for Electronic and Photonic Applications". Thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/78129.

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The continued scaling of feature size in silicon (Si)-based complimentary metal-oxide-semiconductor (CMOS) technology has led to a rapid increase in compute power. Resulting from increases in device densities and advances in materials and transistor design, integrated circuit (IC) performance has continued to improve while operational power (VDD) has been substantially reduced. However, as feature sizes approach the atomic length scale, fundamental limitations in switching characteristics (such as subthreshold slope, SS, and OFF-state power dissipation) pose key technical challenges moving forward. Novel material innovations and device architectures, such as group IV and III-V materials and tunnel field-effect transistors (TFETs), have been proposed as solutions for the beyond Si era. TFETs benefit from steep switching characteristics due to the band-to-band tunneling injection of carriers from source to channel. Moreover, the narrow bandgaps of III-V and germanium (Ge) make them attractive material choices for TFETs in order to improve ON-state current and reduce SS. Further, Ge grown on InₓGa₁₋ₓAs experiences epitaxy-induced strain (ε), further reducing the Ge bandgap and improving carrier mobility. Due to these reasons, the ε-Ge/InₓGa₁₋ₓAs system is a promising candidate for future TFET architectures. In addition, the ability to tune the bandgap of Ge via strain engineering makes ε-Ge/InₓGa₁₋ₓAs heterostructures attractive for nanoscale group IV-based photonics, thereby benefitting the monolithic integration of electronics and photonics on Si. This research systematically investigates the material, optical, and heterointerface properties of ε-Ge/InₓGa₁₋ₓAs heterostructures on GaAs and Si substrates. The effect of strain on the heterointerface band alignment is comprehensively studied, demonstrating the ability to modulate the effective tunneling barrier height (Ebeff) and thus the threshold voltage (VT), ON-state current, and SS in future ε-Ge/InₓGa₁₋ₓAs TFETs. Further, band structure engineering via strain modulation is shown to be an effective technique for tuning the emission properties of Ge. Moreover, the ability to heterogeneously integrate these structures on Si is demonstrated for the first time, indicating their viability for the development of next-generation high performance, low-power logic and photonic integrated circuits on Si.<br>Master of Science
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Eckert, Hagen. "Multiskalensimulation des Ladungstransports in Silizium-Nanodraht-Transistoren." Master's thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-98748.

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Durch Multiskalensimulationen wird der Ladungstransport in nanodrahtbasierten Schottky-Barrieren-Feldeffekt-Transistoren im Materialsystem Ni2Si/Si untersucht. Die Bedingungen an die Genauigkeit der verwendeten Eingangsparameter werden bestimmt und Vorhersagen über optimale Material- und Geräteparameter werden getroffen. Es wird die Frage beantwortet, ob die Bestimmung von physikalischen Parametern aus einzelnen gemessenen Strom-Spannungs-Kennlinie möglich ist. Der Feldeffekt wird durch Berechnungen auf Basis der Finiten-Elemente-Methode und die resultierenden Stromflüsse durch ein quantenmechanisches Transportmodell ermittelt. In der Untersuchung der geometrischen Eingangsparameter wird gezeigt, dass bis auf den Radius des Nanodrahtes die in einem Experiment zu erwartenden Messfehler keinen drastischen Einfluss auf die Strom-Spannungs-Kennlinie haben. Signifikant ist hingegen der Einfluss der Temperatur, der effektiven Ladungsträgermassen und der Höhe der Schottky-Barriere. Da diese drei Eingangsparameter des betrachteten Systems mit relativ großen Ungenauigkeiten behaftet sind, ist die Bestimmung von physikalischen Parametern aus einzelnen gemessenen Strom-Spannungs-Kennlinien auf die erhoffte Weise nicht möglich. Die Arbeit zeigt auch, dass bereits moderate Veränderungen der Arbeitstemperatur einen bedeutenden Einfluss auf die Strom-Spannungs-Kennlinie haben. Für die Konstruktion von Transistoren mit hoher Stromdichte kann anhand der ermittelten Daten die Verkleinerung der aktiven Region durch Oxidation vorgeschlagen werden<br>Charge transport in nanowire-based Schottky-barrier field-effect transistors in the material system Ni2Si/Si is examined by multi-scale simulations. The requirements for the accuracy of the input parameters are determined and predictions about optimum material and device parameters are made. The question is answered, whether the determination of physical parameters from individual measured current-voltage curves is possible? The field effect is described by calculations based on the finite element method and the resulting currents are calculated with a quantum mechanical transport model. In the study of the geometric input parameters it is shown that experimental uncertainties do not drastically affect the current-voltage characteristic, except from the nanowire radius. However, significant is the influence of the temperature, the effective charge carrier mass and the height of the Schottky-barrier. Since these three input parameters are known only with low experimental accuracy for the considered system, the determination of physical parameters from individual measured current-voltage curves is not possible in the expected way. The results also show that moderate changes of the working temperature have a significant influence on the current-voltage characteristic. For the construction of transistors with high current density the reduction of the active region by oxidation is proposed
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Mohammad, Azhar. "EMERGING COMPUTING BASED NOVEL SOLUTIONS FOR DESIGN OF LOW POWER CIRCUITS." UKnowledge, 2018. https://uknowledge.uky.edu/ece_etds/125.

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The growing applications for IoT devices have caused an increase in the study of low power consuming circuit design to meet the requirement of devices to operate for various months without external power supply. Scaling down the conventional CMOS causes various complications to design due to CMOS properties, therefore various non-conventional CMOS design techniques are being proposed that overcome the limitations. This thesis focuses on some of those emerging and novel low power design technique namely Adiabatic logic and low power devices like Magnetic Tunnel Junction (MTJ) and Carbon Nanotube Field Effect transistor (CNFET). Circuits that are used for large computations (multipliers, encryption engines) that amount to maximum part of power consumption in a whole chip are designed using these novel low power techniques.
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Lai, Quan-Yu, and 賴冠瑜. "Multilayer SnSe2/MoTe2/hBN Tunnel Field Effect Transistor." Thesis, 2019. http://ndltd.ncl.edu.tw/cgi-bin/gs32/gsweb.cgi/login?o=dnclcdr&s=id=%22107NCHU5198012%22.&searchmode=basic.

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碩士<br>國立中興大學<br>物理學系所<br>107<br>Recently, traditional Si-MOS device approach to its physical limit as scaling down to atomic level. The large swing off current consumes large energy. To find a way of taking over this challenge, scientists start looking for new material to make new device. Transition metal dichalcogenides(TMDs) are the most hopeful candidates, especially the vertical heterostructure device. They are expected to use in different applications. Because of the heterostructure, we cannot explain the behavior of device easily. We use mechanical exfoliate and electron beam lithography create our SnSe2/MoTe2 heterostructure device. And the hBN provide ultra-flat place for SnSe2/MoTe2. That will reduce some cavity between heterostructure and silicon oxide. Then the trap effect will be reduced greatly. After we apply Scan Photocurrent Microscopy, we found that there are barriers at the edge between overlap and mono MoTe2. That barrier should be considered together, as we analysis the behavior of the devices. After that we think SnSe2/MoTe2 should be type III alignment. And the tunneling current should always exist to consist the current which we measure. According to our I-V data, the on/off ratio is approaching to 106. The equivalent subthreshold swing is 31.5meV/Dec., as the silicon oxide thickness scale down to 10nm at normal temperature. we can estimate the equivalent Schottky barrier height is about 70mV at 0.01V channel voltage from the temperature-dependent data.
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Rezanezhad, Gatabi Iman. "Tunnel MOS Heterostructure Field Effect Transistor for RF Switching Applications." Thesis, 2013. http://hdl.handle.net/1969.1/151047.

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GaN RF switches are widely used in today’s communication systems. With digital communications getting more and more popular nowadays, the need for improving the performance of involved RF switches is inevitable. Designing low ON-state resistance GaN switches are exceedingly important to improve the switch insertion loss, isolation and power loss. Moreover, considerations need to be taken into account to improve the switching speed of the involved GaN HEMTs. In this dissertation, a new GaN HEMT structure called “Tunnel MOS Heterostructure FET (TMOSHFET)” is introduced which has lower ON-state resistance and faster switching speed compared to conventional AlGaN/GaN HEMTs. In the switch ON process, the channel of this device is charged up by electron tunneling from a layer underneath the channel as opposed to typical AlGaN/GaN HEMTs in which electron injection from the source is charging up the channel. The tunneling nature of this process together with the shorter travel distance of electrons in TMOSHFET provide for a faster switching speed. In order to understand the tunneling mechanisms in TMOSHFET, the fabrication of AlGaN/GaN Schottky Barrier Diodes (SBDs) with various AlGaN thicknesses is demonstrated on Si (111) substrate. The impacts of SF6 dry etching on the trap density and trap state energy of AlGaN surface are investigated using the GP/w- w method. Various tunneling mechanisms at different biases are then characterized in samples and compared with each other. To improve the source and drain resistances in TMOSHFET, a model is generated to optimize the 2DEG density and electric field in AlGaN/GaN heterostructure based on Al mole fraction, AlGaN thickness and the thickness of SiN passivation layer and it is experimentally verified by non-contact Hall 2DEG density measurements. The spontaneous and piezoelectric polarizations together with strain relaxation have been implemented into the model, taking into account the annealing effects. From the experimental data on obtained parameters, the operation and device parameterization of the TMOSHFET is outlined and design considerations to improve the device R_(ON)-V_(BR) figure of merit are discussed.
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Chen, Yu-Hsiang, and 陳郁翔. "Fin-Shape Tunnel Field-Effect Transistor Performance and Reliability Study." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/55853140138680156399.

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碩士<br>國立清華大學<br>工程與系統科學系<br>102<br>The market demand for portable electric equipment increase dramatically year by year. Although transistors develop toward low cost and high density, maintaining device characteristics becomes difficult due to the device fabrication and physics limitations of the device. Designing a device that different from conventional MOSFET is a necessary way. This thesis based on P-I-N structure tunnel field effect transistor which operated by quantum tunneling mechanism. Thus, compared with conventional MOSFET operated by drift mechanism, the Tunneling Transistor can achieve fast on/off characteristic and the OFF current can be decrease. This work is the first time to demonstrate the asymmetric gate tunnel FET. The device is based on SOI wafer. We design the gate structure above nanowire and planar to form asymmetric gate structure. The asymmetric gate structure has different control ability to channel. There is tri-gate structure on source and channel intrinsic junction and the control ability is good. It makes the screening length shorter and leads ION increase. There is planar structure on drain and channel intrinsic junction and the control ability is bad. It makes the screening length longer and leads IOFF smaller than tri-gate tunnel FET. The asymmetric gate tunnel FET has the SSmin 152mV/dec and SSavg 233mV/dec. ION gets to 7×10-7A and IOFF gets to 1×10-15A. The ON/OFF ration is 7×108. Compare to tri-gate tunnel FET and planar tunnel FET, the AG-TFET has the better electric characteristic. We also study in the reliability of AG-TFET. In positive bias stress and hot carrier stress analysis, the degradation behaviors after stress are investigated. The AG-TFET presents better reliability than tri-gate TFET after stress. The lesser degradation is due to the peaks of vertical electric field of AG-TFET is lower than tri-gate structure device. This work shows experimental data for device’s reliability; all the data can display asymmetric gate tunnel field effect transistor has applied to high value actually; it would become the next-generation device.
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Ramesha, A. "Sub-Threshold Slope Modeling & Gate Alignment Issues In Tunnel Field Effect Transistor." Thesis, 2008. http://hdl.handle.net/2005/792.

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The Tunnel Field Effect Transistor (TFET) with sub-60mV/decade Sub-threshold slope and extremely high ION/IOFF ratio has attracted enough attention for low standby power (LSTP) applications where the battery life is very important. So far research in this area has been limited to numerical simulation and experimental analysis. It is however extremely necessary to develop compact models for TFET in order to use them in nano-scale integrated circuit design and simulation. In this work, for the first time, we develop analytical Sub-threshold slope model for n-channel double gate TFET (nDGTFET). Unlike conventional FETs, current in TFET is mainly controlled by the band-to-band tunneling mechanism at source/channel interface. As the total drain current is proportional to band-to-band generation rate, the main challenge in the present work is to find an explicit relationship between average electric field over the tunneling path and the applied gate voltage under nonlocal tunneling condition. Two dimensional Poisson’s equation (with Laplace approximation)is first solved in a rectangular coordinate system in order to obtain analytical expression for electron energy distribution over the channel region.Kane’s Model[J. Phy. Chem.Solids 12(181)1959]for band-to-band tunneling along with some analytical approximation techniques are then used to derive the expression for the Sub-threshold slope under nonlocal tunneling conditions. This Sub-threshold slope model is verified against professional numerical device simulator (MEDICI) for different device geometries. Being an asymmetric device, TFET fabrication suffers from source misalignment with gate. As the doping in source and drain-gate are different, conventional-FET-like self-aligned gate stack formation is not possible for TFET. Such misalignment, at source side, seriously degrades the performance of TFETs. To overcome this problem, in this work we explore the possibility of using “gate replacement” technique for TFET fabrication. We first develop process flow for single gate bulk nTFET, and then we extend it to n-channel double gate TFET (nDGTFET) using modified FinFET process. Good alignments between source and gate are observed with TCAD-simulations in both the cases.
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Fan, Yi-Ping, and 范依萍. "Improved-Performance Hafnium Disulfide Field-Effect Transistor with Tunnel Contact and its Application." Thesis, 2019. http://ndltd.ncl.edu.tw/cgi-bin/gs32/gsweb.cgi/login?o=dnclcdr&s=id=%22107NCHU5198014%22.&searchmode=basic.

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碩士<br>國立中興大學<br>物理學系所<br>107<br>In this study, the electrical properties of hafnium disulfide (HfS2) n-type crystal are studied. Because HfS2 is easy to hydrolyze, the application of HfS2 material is carried out by means of mechanical exfoliation method, We present an approach to engineer the contact resistance by introducing a thin TiOx tunnel barrier reducing the Schottky barrier and demonstrating a reduction of the contact resistance and an improved HfS2 transistor performance. Back-gate HfS2 FETs are fabricated on Si substrate with 300 nm thick SiO2. The Au electrodes with and without a TiOx tunnel barrier with 11 are defined by covering copper grid shadow mask with typical gaps and followed by thermal evaporation. The measured results, the Ion current density of HfS2 FET without TiOx is 0.003 μA⁄μm, but 0.019 μA⁄μm for HfS2 FET with TiOx. HfS2 FET without TiOx(HfS2 FET with TiOx) on/off ratio are estimated to be 102(105), mobility is 0.022 〖cm〗^2⁄(V∙s)( 0.192 〖cm〗^2⁄(V∙s)), and Subthreshold Swing are 8.5(2.3). Furthermore, to explore the contact issue of HfS2/Au device and HfS2/ TiOx/Au device, the temperature-dependent measurements(range from 80~340 K)has been achieved. Notably, the Schottky barriers as a function of Vbg has decreased suggesting that the Schottky barrier height has been decreased by the TiOx layer. For HfS2 FET without TiOx, the Schottky barriers change from 1.137 to 0.199. on the other hand, we obtained a drastic reduction of Schottky barriers change from 0.789 to 0.046 in the HfS2 FET with TiOx. We know that the higher contact resistance and limited transistor performance of direct Au contacts on HfS2 could be circumvented by introducing a TiOx tunnel barrier. We systematically study the electric and optoelectric properties of few-layered HfS2 phototransistors, we demonstrate the use of TiOx /Au contact with small Schottky barrier are beneficial for achieving high performance of HfS2 phototransistors. In order to provide detailed information for transmission mechanism of electron, measurements of low frequency noise had been performed. Based on the experimental results, the experimental results were correspond with the results of temperature-dependent measurements. Remarkably, we have found that, with the insertion of a thin TiOx oxide barrier between the Au electrode and the HfS2 flake, the Schottky barrier height can be reduced and the electric performance can be improved.
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Hou, Fu-Ju, and 侯福居. "Process Technologies and Characteristics of Diamond-shaped Ge Nanowire Field-effect Transistor and Microwave-annealed Si Tunnel Transistor." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/64382346737244410326.

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博士<br>國立交通大學<br>電子研究所<br>105<br>In this dissertation, we have investigated the process technologies and device characteristics for sub-10nm MOSFET applications. A feasible pathway to scale Ge NWFETs beyond the 10 nm node was proposed by using a novel diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire (NW) FETs with four {111} facets. In-situ ALD O3 treated Ge surface has been demonstrated to improve the interface of Ge FinFETs by removing damages and roughness induced by fin dry etching. Using microwave annealing (MWA) for S/D dopant activation with low thermal budget suppressed the increase of the interface states. The advantages of MWA for dopant activation include low defect density compared to RTA, negligible dopant diffusion, and suppression of non-ideal straggle effect of ion implantation. The tunable diamond-shaped Ge NW was obtained through simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The different etching selectivity of surface orientations for Cl2 and HBr was employed for the three-step isotropic/anisotropic/ isotropic dry etching. The ratio of Cl2 and HBr, mask width, and Ge recess depth were crucial for forming the nearly defect-free suspended Ge channel through effective removal of dislocations near the Si/Ge interface. The fabricated Ge NWs possesses four {111} facets along the <110> direction. This technique could also be applied for forming diamond-shaped Ge0.9Si0.1 and Si NWs. The diamond-shaped Ge and Ge0.9Si0.1 gate-all-around (GAA) NWFETs with four {111} facets were then fabricated. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an Ion/Ioff ratio exceeding 108, the highest ever reported for Ge-based pFETs. The in-situ atomic layer deposition (ALD) ozone treated Ge surface and MWA have been combined to reduce interface damage and to scale EOT of Ge FinFETs. An atomically thin GeO2 interfacial layer of 0.36 nm is achieved. The superior subthreshold characteristics of 67.8 mV/dec. and 72.9 mV/dec. for Ge n- and p-FinFETs, respectively, were simultaneously obtained for the first time because of the surface smoothing effect of ALD ozone treatment, the interface trap density reduction and diffusionless dopant activation induced by MWA. Furthermore, the gate-induced drain leakage (GIDL) current can be effectively suppressed by using the MWA for the S/D dopant activation. MWA activates dopants through solid-phase epitaxial regrowth with low thermal budget. Optimizing the microwave power during MWA is capable of realizing low defect density at the junction, suppressing dopant diffusion, and mitigating the straggle effect of ion implantation. These favorable features of MWA facilitate the formation of extremely abrupt junction profiles in tunnel field-effect transistors (TFETs). In conjunction with the improved gate-to-channel controllability of the multiple-gate (MG) structure, we demonstrate high-performance lateral n-type and p-type Si-TFETs by using a CMOS-compatible process flow with excellent band-to-band tunneling efficiency and device scalability. The 32-nm MG Si-TFET shows promising characteristics, including a high ON-state current of 41.3 μA/μm, a large current ON/OFF ratio of > 5x107, and minimal short-channel effect by using VG =2 V and VD =1 V.
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Books on the topic "Tunnel field-effect-transistor"

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Solymar, L., D. Walsh, and R. R. A. Syms. Principles of semiconductor devices. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198829942.003.0009.

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p–n junctions are examined initially and the potential distribution in the junction region is derived based on Poisson’s equation. Next the operation of the transistor is discussed, both in terms of the physics and of equivalent circuits. Potential distributions in metal–semiconductor junctions are derived and the concept of surface states is introduced. The physics of tunnel junctions is discussed in terms of their band structure. The properties of varactor diodes are described and the possibility of parametric amplification is touched upon. Further devices discussed are field effect transistors, charge-coupled devices, controlled rectifiers, and the Gunn effect. The fabrication of microelectronic circuits is discussed, followed by the more recent but related field of micro-electro-mechanical systems. The discipline of nanoelectronics is introduced including the role of carbon nanotubes. Finally, the effect of the development of semiconductor technology upon society is discussed.
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Book chapters on the topic "Tunnel field-effect-transistor"

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Pandey, Chandan Kumar, Saurabh Chaudhury, Neerja Dharmale, and Young Suh Song. "Tunnel Field-Effect Transistor." In Emerging Low-Power Semiconductor Devices. CRC Press, 2022. http://dx.doi.org/10.1201/9781003240778-3.

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Kumar, Pramod, Neha Paras, and Manisha Bharti. "Designing of Nonvolatile Memories Utilizing Tunnel Field Effect Transistor." In Tunneling Field Effect Transistors. CRC Press, 2023. http://dx.doi.org/10.1201/9781003327035-13.

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Sharma, Nitika, Nidhi Garg, and Gurpreet Kaur. "Advancements and Challenges in Tunnel Field Effect Transistor." In Lecture Notes in Electrical Engineering. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-7091-5_33.

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Usha, C., and P. Vimala. "Evolution of Heterojunction Tunnel Field Effect Transistor and its Advantages." In Tunneling Field Effect Transistors. CRC Press, 2023. http://dx.doi.org/10.1201/9781003327035-6.

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Wangkheirakpam, Vandana Devi, Brinda Bhowmick, and Puspa Devi Pukhrambam. "Dielectric-Modulated Biosensor Based on Vertical Tunnel Field-Effect Transistor." In Next Generation Smart Nano-Bio-Devices. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-7107-5_9.

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Kulkarni, Netravathi, and P. Vimala. "Two-Dimensional Potential-Based Model for Tunnel Field-Effect Transistor (TFET)." In Lecture Notes in Electrical Engineering. Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-3477-5_9.

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Kumar, C. H. Pavan, and K. Sivani. "Modelling of Tunnel Field-Effect Transistor for Ultra-low-power Applications." In Lecture Notes in Networks and Systems. Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8198-9_63.

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Raushan, Mohd Adil, Mohd Mustaqeem, Shameem Ahmad, and Mohd Jawaid Siddiqui. "Impact of Pocket in a Doping-Less Tunnel Field Effect Transistor." In Proceedings of 6th International Conference on Recent Trends in Computing. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4501-0_18.

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Singh, Ajay, Rakhi Narang, Manoj Saxena, and Mridula Gupta. "Analysis of Electrolyte-Insulator-Semiconductor Tunnel Field-Effect Transistor as pH Sensor." In Communications in Computer and Information Science. Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7_25.

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Ganguly, Anuva, Jayabrata Goswami, Nitai Paitya, Anirudhha Ghosal, and J. P. Banerjee. "Analog/RF Performance Analysis of GAA-GNR Tunnel Field-Effect Transistor (TFET)." In Lecture Notes in Electrical Engineering. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-6301-8_13.

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Conference papers on the topic "Tunnel field-effect-transistor"

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Singh, Prabhat, Dip Prakash Samajdar, and Dharmendra Singh Yadav. "Doping and Dopingless Tunnel Field Effect Transistor." In 2021 6th International Conference for Convergence in Technology (I2CT). IEEE, 2021. http://dx.doi.org/10.1109/i2ct51068.2021.9418076.

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Ahmad, Syed Afzal, and Naushad Alam. "Analysis of Pocket Tunnel Field Effect Transistor." In 2020 IEEE Students Conference on Engineering & Systems (SCES). IEEE, 2020. http://dx.doi.org/10.1109/sces50439.2020.9236723.

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Raushan, M. A., Naushad Alam, and M. J. Siddiqui. "Pocket engineered electrostatically doped tunnel field effect transistor." In TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON). IEEE, 2019. http://dx.doi.org/10.1109/tencon.2019.8929619.

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Vandenberghe, William G., Anne S. Verhulst, Guido Groeseneken, Bart Soree, and Wim Magnus. "Analytical model for a tunnel field-effect transistor." In MELECON 2008 - 2008 IEEE Mediterranean Electrotechnical Conference. IEEE, 2008. http://dx.doi.org/10.1109/melcon.2008.4618555.

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Prasad, N., Xuehao Mou, L. F. Register, and S. K. Banerjee. "Multi-barrier inter-layer tunnel field-effect transistor." In 2016 IEEE International Electron Devices Meeting (IEDM). IEEE, 2016. http://dx.doi.org/10.1109/iedm.2016.7838513.

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M., Aswathy, Nitha M. Biju, and Rama Komaragiri. "Simulation Studies of Tunnel Field Effect Transistor (TFET)." In 2012 International Conference on Advances in Computing and Communications (ICACC). IEEE, 2012. http://dx.doi.org/10.1109/icacc.2012.31.

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Singh, Km Sucheta, Satyendra Kumar, and Kaushal Nigam. "Tunnel Field Effect Transistor Based Biosensors: A Review." In 2021 7th International Conference on Signal Processing and Communication (ICSC). IEEE, 2021. http://dx.doi.org/10.1109/icsc53193.2021.9673155.

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Singh, Amandeep, Sanjeet K. Sinha, and Sweta Chander. "Effect of Negative Capacitance on Heterojunction Tunnel Field Effect Transistor." In 2021 5th International Conference on Electronics, Communication and Aerospace Technology (ICECA). IEEE, 2021. http://dx.doi.org/10.1109/iceca52323.2021.9676074.

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Yao, Lei, Renrong Liang, Chunsheng Jiang, Jing Wang, and Jun Xu. "Investigation of the junctionless line tunnel field-effect transistor." In 2014 International Symposium on Next-Generation Electronics (ISNE). IEEE, 2014. http://dx.doi.org/10.1109/isne.2014.6839326.

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Islam, Md Shofiqul, Kawser Ahmed, and Mirza Mohammad Monzure Elahi. "Off current modeling of a tunnel field effect transistor." In 2012 7th International Conference on Electrical & Computer Engineering (ICECE). IEEE, 2012. http://dx.doi.org/10.1109/icece.2012.6471675.

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