Relevant bibliographies by topics / Turbo-product-code decoder

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Turbo-product-code decoder'

Author: Grafiati
Published: 14 March 2023
Last updated: 31 July 2025

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Journal articles on the topic "Turbo-product-code decoder"

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Boudaoud, A., M. El Haroussi, and E. Abdelmounim. "VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1824. http://dx.doi.org/10.11591/ijece.v7i4.pp1824-1832.

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This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital tra
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A., Boudaoud, El Haroussi M., and Abdelmounim E. "VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (2017): 1824–32. https://doi.org/10.11591/ijece.v7i4.pp1824-1832.

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This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding Equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital tra
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3

Zhou, Li, Hengzhu Liu, and Botao Zhang. "Flexible and high-efficiency turbo product code decoder design." IEICE Electronics Express 9, no. 12 (2012): 1044–50. http://dx.doi.org/10.1587/elex.9.1044.

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Dong, Jie, Yong Li, Rui Liu, Taolin Guo, and Francis C. M. Lau. "Efficient Decoder for Turbo Product Codes Based on Quadratic Residue Codes." Electronics 11, no. 21 (2022): 3598. http://dx.doi.org/10.3390/electronics11213598.

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In this letter, we study turbo product codes with quadratic residue codes (called QR-TPCs) as the component codes. We propose an efficient decoder based on Chase-II algorithm with two convergence conditions for the iterative decoding of QR-TPCs. For each row and column, the Chase-II decoder will stop immediately when one of the conditions is met. The simulation results show that the proposed algorithm has a lower computational complexity compared with existing decoding methods. Moreover, a comparison with 5G low-density parity-check codes shows that the proposed turbo product codes have better
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Ghaith, Alaa. "Improvement Of Block Product Turbo Coding By Using A New Concept Of Soft Hamming Decoder." European Scientific Journal, ESJ 12, no. 18 (2016): 167. http://dx.doi.org/10.19044/esj.2016.v12n18p167.

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The block product turbo code (BPTC) is classified as one of block turbo code concatenation forms. The Hamming code can detect two-bit error and correct one-bit error. The BPTC uses two Hamming codes for "column" coding and "row" coding, it has improved the Hamming code correcting only one error. In addition, the BPTC carries out block interleaving coding for disorganizing the transmission sequence before transmission, so as to avoid burst errors when the signal meets multi-path channel in the channel. This paper will discuss the decoding mechanism of the BPTC and analyze the efficiency of usin
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Leroux, Camille, Christophe Jego, Patrick Adde, Deepak Gupta, and Michel Jezequel. "Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture." Journal of Signal Processing Systems 64, no. 1 (2010): 17–29. http://dx.doi.org/10.1007/s11265-010-0478-5.

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BOIKO, J., I. PYATIN, and A. ZAIETS. "MODELS OF NOISELESS CODING SYSTEMS IN TELECOMMUNICATIONS." Herald of Khmelnytskyi National University. Technical sciences 287, no. 4 (2020): 174–83. https://doi.org/10.31891/2307-5732-2020-287-4-174-183.

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The paper presents the results of the synthesis and analysis of a possible scenario for decoding low-density parity-check codes. The principles of decoding low-density parity-check codes based on the turbo approach are considered. The modern communication theory is based on a scientific task, the essence of which is based on the synthesis of a model of information transfer from an information source to a receiver based on its spatial or temporal dislocation. We will design the decoder based on the “turbo” approach on the basis that the modulation and code will be processed in the receiving dev
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He, Yejun, Francis C. M. Lau, and Chi K. Tse. "Study of bifurcation behavior of two-dimensional turbo product code decoders." Chaos, Solitons & Fractals 36, no. 2 (2008): 500–511. http://dx.doi.org/10.1016/j.chaos.2006.06.101.

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Luo, Jianjun, Xiaoyu Xu, Yifan Shen, Boming Huang, and Wenkui Wang. "Efficient turbo product code decoder with Build‐In SRAM‐based transpose memory." Electronics Letters 60, no. 15 (2024). http://dx.doi.org/10.1049/ell2.13296.

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AbstractTurbo product codes (TPCs) have been widely used for bit error correction in high‐speed applications such as data storage. This letter introduces an efficient hard‐input hard‐output iterating TPC decoder module. A transpose memory utilizing static random access memory (SRAM) is integrated into the decoder to achieve a low hardware overhead. The transpose memory, based on an 8T SRAM bit‐cell, supports both horizontal (row‐wise), and vertical (column‐wise) read/write operations. It is prototyped under a 28nm high‐k/metal gate stack process with bit‐cell size of 0.582 µm2. This specialize
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Liang, Xianming, Jin Yan, Kexian Gong, Peng Sun, and Zhaoyan Xie. "A novel turbo product code decoder architecture with a compact candidate code set." Physical Communication, November 2024, 102565. http://dx.doi.org/10.1016/j.phycom.2024.102565.

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Dissertations / Theses on the topic "Turbo-product-code decoder"

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XIAO, GUOPING. "VLSI architectures design for encoders of High Efficiency Video Coding (HEVC) standard." Doctoral thesis, Politecnico di Torino, 2016. http://hdl.handle.net/11583/2644058.

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The growing popularity of high resolution video and the continuously increasing demands for high quality video on mobile devices are producing stronger needs for more efficient video encoder. Concerning these desires, HEVC, a newest video coding standard, has been developed by a joint team formed by ISO/IEO MPEG and ITU/T VCEG. Its design goal is to achieve a 50% compression gain over its predecessor H.264 with an equal or even higher perceptual video quality. Motion Estimation (ME) being as one of the most critical module in video coding contributes almost 50%-70% of computational complexity
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Bade, Peter. "A 1Mbps 0.18μm CMOS Soft-output Decoder for Product Turbo Codes". Thesis, 2009. http://hdl.handle.net/1807/17493.

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A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW. By making a slight modification, this
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Book chapters on the topic "Turbo-product-code decoder"

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Nair, Gana C., B. Yamuna, Karthi Balasubramanian, and Deepak Mishra. "Hardware Design of a Turbo Product Code Decoder." In Lecture Notes in Electrical Engineering. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4866-0_31.

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Shivanna, Gautham, B. Yamuna, Karthi Balasubramanian, and Deepak Mishra. "Design of High-Speed Turbo Product Code Decoder." In Lecture Notes in Electrical Engineering. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6977-1_15.

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Khavya, S., Karthi Balasubramanian, B. Yamuna, and Deepak Mishra. "Design and Analysis of a Secure Coded Communication System Using Chaotic Encryption and Turbo Product Code Decoder." In Lecture Notes in Electrical Engineering. Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6977-1_48.

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Conference papers on the topic "Turbo-product-code decoder"

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Zhou, Tong, Zhen Wang, Jiacheng Zhang, and Jun Zou. "Implementation of Turbo Product Code Decoder with High Throughput." In 2024 7th International Conference on Information Communication and Signal Processing (ICICSP). IEEE, 2024. https://doi.org/10.1109/icicsp62589.2024.10809309.

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Wu, Xiaoxiao, Yejun He, and Guangxi Zhu. "Performance of Improved Three-Dimensional Turbo Product Code Decoder." In 2007 IEEE International Conference on Integration Technology. IEEE, 2007. http://dx.doi.org/10.1109/icitechnology.2007.4290380.

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Kuang, Wen, Renzhong Zhao, and Zhu Juan. "FPGA implementation of a modified turbo product code decoder." In 2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN). IEEE, 2017. http://dx.doi.org/10.1109/iccsn.2017.8230081.

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Leroux, Camille, Christophe Jego, Patrick Adde, Michel Jezequel, and Deepak Gupta. "A highly parallel Turbo Product Code decoder without interleaving resource." In 2008 IEEE Workshop on Signal Processing Systems (SiPS). IEEE, 2008. http://dx.doi.org/10.1109/sips.2008.4671728.

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Wang, Yaqi, Jun Lin, and Zhongfeng Wang. "A 100 Gbps Turbo Product Code Decoder for Optical Communications." In 2019 IEEE 5th International Conference on Computer and Communications (ICCC). IEEE, 2019. http://dx.doi.org/10.1109/iccc47050.2019.9064204.

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Han, Kaining, Guodong Shen, and Jianhao Hu. "A Novel Stochastic Decoder for Extended BCH Code Based Turbo Product Codes." In ICC 2023 - IEEE International Conference on Communications. IEEE, 2023. http://dx.doi.org/10.1109/icc45041.2023.10278972.

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Yamazaki, Etsushi, and Shinya Sugiura. "Optimization of iterative Chase soft decoder based on cross entropy minimization." In Optical Fiber Communication Conference. Optica Publishing Group, 2024. http://dx.doi.org/10.1364/ofc.2024.w4c.7.

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We propose a scheme to optimize the parameters of iterative Chase decoder. Minimizing the cross entropy loss of the final stage Chase decoder output in the form of log-likelihood ratio improves turbo product code performance.
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Kishore, J. Hari, B. Yamuna, and Karthi Balasubramanian. "Design of a Fast Chase Algorithm based High Speed Turbo Product Code Decoder." In 2021 10th International Conference on Advances in Computing and Communications (ICACC). IEEE, 2021. http://dx.doi.org/10.1109/icacc-202152719.2021.9708201.

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Nageen, Nitin, Subhashini, and Vikas Bhatia. "An Efficient FPGA implementation of Turbo Product Code decoder with single and double error correction." In 2020 National Conference on Communications (NCC). IEEE, 2020. http://dx.doi.org/10.1109/ncc48643.2020.9055995.

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