Academic literature on the topic 'Two-bit flash A'
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Journal articles on the topic "Two-bit flash A"
Lin, Yu-Hsien, Chao-Hsin Chien, Tsung-Yuan Yang, and Tan-Fu Lei. "Two-Bit Lanthanum Oxide Trapping Layer Nonvolatile Flash Memory." Journal of The Electrochemical Society 154, no. 7 (2007): H619. http://dx.doi.org/10.1149/1.2737345.
Full textKerth, D. A., N. S. Sooch, and E. J. Swanson. "A 12-bit, 1-MHz, two-step flash ADC." IEEE Journal of Solid-State Circuits 24, no. 2 (April 1989): 250–55. http://dx.doi.org/10.1109/4.18583.
Full textAn, Ho-Myoung, Tae-Hyeon Han, and Kwang-Yell Seo. "New Erase Characteristics for a Two-Bit SONOS Flash Memory." Journal of the Korean Physical Society 43, no. 5 (November 15, 2003): 868–72. http://dx.doi.org/10.3938/jkps.43.868.
Full textYu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Chun-Yen Chang, and Tan-Fu Lei. "Novel two-bit HfO/sub 2/ nanocrystal nonvolatile flash memory." IEEE Transactions on Electron Devices 53, no. 4 (April 2006): 782–89. http://dx.doi.org/10.1109/ted.2006.871190.
Full textLee, Jong-Ho. "Two-Bit/Cell NFGM Devices for High-Density NOR Flash Memory." JSTS:Journal of Semiconductor Technology and Science 8, no. 1 (March 30, 2008): 11–20. http://dx.doi.org/10.5573/jsts.2008.8.1.011.
Full textDoernberg, J., P. R. Gray, and D. A. Hodges. "A 10-bit 5-Msample/s CMOS two-step flash ADC." IEEE Journal of Solid-State Circuits 24, no. 2 (April 1989): 241–49. http://dx.doi.org/10.1109/4.18582.
Full textLorenzini, M., M. V. Rudan, and G. Baccarani. "A dual gate flash EEPROM cell with two-bit storage capacity." IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A 20, no. 2 (June 1997): 182–89. http://dx.doi.org/10.1109/95.588572.
Full textBhatia, Veepsa, and Neeta Pandey. "Modified Tang and Pun’s Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs." Journal of Electrical and Computer Engineering 2017 (2017): 1–12. http://dx.doi.org/10.1155/2017/8245181.
Full textSai Lakshmi, Taninki, Avireni Srinivasulu, and Pittala Chandra Shaker. "Implementation of Power Efficient Flash Analogue-to-Digital Converter." Active and Passive Electronic Components 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/723053.
Full textChien, Hua-Ching, Chin-Hsing Kao, Jui-Wen Chang, and Tzung-Kuen Tsai. "Two-bit SONOS type Flash using a band engineering in the nitride layer." Microelectronic Engineering 80 (June 2005): 256–59. http://dx.doi.org/10.1016/j.mee.2005.04.077.
Full textDissertations / Theses on the topic "Two-bit flash A"
Bojan, Vujičić. "Detekcija nule A/D konvertorom niske rezolucije." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2017. https://www.cris.uns.ac.rs/record.jsf?recordId=104132&source=NDLTD&language=en.
Full textThe main goal of this thesis was null-detection using a two-bit stochasticdigital measurement method (SDMM). Two methods of null-detection, usingtwo-bit SDMM, were formulated. Using the first method around 100 dB ofdynamic reserve was achieved and using the second one no less than160 dB. Both methods were theoretically, using simulation and experimentallyconfirmed. In addition to the solution of the main problem, several otherrelated problems were also solved. The hypothesis of this thesis – “two-bitSDMM in range from 0 % - 10 % FS is better than the standard samplingmethod (SSM)” has been fully confirmed in all considered cases.
Huang, Yi-Ren, and 黃奕仁. "Low-Frequency Noise in Two-Bit Poly-Si TANOS Flash Memory." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/xuaqw8.
Full text國立臺北科技大學
電腦與通訊研究所
102
In recent years, Poly-Si flash memory is extensively utilized in various portable electronic products. Poly-Si flash memory can be applied to system-on-panel (SOP) and 3D circuit applications because of its characteristics of low cost and low power consumption. In this thesis, the NVM utilizes a two-bit TaN-SiO2-Si3N4-SiO2-Si (TANOS)-type thin-film transistor (TFT), which has shown NVM characteristics and ultrahigh storage density. In poly-Si TANOS flash memory devices with a long channel, 2-bit operation is difficult to achieved by channel hot electron injection (CHEI) programing and band-to-band tunneling-induced hot-hole injection (BTBT-HHI) erasing owing to the grain boundaries. Accordingly, modulated Fowler-Nordheim (MFN) tunneling, which requires no charge acceleration, was performed in poly-Si TANOS flash memory for spatial programming and erasing. In this thesis, we would like to study the LFN in dual-gate (DG) TANOS with multiple nanowire (multi-NW) channel structure under modulate Fowler–Nordheim tunneling program/erase (P/E) operation. In addition, grain boundary trap density (QT) were examined to assist in the analysis of LFN for poly-Si TANOS NVM. In conclusion, through this thesis, we would like to provide DG TANOS-TFT design with strong reference to optimize memory by reducing the impact of LFN, and thus achieve the idealization of SOP.
Kuo, Jian-Hung, and 郭建鴻. "Investigation of the Mechanism and Reliability in a Two-Bit SONOS Flash Memory." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/00711881673803377573.
Full text國立交通大學
電子工程系所
96
For the design of advanced flash memories with better data retention characteristics, SONOS (Silicon Oxide Nitride Oxide Silicon) will become the main stream of nonvolatile memory products because of its simplicity in structure and scalable by comparing with conventional floating gate cells. The flash memory today, due to the vigorous development of the portable information system, the requirements for low voltage operation, low power consumption, and high speed are becoming increasingly important. By using the conventional programming scheme of channel hot electron injection, the interaction of the generated electron and hole pairs could cause the reliability issue for the tunnel oxide. This thesis will be focused on a novel programming method for SONOS applications, in which its physical mechanism and reliability issues will be demonstrated. For the scaling of SONOS memory, two-bit-per-cell operation has been one of the merits for SONOS devices. The unique feature of two-bit-per-cell storage is owing to the localized charge injection and the non-conducting property of charge storage material. First, we developed a low voltage operation scheme, FBEI (Forward Bias induced Electron Injection). Comparing to those reported schemes, this FBEI scheme has features of low voltage and sufficient large operation window. We found that the FBEI and CHEI have a similar characteristic to store charge locally verified from our experiment. Moreover, the stored charge for FBEI is closer to the drain than CHEI from the profiling of the stored charge density distribution. In addition, a better data retention property also made FBEI to become a new candidate for 2-bit operation. The characteristics of endurance and data retention test have also been compared.
周承翰. "The Investigation of a Novel Operating Method for Two-Bit Split Gate SONOS Flash Memory." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/00467886790886377785.
Full text國立交通大學
電子研究所
99
In this thesis, a novel operating scheme has been proposed for 2-bit/cell split gate SONOS. For a certain design of split gate structure, source-side injection (SSI) is usually used for programming and band-to-band hot hole injection (BTBHHI) is used for erase. By using the conventional operating method of charge injection, the interaction between the generated electron and hole pairs could cause the reliability issue for bottom oxide. Stress induced leakage current (SILC) at the bottom oxide has been discussed as a major reliability issue in flash memory. Among different erase method, hot hole injection induced oxide degradation has been found to be most serious condition. In thesis, we propose the new operating scheme to suppress the oxide damage during erase. First, the new timing diagram for novel operating scheme used the multi-cycle pulse series to enhance the efficient of Program/Erase. For the programming method, Forward bias assisted Electron Injection (FBEI), achieved by forward-bias assisted electron injection, the new erase method, Forward Bias assisted Hot Hole Injection (FBHHI), achieved by suitable forward-bias assisted hole generation were proposed. A lower voltage operation and high speed operation can then be implemented in FBEI program. For the erase, FBHHI can supply more holes and less time than BTBHHI in the same operation condition. The results showed that the new operation schemes are more reliable than conventional operation. Finally, we used the specific split gate structure to analyze the charge profiling of various program methods and second bit effect (SBE). And then, a 2 bit/cell operation for split gate SONOS by using multi-cycle pulse series, in which better performance and reliability can be achieved in comparison to conventional operation scheme, e.g. SSI or BTBHHI etc.
Kuan-Wei, Wu. "Study on the 2nd Bit Effect of Scaled Two Bits Per Cell Storage SONOS Type Flash Memory." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0005-2607200616231300.
Full textHuang, Hung-Yu, and 黃宏裕. "A 5-bit 1-GSample/s Two-Stage A/D Converter with a New Flash Folded Architecture." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/36816546608398772512.
Full text國立成功大學
電機工程學系碩博士班
95
For multi-band OFDM UWB applications, we propose a new architecture, which combines the characteristics of flash and folding structures, for low-power high-speed analog-to-digital conversion. The analog front-end of the proposed design is the same as that of a typical flash A/D converter. By replacing folding amplifier with current-mode multiplexer (MUX), cyclic thermometer output codes, the digital output codes of a conventional folding A/D converter, can be obtained. By manipulating this arrangement, the frequency multiplication problem of a traditional folding amplifier is alleviated. Using the proposed architecture, the number of the comparators is reduced to 16, and it is 32 for a typical flash A/D converter. A 5-bit 1-Gsample/s A/D converter is designed in TSMC 0.18-�慆 1P6M CMOS process. Operating at 1-GSample/s, the ENOB is 4.25 bits at input frequency 500 MHz. The maximum DNL is no more than 0.175 LSB and the maximum INL is less than 0.261 LSB. This A/D converter consumes 69 mW from a 1.8 V supply voltage, achieving an FOM of 2.23 pJ/ conversion-step at 1-GSample/s.
Chen, Jiang-Hung, and 陳江宏. "Characterization and Two-Bit Operation Study of Flash Memory with Al2O3 Blocking Layer and TaN Metal Gate." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/81933356324882937762.
Full text國立清華大學
工程與系統科學系
98
Compared with the amorphous-Si thin film transistors (TFTs), low-temperature poly-Si (LTPS) TFTs have higher mobility that help shrinking the transistor dimension, enhance the circuit operation speed, increase the transistor density on circuit, and add function of design capability of the circuit. The Pi-gate nanowires (NWs) with TaN metal gate and Al2O3 blocking layer were introduced to the poly-Si TFT nonvolatile memory. These devices have drawn much attention because of their wide applications on active matrix crystal displays (AMLCDs), and organic light emitting diodes (OLEDs). Furthermore, the LTPS TFTs will help to carry out three-dimensional integrated circuits (3D-ICs) for system-on–chip (SOC) and fully functional system-on-panel (SOP) applications. In this thesis, introducing NWs channel in NVM increase gate controllability and program/erase speed (P/E) speed. The P/E speed and data retention can be improved by introducing Al2O3 high-κ blocking oxide. The erase efficiency of the TaN gate device is higher than the Poly-Si device due to the work function of the TaN is higher than the Poly-Si. The unwanted backward FN tunneling current of electron through the blocking oxide is significantly suppressed. Because of the discrete traps of Si3N4, two-bit operation could be achieved. We discuss two kinds of two-bit operations. In addition, we discuss the dual gate poly-Si TFT NVM with Al2O3 blocking layer and TaN metal gate. Dual gate devices exhibit low leakage current in the off state and high program and erase speed due to the more edge-induced fringe electric field at each corner. A novel two-bit per cell operation is performed by modulated Fowler-Nordheim (MFN) programming and band-to-band tunneling-induced hot-hole injection (BTBT HH) erasing. The dual gate TANOS memory shows larger memory window and clear distinguish ability than single gate memory under two-bit operation
Wu, Kuan-Wei, and 吳冠緯. "Study on the 2nd Bit Effect of Scaled Two Bits Per Cell Storage SONOS Type Flash Memory." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/48001771590507069061.
Full text國立中興大學
電機工程學系所
94
This thesis focus on the discussions about 2nd bit effect of two bits per cell storage SONOS type flash memory. In our experimental designs, the primary topics for discussion are the channel length effect and BD (source/drain) implantation dosage effect. In this study, the two bits per cell storage SONOS cell is made of an n-channel MOSFET with an oxide-nitride-oxide gate structure. Unlike conventional SONOS cell, this cell has a relatively thicker bottom oxide to avoid charge direct tunneling and is operated with channel hot electron to program and band-to-band hot hole to erase, respectively. Thus, after the program operation, we use the charge profiling methodology to extract the electron distribution trapped in the nitride and take advantage of TCAD tools to simulate process conditions and analyze the electrical characteristics. Using these simulated results, we try to understand how the channel length and source/drain implantation dosage affect 2nd bit effect as shown in our experimental data. The degrading factors of 2nd bit effect are the short channel effect and different junction shapes inducing different potential distribution, respectively.
Conference papers on the topic "Two-bit flash A"
Celebi, A., O. Aytar, and A. Tangel. "A 10-Bit 500Ms/s Two-Step Flash ADC." In EUROCON 2005 - The International Conference on "Computer as a Tool". IEEE, 2005. http://dx.doi.org/10.1109/eurcon.2005.1630090.
Full textCremonesi, A., F. Maloberti, G. Torelli, and C. Vacchi. "An 8-bit two-step flash A/D converter for video applications." In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56700.
Full textTo, Hoang-Yen, Dat Nguyen, Clyde Dunn, and Detric Davis. "Latent Flash Single Bit and Multiple Bits Systematic Approach to Failure Analysis." In ISTFA 2008. ASM International, 2008. http://dx.doi.org/10.31399/asm.cp.istfa2008p0344.
Full textAdimulam, Mahesh Kumar, Amit Kapoor, Sreehari Veeramachaneni, and M. B. Srinivas. "An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications." In 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID). IEEE, 2018. http://dx.doi.org/10.1109/vlsid.2018.31.
Full textDixit, Swati, and Manisha Pattanaik. "Programming Characteristics of Two-Bit Sonos Type Flash Memory Using High-K Dielectric Material." In 2015 Fifth International Conference on Communication Systems and Network Technologies (CSNT). IEEE, 2015. http://dx.doi.org/10.1109/csnt.2015.285.
Full textSrinivasan, R., and R. Ambika. "TCAD simulation study of two bit storage flash memory using conventional FinFET and junctionless FET." In 2012 IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT). IEEE, 2012. http://dx.doi.org/10.1109/icaccct.2012.6322909.
Full textAdimulam, Mahesh Kumar, Krishna Kumar Movva, and M. B. Srinivas. "A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications." In 2017 30th IEEE International System-on-Chip Conference (SOCC). IEEE, 2017. http://dx.doi.org/10.1109/socc.2017.8226004.
Full textHung-Yu Huang, Ying-Zu Lin, and Soon-Jyh Chang. "A 5-bit 1 Gsample/s two-stage ADC with a new flash folded architecture." In TENCON 2007 - 2007 IEEE Region 10 Conference. IEEE, 2007. http://dx.doi.org/10.1109/tencon.2007.4428897.
Full textHayashi, Hirokazu, Valery Axelrad, Marie Mochizuki, Takahisa Hayashi, Tetsuhiro Maruyama, Kazuya Suzuki, and Yoshiki Nagatomo. "Optimization of program and erase characteristics of two bit flash memory P-channel cell structure using TCAD." In 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2014. http://dx.doi.org/10.1109/sispad.2014.6931590.
Full textTryzna, M. "An 8-bit 3MS/s CMOS two-step flash converter for low voltage mixed signal CMOS integration." In Second International Conference on `Advanced A-D and D-A Conversion Techniques and their Applications'. IEE, 1994. http://dx.doi.org/10.1049/cp:19940546.
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