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1

Kim, J., H. D. Choi, J. H. Lee, and D. S. Lee. "An anti-wind-up controller design for rocket control systems with control input saturation." Proceedings of the Institution of Mechanical Engineers, Part G: Journal of Aerospace Engineering 212, no. 4 (1998): 261–69. http://dx.doi.org/10.1243/0954410981532423.

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An anti-wind-up controller for the attitude control of a two-stage sounding rocket has been designed. Once the actuator comes up to saturation limits, a feedback signal is generated in this controller from the difference between the compensator output and the actuator control input, and is used to make the actuator work in linear ranges. When this type of controller was applied to the two-stage sounding rocket attitude control system, a remarkable improvement was made in the control performance as compared with the PID (proportional, integral, plus derivative) controller case. Since the performance of this anti-wind-up controller was sensitive to the variation of control gains, a modified anti-wind-up controller has been also proposed to compensate for this.
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2

Shilyaev, Sergey, Evgeniy Slashchev, Igor Voyachek, and Rinat Shaikhov. "Rational reduction of work in progress when assembling parts of a product using the group interchangeability method." MATEC Web of Conferences 329 (2020): 03016. http://dx.doi.org/10.1051/matecconf/202032903016.

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The article discusses the method for interchangeability method. To reduce the volume of work in progress, the design of a fixed combined compensator is developed, which provides stepwise regulation. The article reducing the work in progress by stepwise regulation in multilink dimension chains when assembled using the group proposes a rational technology for the use of combined compensator, taking into account the peculiarities of the group interchangeability method. In order to reduce the work in progress during assembly using the group interchangeability method, two ways of using the combined compensator have been developed: 1 - the inclusion of a compensator in each dimensional chain collected by the group interchangeability method; 2-application of the compensator only at the stage of formation of work in progress during group assembly by replacing one of the parts with it. The peculiarity of the methods is the use of the informational advantage of group assembly — information about the actual dimensions necessary for sorting parts into groups. This eliminates the step of measuring the closing link during assembly and simplifies the design of the compensator, reducing the number of control steps.
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3

Ahmad, Irfan. "Two Degree-of-Freedom Robust Digital Controller Design With Bouc-Wen Hysteresis Compensator for Piezoelectric Positioning Stage." IEEE Access 6 (2018): 17275–83. http://dx.doi.org/10.1109/access.2018.2815924.

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4

Kamenev, Y. B., M. V. Lushina, V. A. Yakovlev, and V. N. Leonov. "New lead-acid battery for submersible vehicles." Electrochemical Energetics 9, no. 3 (2009): 166–70. http://dx.doi.org/10.18500/1608-4039-2009-9-3-166-170.

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In this paper a new design of a container is detailed for sealed lead-acid battery operating overboard of a submersible vehicle in conditions of increased ambient pressure. Such a container is both a battery jar and a pressure compensator. It has been shown that a mandatory requirement for such container use is an application of a gelled-electrolyte. Authors have offered a two-stage technology of filling of accumulators without using vacuum pumping.
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5

Ahmed, Nigar, and Nashmi Alrasheedi. "Commanded Filter-Based Robust Model Reference Adaptive Control for Quadrotor UAV with State Estimation Subject to Disturbances." Drones 9, no. 3 (2025): 181. https://doi.org/10.3390/drones9030181.

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Unmanned aerial vehicles must achieve precise flight maneuvers despite disturbances, parametric uncertainties, modeling inaccuracies, and limitations in onboard sensor information. This paper presents a robust adaptive control for trajectory tracking under nonlinear disturbances. Firstly, parametric and modeling uncertainties are addressed using model reference adaptive control principles to ensure that the dynamics of the aerial vehicle closely follow a reference model. To address the effects of disturbances, a modified nonlinear disturbance observer is designed based on estimated state variables. This observer effectively attenuates constant, nonlinear disturbances with variable frequency and magnitude, and noises. In the next step, a two-stage sliding mode control strategy is introduced, incorporating adaptive laws and a commanded-filter to compute numerical derivatives of the state variables required for control design. An error compensator is integrated into the framework to reduce numerical and computational delays. To address sensor inaccuracies and potential failures, a high-gain observer-based state estimation technique is employed, utilizing the separation principle to incorporate estimated state variables into the control design. Finally, Lyapunov-based stability analysis demonstrates that the system is uniformly ultimately bounded. Numerical simulations on a DJI F450 quadrotor validate the approach’s effectiveness in achieving robust trajectory tracking under disturbances.
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6

Piao, Chang Hao, Yu Sheng Li, Hong Tao Qiao, and Cong Teng. "The Study of Digital DC-DC Converter of Electric Vehicles." Applied Mechanics and Materials 224 (November 2012): 466–69. http://dx.doi.org/10.4028/www.scientific.net/amm.224.466.

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This paper presents a two-stage DC-DC converter for electric vehicles that controlled by using a digital MCU with a lag algorithm. Because the fuel vehicle causes many environmental issues, the electric vehicle becomes a new tendency in vehicle fields. The voltage of power battery is very high and can’t charge for lead-acid battery directly, so DC-DC converter is an essential device. In order to absorb the advantage of digital converter and meet the requirement of widely range input voltage, a digital DC-DC converters for electric vehicle is proposed. The BUCK and half bridge topology was analysis in detail and chosen for the DC-DC converter. A digital DC-DC converter system which includes the hardware and software was designed. The sample circuit, driven circuit and how to make the power transformer is described in detail in hardware design. The software mainly consist the voltage regulate program and CAN communication program. A lag compensator was designed for the voltage regulate. A prototype was made and test in the charge of the lead-acid battery. The result shows the correctness of the topology selection and circuit design. It proved that the DC-DC converter can charge the lead-acid battery within working voltage of power battery and meet the specification basically.
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7

AMINZADEH, HAMED, and REZA LOTFI. "ON THE POWER EFFICIENCY OF CASCODE COMPENSATION OVER MILLER COMPENSATION IN TWO-STAGE OPERATIONAL AMPLIFIERS." Journal of Circuits, Systems and Computers 17, no. 01 (2008): 1–13. http://dx.doi.org/10.1142/s0218126608004113.

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Optimization of power consumption is one of the main design challenges in today's low-power high-speed analog integrated circuits. In this paper, two popular techniques to stabilize two-stage operational amplifiers, namely, Miller and cascode compensations are compared from power efficiency point of view. To accomplish this, cascode-compensated topologies are basically analyzed to derive the required equations for the comparison. In the analysis, a new method to take into account the effect of transfer function zeros is proposed. By assuming that the zeros' magnitudes are fairly nondominant, the method increases the accuracy of the analyses. The relationships show that for the same specifications, cascode compensation is more power-efficient than Miller compensation, especially for heavy capacitive loads. This has been confirmed by SPICE simulations.
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8

D, Pruthvi, and Dr Kiran V. "Design of Two stage OTA with Optimised Compensation Capacitance." International Journal of Research and Review 9, no. 11 (2022): 60–65. http://dx.doi.org/10.52403/ijrr.20221109.

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A two-stage operational transconductance amplifier is constructed and compared between 45nm and 180nm CMOS technology in this paper. To find the best design, the suggested operational amplifier is examined across a number of distinct parameters. With a supply voltage of 1.8V, it reaches a maximum gain of about 66 dB and a phase margin of 82°. A Cadence Virtuoso-based circuit simulator has been used to construct the suggested operational amplifier and the comparison is done. Keywords: OTA, Miller coupling capacitance, cadence virtuoso, Gain, output swing, power dissipation.
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9

Zou, Yuheng. "Design and Analysis of Miller Compensated Two-Stage Operational Amplifier." Applied and Computational Engineering 107, no. 1 (2024): 14–23. http://dx.doi.org/10.54254/2755-2721/107/20241072.

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Abstract. With the development of integrated circuit technology, the size of electronic equipment continues to reduce, and speed continues to increase. Operational amplifiers are the key circuit in analog ICs, and the required performance of operational amplifiers is also increasingly high, research and design of high-performance operational amplifiers has become one of the key topics of today's research. A CMOS two-stage operational amplifier with high unity-gain bandwidth is analysed and designed with an appropriate Miller-compensation technique in this research to improve the frequency characteristics and stability. The design is based on 180nm CMOS process. Its performance is simulated and analysed in Cadence software environment. The performance parameters are shown by simulation results that the amplifier has a gain of 61.81dB, a GB (unity-gain bandwidth) of 907.42MHz and a phase margin of 75.02. The experimental results show that it achieves high unity-gain bandwidth while ensuring gain and stability. Through this study, the principles of two-stage operational amplifiers and their compensation as well as the design and simulation are shown in detail in both theoretical and experimental sections.
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10

Hsieh, Chen, K. C. Lin, and Chieh Li Chen. "Contour Controller Design for Two-Dimensional Stage System with Friction." Materials Science Forum 505-507 (January 2006): 1267–72. http://dx.doi.org/10.4028/www.scientific.net/msf.505-507.1267.

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For multiple-axis stages, it is required to operate the axes simultaneously, such that the resulting trajectory of platform follows a given contour. For most stage systems, friction acts as the major disturbance which degrades the precision of system motion and its effect should be compensated. In this paper, contouring control of a two-dimensional stage system subjected to friction is investigated. A systematic contour controller design based on task coordinate frame is proposed and its effectiveness is studied through theoretical analysis and numerical simulations.
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11

Wang, Xueliang, Nan Zheng, Fenglong Wei, Yue Zhou, and Huaijiang Yang. "Stability Compensation Design and Analysis of a Piezoelectric Ceramic Driver with an Emitter Follower Stage." Micromachines 14, no. 5 (2023): 914. http://dx.doi.org/10.3390/mi14050914.

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Piezoelectric ceramic has been widely applied in many fields because of its characteristics, and the performance of piezoelectric ceramic is determined strongly by its driver. In this study, an approach to analyzing the stability of a piezoelectric ceramic driver with an emitter follower stage was presented, and a compensation was proposed. First of all, using the method of modified nodal analysis and loop gain analysis, the transfer function for the feedback network was analytically deduced, and the cause of the instability of the driver was found to be the pole composed of the effective capacitance from the piezoelectric ceramic and the transconductance from the emitter follower. Then, a compensation involving a novel delta topology composed of an isolation resistor and a second feedback path was proposed, and its function principle was discussed. Simulations showed a correspondence between the analysis and the effectiveness of the compensation. Finally, an experiment was set up with two prototypes, one with compensation, and the other without compensation. Measurements showed the elimination of oscillation in the compensated driver.
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12

Zhang, Chao, Wen Wang, Yong Pan, Lina Cheng, Shoupei Zhai, and Xu Gao. "A two-stage method for real-time baseline drift compensation in gas sensors." Measurement Science and Technology 33, no. 4 (2022): 045108. http://dx.doi.org/10.1088/1361-6501/ac491f.

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Abstract Baseline drift caused by slowly changing environment and other instability factors affects significantly the performance of gas sensors, resulting in reduced accuracy of gas classification and quantification of the electronic nose. In this work, a two-stage method is proposed for real-time sensor baseline drift compensation based on estimation theory and piecewise linear approximation. In the first stage, the linear information from the baseline before exposure is extracted for prediction. The second stage continuously predicts changing linear parameters during exposure by combining temperature change information and time series information, and then the baseline drift is compensated by subtracting the predicted baseline from the real sensor response. The proposed method is compared to three efficient algorithms and the experiments are conducted towards two simulated datasets and two surface acoustic wave sensor datasets. The experimental results prove the effectiveness of the proposed algorithm. Moreover, the proposed method can recover the true response signal under different ambient temperatures in real-time, which can guide the future design of low-power and low-cost rapid detection systems.
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13

Jianhai, WEI. "Design of Three-stage Cascaded Two-Stage Millar Compensated OTA for Wearable ECG Sensor Technologies." Journal of Physics: Conference Series 1846, no. 1 (2021): 012088. http://dx.doi.org/10.1088/1742-6596/1846/1/012088.

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14

Xia, Tao, Zhi Chang Yuan, Yong Xing Li, Hai Feng Guo, and Bai Hua Zhang. "Unified Controller Design for Two-Stage Converter Based on Feed-Forward Compensation." Advanced Materials Research 732-733 (August 2013): 1271–79. http://dx.doi.org/10.4028/www.scientific.net/amr.732-733.1271.

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A unified control structure for two-stage power converter system (PCS) is proposed which incorporates both charging and discharging modes within the same controller. Detailed modeling process is presented using sub-system approach. Power feed-forward compensation with direct battery current reference is engaged to enable fast response to power change on battery side, thus reducing DC bus voltage fluctuation during transients. Simulation and experiments show that the proposed control structure can effectively improve dynamic response without compromising steady-state performance.
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15

Xie, Wei. "Study on reactive power compensation for a grid connected photovoltaic power generation system." Journal of Physics: Conference Series 2835, no. 1 (2024): 012021. http://dx.doi.org/10.1088/1742-6596/2835/1/012021.

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Abstract The photovoltaic (PV) industry is developing rapidly, and electricity from decentralized or grid-connected systems is becoming increasingly important. Grid-connected PV systems with active and reactive power compensation can compensate for voltage fluctuation and enhance power system stability. The paper proposes a two-stage, three-phase PV system with reactive power compensation based on the structural properties of conventional PV grid-connected systems. The system achieves maximum power point tracking through real-time detection of PV current and voltage output, load current, and grid voltage and provides active electricity to the grid. It can provide reactive energy required by the grid to compensate for local load reactive current, effectively suppress dynamic voltage fluctuations, improve the electric power quality, and reduce investment outlay. Simulation results are carried out to validate the rationality of the design.
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16

Zaidi, Muhaned. "Low-voltage Low-power Bulk-driven CMOS Op-Amp Using Negative Miller Compensation for ECG." Journal of Engineering and Technological Sciences 54, no. 5 (2022): 220510. http://dx.doi.org/10.5614/j.eng.technol.sci.2022.54.5.10.

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Two bulk-driven CMOS (Complementary Metal Oxide Semiconductor) operational amplifier (op-amp) designs for electrocardiogram (ECG) application are presented and compared in this paper. Both op-amps are based on two-stage amplification, where bulk-driven differential input is the first stage, while additional DC gain is the second stage. Different compensation techniques were integrated in each op-amp design. Standard Miller compensation was used for the first op-amp parallel with the second stage. The novelty of the second op-amp is that it utilizes negative Miller compensation between the bulk-driven input node and the output node of the first stag, while standard Miller compensation was used in the second stage. The purpose of this work was to compare DC gain, phase margin (PM) and unit gain frequency (UGF) obtained through different simulated compensation strategies and test results. The op-amps were simulated using 0.25 μm CMOS technology. The simulation results are presented using the standard model libraries from Tanner EDA tools, operating on a single rail +0.8V power supply.
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17

Lv, Gaochong, and Yushun Guo. "Exact design for the settling time of two-stage Miller compensated operational amplifiers." Analog Integrated Circuits and Signal Processing 110, no. 1 (2021): 151–63. http://dx.doi.org/10.1007/s10470-021-01955-3.

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18

Li, Dan, Meng-tian Rong, and Guo-hua Shu. "Optimization design of two-stage operational amplifier with frequency compensation via geometric programming." Journal of Shanghai Jiaotong University (Science) 16, no. 6 (2011): 648–51. http://dx.doi.org/10.1007/s12204-011-1205-5.

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19

Pugliese, A., F. A. Amoroso, G. Cappuccino, and G. Cocorullo. "Design approach for fast-settling two-stage amplifiers employing current-buffer Miller compensation." Analog Integrated Circuits and Signal Processing 59, no. 2 (2008): 151–59. http://dx.doi.org/10.1007/s10470-008-9215-4.

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20

Supithak, Tanathorn, Nicha Wongyimyong, Kou Yamada, and David Banjerdpongchai. "Convex Optimization Approach to Multi-Objective Design of Two-Stage Compensators for Linear Systems." Engineering Journal 25, no. 8 (2021): 153–62. http://dx.doi.org/10.4186/ej.2021.25.8.153.

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21

Chen, Xiaodong, Kang Tai, Huifeng Tan, and Zhimin Xie. "Design of a two-stage compliant asymmetric piezoelectrically actuated microgripper with parasitic motion compensation." Mechanical Systems and Signal Processing 208 (February 2024): 110950. http://dx.doi.org/10.1016/j.ymssp.2023.110950.

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22

Ren, Ming Yuan, Chun Xiang Zhang, Jing Ying Zhao, and Hai Guo. "Design and Simulation of Transconductance with Capacitances Feedback Compensation Amplifier." Applied Mechanics and Materials 147 (December 2011): 311–14. http://dx.doi.org/10.4028/www.scientific.net/amm.147.311.

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This paper presents a low-power multistage amplifier with a novel Transconductance with Capacitances Feedback Compensation (TCFC) technique. A transconductance stage and two capacitors introduce negative feedback to a three-stage amplifier, which significantly improves the performance such as gain-bandwidth product, slew rate, stability and sensitivity. Implemented in a commercial 0.5-μm CMOS technology and driving 10pF capacitive load, a three-stage TCFC amplifier achieves over 120dB gain, 1.515MHz GBW and 1.3V/μS average slew rate, while only dissipating 380μW under 3.3V supply.
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23

Zhang, Bin, Guoyu Hei, and Huirong Li. "Analysis and Design of Two-Stage Cascaded LED Load Wireless Power Transfer System." Journal of Physics: Conference Series 2290, no. 1 (2022): 012002. http://dx.doi.org/10.1088/1742-6596/2290/1/012002.

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Abstract This paper proposes a two-stage cascaded wireless power transfer (WPT) system aimed at increasing the transfer radius and supplying power to multiple low-power loads. The proposed WPT scheme is regarded as a cascading of two WPT systems. The system realizes constant current power supply for two-stage LED load and put emphasis on solving the problems of limited power supply radius and power supply of multiple constant current/voltage loads in WPT system. Four basic power supply types of transmission network are discussed in this paper, and the compensation network structures and parameters suiting for these types are determined by analyzing every stage’s input and output characteristic using two-port network T matrix. The result of research validates that constant current is achieved in general. Moreover, the two stage’s maximum efficiency is 68.04% when the LED total number changes from 6 to 13, which proves the feasibility of the proposed scheme.
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24

Vasudeva, G., and Mandar Jatkar. "Design of High Performance Operational Transconductance Amplifier." ACS Journal for Science and Engineering 3, no. 2 (2023): 21–30. http://dx.doi.org/10.34293/acsjse.v3i2.81.

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Designing high-performance analog circuits is becoming increasingly challenging with the persistent trend toward reduced supply voltages. The main bottleneck in an analog circuit is the operational amplifier. At large supply voltages, there is a trade off among speed, power, and gain, amongs to ther performance parameters. Often these parameters present contradictory choices for the op-amp architecture. At reduced supply voltages, output swing becomes yet another performance metric to be considered when designing the opamp. Of the several architecture folded cascode OTA is used in which all the transistors are in saturation regime. Furthermore, in an effort to reduce costs and integrate analog and digital circuits onto a single chip, the analog designer must often face the challenges using CMOS processes. This paper covers the design and implementation of a novel CMOS folded cascode OTA designed in 1m technology. Covered topic include current source and sinks, differential amplifier, compensation techniques, two stage compensated OTA and cascode OTA. Our design emphasis is on practical design where power consumption and speed are critical. The OTA has very low settling time and can be used for high speed applications, such Analog-to–Digital converters, high speed Sigma-delta ADC.
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25

Akbari, Meysam, and Omid Hashemipour. "High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation." Journal of Circuits, Systems and Computers 24, no. 04 (2015): 1550057. http://dx.doi.org/10.1142/s0218126615500577.

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By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.
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26

Supithak, Tanathorn, and David Banjerdpongchai. "A convex optimization approach to multi-objective design of two-stage compensators for MIMO linear systems." Journal of Process Control 123 (March 2023): 123–30. http://dx.doi.org/10.1016/j.jprocont.2023.01.016.

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27

Tiwari, Asheesh Kumar. "Two Stage Miller Compensated Op-Amp design in 180 nm CMOS for High Gain Methodology." International Journal of Advanced Trends in Computer Science and Engineering 9, no. 2 (2020): 1903–8. http://dx.doi.org/10.30534/ijatcse/2020/153922020.

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28

Jovanovic Dolecek, G., and M. Laddomada. "Design of two-stage nonrecursive rotated comb decimation filters with droop compensation and multiplierless architecture." Journal of the Franklin Institute 352, no. 3 (2015): 913–29. http://dx.doi.org/10.1016/j.jfranklin.2014.11.016.

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29

Goyal, Shilpa. "Analysis and Design of a Two Stage CMOS OPAMP with 180nm using Miller Compensation Technique." International Journal on Recent and Innovation Trends in Computing and Communication 3, no. 4 (2015): 2255–60. http://dx.doi.org/10.17762/ijritcc2321-8169.1504107.

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., D. S. Shylu. "DESIGN AND ANALYSIS OF A TWO STAGE MILLER COMPENSATED OP-AMP SUITABLE FOR ADC APPLICATIONS." International Journal of Research in Engineering and Technology 03, no. 19 (2014): 249–56. http://dx.doi.org/10.15623/ijret.2014.0319045.

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31

Chaithanya, M., R. K. Srivastava, and S. R. Ijjada. "Design of a Two Stage Operational Amplifier with Zero Compensation for Accurate Bandgap Reference Circuit." Acta Physica Polonica A 135, no. 5 (2019): 977–79. http://dx.doi.org/10.12693/aphyspola.135.977.

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Chen, Zitao. "Design and optimisation of a two-stage amplifier based on a differential input stage and a common-source amplifier." Applied and Computational Engineering 104, no. 1 (2024): 104–9. http://dx.doi.org/10.54254/2755-2721/104/20241052.

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Abstract. Since the emergence of integrated circuits, through the circuit structure, the production process of continuous iterative updating, so that its used in various types of electronic equipment more and more widely. Currently, operational amplifier circuits play an extremely important role in signal processing and communication systems. Amplifiers have different characteristics depending on the needs of different electronic devices. This thesis addresses the optimisation and design of the characteristics of the two-stages amplifier. Firstly, several classical amplifier structures are analysed. Select the appropriate structure and combine it into a two-stages amplifier. Simulation is carried out on cadence software and later the simulation results are analysed before parameter optimisation. On this basis, a two-stages amplifier based on a PMOS differential input stage with a common-source amplifier has been designed. It also improves the amplifier's gain, frequency range, gain bandwidth, and other performance metrics. Using PMOS self-bias circuit to improve power supply stability. Finally, based on the development hotspots of integrated circuits, the possibility of circuit optimization was analyzed. Discussions were conducted on negative feedback circuits, phase compensation methods, and other aspects.
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AMINZADEH, HAMED. "MOSFET-ONLY TWO-STAGE OPERATIONAL AMPLIFIERS WITH MILLER COMPENSATION: DESIGN AND FABRICATION IN NANO-SCALE CMOS." Journal of Circuits, Systems and Computers 22, no. 08 (2013): 1350065. http://dx.doi.org/10.1142/s0218126613500655.

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Nano-scale area-efficient MOS devices are employed in this article to stabilize high-speed operational amplifiers (opamps) for those applications that deal with negative feedback. As an alternative choice, metal-insulator-metal (MIM) capacitors cannot be integrated in every technology as they require additional process masks. Moreover, these components suffer from large silicon area. In this paper, considerations of a successful MOSFET-only amplifier design are highlighted and described. These considerations make it possible to fabricate these amplifiers for a nano-scale digital system-on-chip (SoC). Circuit-level simulations include comparison between MOS capacitors (MOSCAPs) with MIM capacitors (MIMCAPs) in two identical processes. The efficiency of the given design considerations are also validated through simulation in 90-nm CMOS technology. A MOSFET-only amplifier is designed as the main part of a 5 MS/s sample-and-hold. Using the proposed design techniques, the MOSFET-only amplifier with Miller compensation recovers 51% silicon die with respect to a MIMCAP amplifier for identical signal-to-noise-plus-distortion (SNDR) ratio.
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MARANO, DAVIDE, GAETANO PALUMBO, and SALVATORE PENNISI. "IMPROVED POWER-EFFICIENT RNMC TECHNIQUE WITH VOLTAGE BUFFER AND NULLING RESISTORS FOR LOW-POWER HIGH-LOAD THREE-STAGE AMPLIFIERS." Journal of Circuits, Systems and Computers 18, no. 07 (2009): 1321–31. http://dx.doi.org/10.1142/s021812660900568x.

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This work proposes and develops an original compensation approach for low-power three-stage operational transconductance amplifiers driving large capacitive loads. The proposed solution is based on the basic reversed nested Miller compensation and exploits a voltage buffer and two nulling resistors in the compensation network, along with a feedforward stage to improve slewing and settling performance. A well-defined design procedure using the loop gain phase margin as the main design parameter is also developed. SPECTRE simulations on a three-stage amplifier are carried out and are found to be in excellent agreement with the theoretical analysis, showing a significant improvement of the proposed approach over traditional compensation strategies in terms of small-signal and large-signal performance. Monte Carlo simulation results finally prove the proposed technique to be well-guarded against process parameter variations.
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De, Bishnu Prasad, Kanchan Baran Maji, Rajib Kar, Durbadal Mandal, and Sakti Prasad Ghoshal. "Evolutionary Computation Based Sizing Technique of Nulling Resistor Compensation Based CMOS Two-Stage Op-Amp Circuit." International Journal of High Speed Electronics and Systems 26, no. 04 (2017): 1740021. http://dx.doi.org/10.1142/s0129156417400213.

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This article explores the comparative optimizing efficiency between two PSO variants, namely, Craziness based PSO (CRPSO) and PSO with an Aging Leader and Challengers (ALC-PSO) for the design of nulling resistor compensation based CMOS two-stage op-amp circuit. The concept of PSO is simple and it replicates the nature of bird flocking. As compared with Genetic algorithm (GA), PSO deals with less mathematical operators. Premature convergence and stagnation problem are the two major limitations of PSO technique. CRPSO and ALC-PSO techniques individually have eliminated the disadvantages of the PSO technique. In this article, CRPSO and ALC-PSO are individually employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained individually from CRPSO and ALC-PSO techniques are validated in SPICE environment. SPICE based simulation results justify that ALC-PSO is much better technique than CRPSO and other formerly reported methods for the design of the afore mentioned circuit in terms of the MOS area, gain and power dissipation etc.
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Wang, Quan, Huan Wang, and Qiong Xiang. "Design and Calibration of Inductive Current Transformer." Advanced Materials Research 860-863 (December 2013): 2261–65. http://dx.doi.org/10.4028/www.scientific.net/amr.860-863.2261.

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In this paper, the design principle of inductive current transformer is introduced at first. Then an inductive current transformer is produced by applying the structure of two-stage inductive voltage divider. And finally, the error of the sample machine is given through examine test, and the suggestion for improving the machine is given based on the data. The data from the sample machine shows that: without compensation winding, the error level of 1200 ampere-turn of inductive current transformer can reach 0.1 level, after adding the compensation winding, it can reach 0.02 level. The design and data have laid a foundation for the future design of inductive current transformer with higher level of accuracy.
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Liu, Zhangyu, Zhi Li, Long Zheng, and Dandan Li. "Two-Stage Robust Lossless DWI Watermarking Based on Transformer Networks in the Wavelet Domain." Applied Sciences 13, no. 12 (2023): 6886. http://dx.doi.org/10.3390/app13126886.

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For copyright protection of diffusion-weighted imaging (DWI) images, traditional robust watermarking techniques result in irreversible distortions, while reversible watermarking methods exhibit poor robustness. We propose a two-stage lossless watermarking algorithm based on a Transformer network to solve this problem. The first stage of the algorithm is to train the robust watermarking network, embed the watermark into the cover image in the wavelet domain, and design the frequency information enhancement module to improve the reconstruction quality. In the second stage, based on the pre-trained robust watermarking network, the difference image between the watermarked image and the cover image is reversibly embedded into the watermarked image as the compensation information to losslessly recover the cover image. The difference image is compressed using DCT and Huffman coding to reduce the compensation information. Finally, the watermark extraction network is trained on the second embedding result to avoid weakening the robustness of the first stage caused by the reversible embedding. The experimental results demonstrate that the PSNR of the watermarked image reaches 60.18 dB. Under various types of image attacks, the watermark extraction BER is below 0.003, indicating excellent robustness. The cover image can be recovered losslessly under no attack.
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38

Ruiz-Amaya, J., M. Delgado-Restituto, and A. Rodriguez-Vazquez. "Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits." IEEE Transactions on Circuits and Systems I: Regular Papers 56, no. 6 (2009): 1077–87. http://dx.doi.org/10.1109/tcsi.2008.2008509.

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39

Pandiev, Ivaylo. "Design and Implementation of Self-Limiting Two-Stage LC Oscillators Using Cascade Structure of Monolithic CCIIs as Active Elements." Energies 16, no. 17 (2023): 6226. http://dx.doi.org/10.3390/en16176226.

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This paper presents the structure and principle of operation of two circuit configurations of self-limiting LC oscillators using monolithic positive second-generation current conveyors (CCII+s), that are implemented using Current-Feedback Operational Amplifiers (CFOAs) with an available compensation pin (Z). The proposed LC oscillators are synthesized using a systematic approach in the design of analog electronic circuits and can be considered as variants of the basic three-point oscillators, implemented using transistors (BJTs or FETs). Based on the analysis of the structure and electrical parameters of the CFOAs with a compensation pin (Z), electronic circuits of oscillators with two-stage amplifier blocks are synthesized. The characteristic equations and self-oscillation conditions are derived for the obtained analog circuits, and recommendations for designing circuits with arbitrary frequencies are defined. To verify the efficiency of the proposed LC oscillators, an experimental study is performed in the frequency range from 100 kHz to 10 MHz. The CFOAs AD844A with an external terminal z of the internal current conveyor are used as active elements. The obtained experimental results well match the results of the simulation modelling and the parameters based on the derived analytical expressions. The developed LC oscillators are intended to be used in schematic configurations of gas sensors based on surface acoustic wave (SAW) resonators.
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40

Nsengiyumva, Isidore, Elijah Mwangi, and George Kamucha. "Performance Analysis of a Linear Gaussian- and tanh-Apodized FBG and Dispersion Compensating Fiber Design for Chromatic Dispersion Compensation in Long-haul Optical Communication Networks." International Journal of Optics 2022 (September 2, 2022): 1–14. http://dx.doi.org/10.1155/2022/5734420.

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This paper investigates a novel compensation technique of dispersion effect mitigation using a combination of three- and four-stage-apodized fiber Bragg gratings (FBG) and dispersion compensating fiber (DCF) designs. Two designs using three-stage and four-stage FBG and DCF in combination have been proposed and compared for their performance in mitigating chromatic dispersion effects at 100 km SMF. The performance of each design has been evaluated using Q-factor results using linear Gaussian- and tanh-apodized fiber Bragg gratings. Each profile manifested different Q-factor results over a range of 5 dBm, 7.5 dBm, and 10 dBm of CW laser power over FBG grating lengths from 4 mm to 8 mm. The results obtained using the three-stage and four-stage FBG and DCF designs showed that an apodization profile using a tanh function can be used successfully with FBG lengths from 4 mm to 8 mm, regardless of the CW launched power. In contrast, the results using a Gaussian apodization profile for three- and four-stage FBG and DCF designs are applicable to FBG lengths from 5 mm to 8 mm. Designs using three-stage FBG and DCF generated higher Q-factor results than designs using only four-stage FBG and DCF, regardless of the launched power. The highest Q-factor of 18.58 was obtained for three-stage tanh-apodized FBG and DCF used in combination for an FBG length of 6 mm. The highest result obtained for a three-stage Gaussian-apodized FBG and DCF design was a Q factor of 17.13 using an FBG length of 8 mm. The proposed method was also compared to current similar works and can be successfully implemented in long-haul optical communication.
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41

dos Santos, Rafael A. P., and Jacob Scharcanski. "Lossless and near-lossless digital angiography coding using a two-stage motion compensation approach." Computerized Medical Imaging and Graphics 32, no. 5 (2008): 379–87. http://dx.doi.org/10.1016/j.compmedimag.2008.03.001.

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42

Sheng, Jun, Jian Gang Li, and Lei Zhou. "Closed-Loop Identification and Composed Controller Design for Precise Machining." Advanced Materials Research 97-101 (March 2010): 3139–45. http://dx.doi.org/10.4028/www.scientific.net/amr.97-101.3139.

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For a class of three-loop architecture motion control system, two-stage close-loop identification is introduced to estimate the control plant and thus to tune the velocity controller. Based on the estimated model, PID position controller with derivative filter is proposed using pole-zero cancellation and pole assignment. Feed-forward compensators such as Velocity and Acceleration Feed-forward Controller (VAFC), Zero Phase Error Tracking Controller (ZPETC), Zero Magnitude Error Tracking controller (ZMETC) are introduced as well, and their effects are compared.
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43

Wang, Minghao. "The Application of Two Stage Amplifier Based on CMOS in Amplification of Electrocardiogram." Highlights in Science, Engineering and Technology 32 (February 12, 2023): 289–94. http://dx.doi.org/10.54097/hset.v32i.5180.

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With the purpose of detecting heart diseases, electrocardiogram monitor is created, which records the micro electrical activity of the heart muscle. In the paper, a two stage amplifier is design to amplify the signal in a observable level. It is based on CMOS of TSMC 0.18 μm technology with 1.8 V supply voltage. The total gain Direct Current (DC) gain is around 87 dB and -3dB bandwidth is about 3000Hz. After adding a 0.1 pF compensation capacitor, the phase margin obtained is 91.57°. Also, the total current consumption of the amplifier is less than 6 μm, which is 5.21 μm. Please note that the simulation and analysis is operated on Coolspice Software. This two stage amplifier could be an alternative choice applied in the ECG monitor in order to increase the performance of the wave interpretation.
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Finnie, David, Rehan Masood, and Liam Grant. "Subcontractor Engagement in the Two-Stage Early Contractor Involvement Paradigm for Commercial Construction." Knowledge 4, no. 2 (2024): 302–20. http://dx.doi.org/10.3390/knowledge4020017.

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Commercial construction projects (CCPs) in New Zealand contribute more to the economy than other project types. However, many face cost and time increases due to inadequate planning. Procurement pathways that involve contractors during design development provide more time to plan, collaboratively. Nevertheless, most projects are procured through traditional tender where contractors are only involved after detailed design. Through two-stage early contractor involvement (2S-ECI), contractors can provide design buildability advice for complex projects, contribute value management, carry out exploratory works, and order materials. The role of subcontractors in 2S-ECI can be significant. Six semi-structured interviews were conducted with clients, consultants, main contractors, and a subcontractor involved in large complex commercial construction projects. The findings build on the emerging body of knowledge about 2S-ECI by providing insight into subcontractor early involvement. Project complexity and market conditions were the main reasons for early subcontractor involvement. Common challenges include a lack of information sharing among the parties, non-competitive selection, and a lack of standard contract documentation. Opportunities for improvement include clarifying client expectations, educating stakeholders, and providing more equitable compensation for pre-construction services. Key drivers for subcontractor involvement include project complexity, market conditions, ordering long-lead-time systems, and performance specifications. Specialist early sub-trades include electrical, mechanical, structural steel, and façades. Subcontractors should typically be engaged as early as possible, often concurrently via main contractors to share performance risk. Pre-construction services provided by subcontractors include planning and sequencing; design buildability analysis; risk mitigation; value management; budget advice; systems procurement; design solutions; and document control systems. Advantages include obtaining specialist project knowledge and improving completion certainty. Producing a pre-construction services agreement (PCSA) for subcontractors may address challenges, as has been carried out for main contractors, but there is still a gap in the contractual framework for 2S-ECI for subcontractors.
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45

Aminzadeh, Hamed, Mohammad Danaie, and Reza Lotfi. "Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters." Integration 41, no. 2 (2008): 183–92. http://dx.doi.org/10.1016/j.vlsi.2007.05.003.

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46

Xiaojia, Feng, and Zhang Jun-An. "Gain-Based Double Feedforward Compensation for Multi-Stage Amplifiers." Journal of Nanoelectronics and Optoelectronics 16, no. 2 (2021): 196–200. http://dx.doi.org/10.1166/jno.2021.2775.

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A gain-based double feedforward compensation (GBDFC) for multi-stage amplifiers is proposed, which could be used in multi-stage OTA design. The proposed compensation technique provides two left-plane zeros to counteract with the first and second non-dominant poles of the OTA without reducing the dominant pole obviously. Meanwhile, a high slew-rate is presented in the condition of large step input signal. A three-stage Opamp prototype with the proposed technique is realized in a 0.18 yitm CMOS process. The post simulation results show that it provides a unity-gain bandwidth (GBW) of 103 MHz and phase margin (PM) of 70° with power consumption of 0.328 mW and small compensation capacitors, implying a better FOM compare with the state-of-the-art.
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47

Yao, Peiyuan. "A High-Performance CMOS Operational Amplifier Design." Applied and Computational Engineering 147, no. 1 (2025): 197–202. https://doi.org/10.54254/2755-2721/2025.22724.

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This paper presents the design of a high-performance two-stage folded cascode operational amplifier based on the TSMC 180nm CMOS process. The input stage adopts a folded cascode structure, which not only achieves a high DC gain but also enhances the suppression of common-mode noise. The output stage uses a common-source structure to ensure the output swing. To ensure the stability of the operational amplifier, a Miller capacitor is used to compensate the output stage amplifier, ensuring sufficient phase margin. The design and simulation of the circuit were completed using Cadence software. Simulation results under a 1.8V supply voltage and a 2pF load capacitance show that the DC gain of the operational amplifier is no less than 84dB, the common-mode rejection ratio (CMRR) is greater than 130dB, and the power supply rejection ratio (PSRR) is greater than 114dB under various temperature and process corners. At room temperature, the quiescent power consumption is 1.5mW, and the circuit demonstrates good robustness. The circuit has low power consumption and has significant application value in bandgap reference circuits and active filter circuits.
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48

Ding, Bingxiao, Yangmin Li, Xiao Xiao, and Zhigang Wu. "Design and analysis of a flexure-based modular precision positioning stage with two different materials." Multidiscipline Modeling in Materials and Structures 14, no. 3 (2018): 516–29. http://dx.doi.org/10.1108/mmms-10-2016-0049.

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Purpose Generally, the motion range of the micro scale operation is within several hundreds of microns, and the conventional joints cannot satisfy the requirements due to manufacturing and assembling errors, hysteresis and backlash in the joints. The paper aims to discuss these issues. Design/methodology/approach The following issues should be considered: a micromanipulation stage should be designed using a small-dimensional scale driven by the small size of piezoelectric actuator and the components can be replaced due to fatigue failure caused by repeated cyclic loading. This paper proposes a modular design of a flexure-based 2-DOF precision stage made using aluminum (T6-7075) material and Acrylonitrile Butadiene Styrene plastic material. The piezoelectric actuator is adopted to drive the stage for the fast response and large output force. To compensate the stroke of piezoelectric actuator, a bridge-type amplifier is designed with optimized structure. Findings The simulation results validate the advantages of modular positioning stage fabricated by two different materials. Research limitations/implications The stage can be used in micro scale precision’s applications. If it will be used in nanoscale precision, then some sensors in nanoscale of measurement should be used. Practical implications The designed stage can be used in biomedical engineering, such as cell injection testing, etc. Social implications The designed stage will be used in micro/nanoengineering field, such as micro/nanomanufacturing or assembly, manipulation of cell, etc., which will push forward high technology to a higher level. Originality/value Two kinds of materials have been selected to make the positioning stage, which are seldomly found in literature on compliant mechanism field. A modular design concept is proposed for the positioning stage design.
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49

Reeve, Stephanie M., Pablo Gainza, Kathleen M. Frey, Ivelin Georgiev, Bruce R. Donald, and Amy C. Anderson. "Protein design algorithms predict viable resistance to an experimental antifolate." Proceedings of the National Academy of Sciences 112, no. 3 (2014): 749–54. http://dx.doi.org/10.1073/pnas.1411548112.

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Methods to accurately predict potential drug target mutations in response to early-stage leads could drive the design of more resilient first generation drug candidates. In this study, a structure-based protein design algorithm (K* in the OSPREY suite) was used to prospectively identify single-nucleotide polymorphisms that confer resistance to an experimental inhibitor effective against dihydrofolate reductase (DHFR) from Staphylococcus aureus. Four of the top-ranked mutations in DHFR were found to be catalytically competent and resistant to the inhibitor. Selection of resistant bacteria in vitro reveals that two of the predicted mutations arise in the background of a compensatory mutation. Using enzyme kinetics, microbiology, and crystal structures of the complexes, we determined the fitness of the mutant enzymes and strains, the structural basis of resistance, and the compensatory relationship of the mutations. To our knowledge, this work illustrates the first application of protein design algorithms to prospectively predict viable resistance mutations that arise in bacteria under antibiotic pressure.
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YAVARI, MOHAMMAD. "ACTIVE-FEEDBACK SINGLE MILLER CAPACITOR FREQUENCY COMPENSATION TECHNIQUES FOR THREE-STAGE AMPLIFIERS." Journal of Circuits, Systems and Computers 19, no. 07 (2010): 1381–98. http://dx.doi.org/10.1142/s0218126610006712.

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This paper presents two novel active-feedback single Miller capacitor frequency compensation techniques for low-power three-stage amplifiers. These techniques include the active-feedback single Miller capacitor frequency compensation (AFSMC) and the dual active-feedback single Miller capacitor frequency compensation (DAFSMC). In the proposed techniques, only one Miller capacitor in series with a current buffer is utilized. The main advantages of the proposed three-stage amplifiers are the enhanced unity-gain bandwidth and the reduced silicon area. Small-signal analyses are performed and the design equations are obtained. Extensive HSPICE simulation results are provided to show the usefulness of the proposed AFSMC and DAFSMC amplifiers in both large and small capacitive loads.
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