Dissertations / Theses on the topic 'Ultra low background techniques'

As the gap between processor and memory speeds increases, memory latencies have become a critical bottleneck for computing performance. To reduce this bottleneck, designers have been working on techniques to hide these latencies. On the other hand, design of embedded processors typically targets low cost and low power consumption. Therefore, techniques which can satisfy these constraints are more desirable for embedded domains. While out-of-order execution, aggressive speculation, and complex branch prediction algorithms can help hide the memory access latency in high-performance systems, yet they can cost a heavy power budget and are not suitable for embedded systems. Prefetching is another popular method for hiding the memory access latency, and has been studied very well for high-performance processors. Similarly, for embedded processors with strict power requirements, the application of complex prefetching techniques is greatly limited, and therefore, a low power/energy solution is mostly desired in this context. In this work, we focus on instruction prefetching for ultra-low power processing architectures and aim to reduce energy overhead of this operation by proposing a combination of simple, low-cost, and energy efficient prefetching techniques. We study a wide range of applications from cryptography to computer vision and show that our proposed mechanisms can effectively improve the hit-rate of almost all of them to above 95%, achieving an average performance improvement of more than 2X. Plus, by synthesizing our designs using the state-of-the-art technologies we show that the prefetchers increase system’s power consumption less than 15% and total silicon area by less than 1%. Altogether, a total energy reduction of 1.9X is achieved, thanks to the proposed schemes, enabling a significantly higher battery life.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2004.
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Includes bibliographical references (p. 165-169).
In a number of emerging applications such as wireless sensor networks, system lifetime depends on the energy efficiency of computation and communication. The key metric in such applications is the energy dissipated per function rather than traditional ones such as clock speed or silicon area. Hardware designs are shifting focus toward enabling energy-awareness, allowing the processor to be energy-efficient for a variety of operating scenarios. This is in contrast to conventional low-power design, which optimizes for the worst-case scenario. Here, three energy-quality scalable hooks are designed into a real-valued FFT processor: variable FFT length (N=128 to 1024 points), variable bit precision (8,16 bit), and variable voltage supply with variable clock frequency (VDD=1 80mV to 0.9V, and f=164Hz to 6MHz). A variable-bit-precision and variable-FFT-length scalable FFT ASIC using an off-the-shelf standard-cell logic library and memory only scales down to 1V operation. Further energy savings is achieved through ultra-low voltage-supply operation. As performance requirements are relaxed, the operating voltage supply is scaled down, possibly even below the threshold voltage into the subthreshold region. When lower frequencies cause leakage energy dissipation to exceed the active energy dissipation, there is an optimal operating point for minimizing energy consumption.
(cont.) Logic and memory design techniques allowing ultra-low voltage operation are employed to study the optimal frequency/voltage operating point for the FFT. A full-custom implementation with circuit techniques optimized for deep voltage scaling into the subthreshold regime, is fabricated using a standard CMOS 0.18[mu]m logic process and functions down to 180mV. At the optimal operating point where the voltage supply is 350mV, the FFT processor dissipates 155nJ/FFT. The custom FFT is 8x more energy-efficient than the ASIC implementation and 350x more energy-efficient than a low-power microprocessor implementation.
by Alice Wang.
Ph.D.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Paul Hasler; Committee Co-Chair: David V. Anderson. Part of the SMARTech Electronic Thesis and Dissertation Collection.

La radio impulsionnelle UWB (IR-UWB) est une technologie de communication relativement récente, qui apporte une solution intéressante au problème de l’encombrement du spectre RF, et qui répond aux exigences de haut débit et localisation précise d’un nombre croissant d’applications, telles que les communications indoor, les réseaux de capteurs personnels et corporels, l’IoT, etc. Ses caractéristiques uniques sont obtenues par la transmission d’impulsions de très courte durée (inférieure à 1 ns), occupant une largeur de bande allant jusqu’à 7,5 GHz, et ayant une densité spectrale de puissance extrêmement faible (inférieure à -43 dBm/MHz). Les meilleures performances d’un système IR-UWB sont obtenues avec des récepteurs cohérents de type Rake, au prix d’une complexité accrue, due notamment à l’étape d’estimation du canal UWB, caractérisé par de nombreux trajets multiples. Cette étape de traitement nécessite l’estimation d’un ensemble de composantes spectrales du signal reçu, sans pouvoir faire appel aux techniques d’échantillonnage usuelles, en raison d’une limite de Nyquist particulièrement élevée (plusieurs GHz).Dans le cadre de cette thèse, nous proposons de nouvelles approches, à faible complexité, pour l’estimation du canal UWB, basées sur la représentation parcimonieuse du signal reçu, la théorie de l’acquisition compressée, et les méthodes de reconstruction des signaux à taux d’innovation fini. La réduction de complexité ainsi obtenue permet de diminuer de manière significative le coût d’implémentation du récepteur IR-UWB et sa consommation. D’abord, deux schémas d’échantillonnage compressé, monovoie (filtre SoS) et multivoie (MCMW) identifiés dans la littérature sont étendus au cas des signaux UWB ayant un spectre de type passe-bande, en tenant compte de leur implémentation réelle dans le circuit. Ces schémas permettent l’acquisition des coefficients spectraux du signal reçu et l’échantillonnage à des fréquences très réduites ne dépendant pas de la bande passante des signaux, mais seulement du nombre des trajets multiples du canal UWB. L’efficacité des approches proposées est démontrée au travers de deux applications : l’estimation du canal UWB pour un récepteur Rake cohérent à faible complexité, et la localisation précise en environnement intérieur dans un contexte d’aide à la dépendance.En outre, afin de réduire la complexité de l’approche multivoie en termes de nombre de voies nécessaires pour l’estimation du canal UWB, nous proposons une architecture à nombre de voies réduit, en augmentant le nombre d’impulsions pilotes émises.Cette même approche permet aussi la réduction de la fréquence d’échantillonnage associée au schéma MCMW. Un autre objectif important de la thèse est constitué par l’optimisation des performances des approches proposées. Ainsi, bien que l’acquisition des coefficients spectraux consécutifs permette une mise en oeuvre simple des schémas multivoie, nous montrons que les coefficients ainsi choisis, ne donnent pas les performances optimales des algorithmes de reconstruction. Ainsi, nous proposons une méthode basée sur la cohérence des matrices de mesure qui permet de trouver l’ensemble optimal des coefficients spectraux, ainsi qu’un ensemble sous-optimal contraint où les positions des coefficients spectraux sont structurées de façon à faciliter la conception du schéma MCMW. Enfin, les approches proposées dans le cadre de cette thèse sont validées expérimentalement à l’aide d’une plateforme expérimentale UWB du laboratoire Lab-STICC CNRS UMR 6285
Ultra-wideband impulse radio (IR-UWB) is a relatively new communication technology that provides an interesting solution to the problem of RF spectrum scarcity and meets the high data rate and precise localization requirements of an increasing number of applications, such as indoor communications, personal and body sensor networks, IoT, etc. Its unique characteristics are obtained by transmitting pulses of very short duration (less than 1 ns), occupying a bandwidth up to 7.5 GHz, and having an extremely low power spectral density (less than -43 dBm / MHz). The best performances of an IR-UWB system are obtained with Rake coherent receivers, at the expense of increased complexity, mainly due to the estimation of UWB channel, which is characterized by a large number of multipath components. This processing step requires the estimation of a set of spectral components for the received signal, without being able to adopt usual sampling techniques, because of the extremely high Nyquist limit (several GHz).In this thesis, we propose new low-complexity approaches for the UWB channel estimation, relying on the sparse representation of the received signal, the compressed sampling theory, and the reconstruction of the signals with finite rate of innovation. The complexity reduction thus obtained makes it possible to significantly reduce the IR-UWB receiver cost and consumption. First, two existent compressed sampling schemes, single-channel (SoS) and multi-channel (MCMW), are extended to the case of UWB signals having a bandpass spectrum, by taking into account realistic implementation constraints. These schemes allow the acquisition of the spectral coefficients of the received signal at very low sampling frequencies, which are not related anymore to the signal bandwidth, but only to the number of UWB channel multipath components. The efficiency of the proposed approaches is demonstrated through two applications: UWB channel estimation for low complexity coherent Rake receivers, and precise indoor localization for personal assistance and home care.Furthermore, in order to reduce the complexity of the MCMW approach in terms of the number of channels required for UWB channel estimation, we propose a reduced number of channel architecture by increasing the number of transmitted pilot pulses. The same approach is proven to be also useful for reducing the sampling frequency associated to the MCMW scheme.Another important objective of this thesis is the performance optimization for the proposed approaches. Although the acquisition of consecutive spectral coefficients allows a simple implementation of the MCMW scheme, we demonstrate that it not results in the best performance of the reconstruction algorithms. We then propose to rely on the coherence of the measurement matrix to find the optimal set of spectral coefficients maximizing the signal reconstruction performance, as well as a constrained suboptimal set, where the positions of the spectral coefficients are structured so as to facilitate the design of the MCMW scheme. Finally, the approaches proposed in this thesis are experimentally validated using the UWB equipment of Lab-STICC CNRS UMR 6285

L’accroissement du champ d’application et de la performance des microcontrôleurs s’accompagne d’une augmentation de la puissance consommée limitant l’autonomie des systèmes nomades (smartphones, tablettes, ordinateurs portables, implants biomédicaux, …). L’étude menée dans le cadre de la thèse, consiste à réduire la consommation dynamique des circuits fabriqués en technologie CMOS 80 nm avec mémoire non-volatile embarquée (e-NVM) ; à travers l’amélioration des performances des transistors MOS. Pour augmenter la mobilité des porteurs de charge, des techniques de fabrication utilisées dans les nœuds les plus avancés (40 nm, 32 nm) sont d’abord étudiées en fonction de différents critères (intégration, coût, gain en courant/performance). Celles sélectionnées sont ensuite optimisées et adaptées pour être embarquées sur une plate-forme e-NVM 80 nm. L’étape suivante est d’étudier comment transformer le gain en courant, en gain sur la consommation dynamique, sans dégrader la consommation statique. Les approches utilisées ont été de réduire la tension d’alimentation et la largeur des transistors. Un gain en consommation dynamique supérieur à 20 % est démontré sur des oscillateurs en anneau et sur un circuit numérique conçu avec près de 20 000 cellules logiques. La méthodologie appliquée sur le circuit a permis de réduire automatiquement la taille des transistors (évitant ainsi une étape de conception supplémentaire). Enfin, une dernière étude consiste à optimiser la consommation, les performances et la surface des cellules logiques à travers des améliorations de conception et une solution permettant de réduire l’impact de la contrainte induite par l’oxyde STI
The increase of the scope of application and the performance of microcontrollers is accompanied by an increase in power consumption reducing the life-time of mobile systems (smartphones, tablets, laptops, biomedical implants, …). Here, the work consists of reducing the dynamic consumption of circuits manufactured in embedded non-volatile memories (e-NVM) CMOS 80 nm technology by improving the performance of MOS transistors. In order to increase the carriers’ mobility, manufacturing techniques used in the most advanced technological nodes (40 nm, 32 nm) are firstly studied according to different criteria (process integration, cost, current/performance gain). Then, selected techniques are optimized and adapted to be used on an e-NVM technological platform. The next step is to study how to transform the current gain into dynamic power gain without impacting the static consumption. To do so, the supply voltage and the transistor widths are reduced. Up to 20 % in dynamic current gain is demonstrated using ring oscillators and a digital circuit designed with 20,000 standard cells. The methodology applied on the circuit allows automatic reduction to all transistor widths without additional design modifications. Finally, a last study is performed in order to optimize the consumption, the performance and the area of digital standard cells through design improvements and by reducing the mechanical stress of STI oxide

La matière sombre compte pour 85% de la matière composant l’univers et nous ne savons toujours pas ce qu’elle est. Depuis plusieurs années, l’expérience Picasso, maintenant devenue l’expérience PICO, tente d’élucider ce mystère. Les fréons de la famille des CXFY sont utilisés comme cibles de choix dans les détecteurs à liquides surchauffés de l’expérience PICO. Situés à SNOLab, en Ontario, ces détecteurs font parties des plus performant de la recherche de la matière sombre. Lors d’interactions de particules avec le liquide en surchauffe, un changement de phase est induit par le dépôt d’énergie engendré par l’interaction. Les bulles créées par l’évènement sont alors détectées par différents capteurs afin de déterminer le type d’interaction qui a eu lieu. Dans ce travail seront présentés les détecteurs à liquides surchauffés dans le cadre de la recherche de la matière sombre. Principalement, nous y verrons trois types de détecteurs utilisés par les expériences PICO et Picasso. Le principe de fonctionnement de chacun des détecteurs sera exposé en premier lieu ainsi que leur fabrication, puis leur mode d’opération et l’analyse des données. Les méthodes de calibration seront par la suite expliquées pour terminer avec une description des résultats obtenus démontrant la performance de ce type de détection.
Dark matter makes up 85% of the matter content of the universe and we still don’t know what it is made of. The Picasso experiment, now named PICO, has been searching for it for several years with the use of superheated liquid detectors. Following the interaction of a particle with a superheated liquid freon of the CXFY family, a bubble is formed through a phase change and is detected with several types of sensors, telling us about the nature of the event. Located at SNOLab, in Ontario, these detectors produce some of the best results in the field. The present work will go through three types of superheated liquid detectors. A full description of the working principles will be presented for each of them. In addition, the fabrication, the operation mode and the data analysis will be shown. Detector calibration techniques will then be presented with different particle sources. Finally, the most recent results will be discussed, demonstrating the performance of the superheated liquid detector technique.

abstract: Modern day deep sub-micron SOC architectures often demand very low supply noise levels. As supply voltage decreases with decreasing deep sub-micron gate length, noise on the power supply starts playing a dominant role in noise-sensitive analog blocks, especially high precision ADC, PLL, and RF SOC's. Most handheld and portable applications and highly sensitive medical instrumentation circuits tend to use low noise regulators as on-chip or on board power supply. Nonlinearities associated with LNA's, mixers and oscillators up-convert low frequency noise with the signal band. Specifically, synthesizer and TCXO phase noise, LNA and mixer noise figure, and adjacent channel power ratios of the PA are heavily influenced by the supply noise and ripple. This poses a stringent requirement on a very low noise power supply with high accuracy and fast transient response. Low Dropout (LDO) regulators are preferred over switching regulators for these applications due to their attractive low noise and low ripple features. LDO's shield sensitive blocks from high frequency fluctuations on the power supply while providing high accuracy, fast response supply regulation. This research focuses on developing innovative techniques to reduce the noise of any generic wideband LDO, stable with or without load capacitor. The proposed techniques include Switched RC Filtering to reduce the Bandgap Reference noise, Current Mode Chopping to reduce the Error Amplifier noise & MOS-R based RC filter to reduce the noise due to bias current. The residual chopping ripple was reduced using a Switched Capacitor notch filter. Using these techniques, the integrated noise of a wideband LDO was brought down to 15µV in the integration band of 10Hz to 100kHz. These techniques can be integrated into any generic LDO without any significant area overhead.
Dissertation/Thesis
Masters Thesis Electrical Engineering 2014

Prometheus I, a low-energy ($\sim$0.06-12.0 MeV), balloon-borne gamma ray telescope has been developed and successfully flown. It consists of a central NaI(Tl) detector that is segmented into an array of 9 x 9 crystals and an active anticoincidence shield of thick plastic scintillator. Implemented on Prometheus are several background reduction techniques which allow it to be 10 times more sensitive to aperture gamma rays than previous generations of low-energy gamma ray telescopes. First, a $\beta$ ray rejection method is used. Next, a low-Z shield minimizes cosmic ray activation. Also layers of Li$\sp6$ absorb slow neutrons, thereby reducing background caused from inelastic neutron scattering and neutron capture. Finally the use of lightweight, low-Z construction materials minimizes locally produced background. Semi-analytical calculations and preliminary in-flight count rate data confirm the usefulness of these techniques.

The major limiting factor of DRAM access time is the low transconductance of the MOSFET's which have only limited current drive capability. The bipolar junction transistor(BJT) has a collector current amplification factor, ��, times base current and is limited mostly by the willingness to supply this base current. This collector current is much larger than the MOSFET drain current under similar conditions. The requirements for low power and low power densities results in lower power supply voltages which are also inconsistent with the threshold voltage variations in CMOS technology, as a consequence at least pulsed body bias or synchronous body bias will probably be utilized. Given that of the CMOS body will be driven or the CMOS gate and body connected a BJT technique is proposed for ultra low voltages like Vdd=0.5. Utilizing present CMOS process technology good results can be achieved with ultra low power using gate-body connected transistors and a current sense amplifier.
Graduation date: 1999

碩士
國立交通大學
電機學院電信學程
100
This thesis discusses the design and analysis of an ultra wideband low noise amplifier. It has the advantage of high gain, high linearity, low noise, low power consumption and small chip size. The ultra wideband low noise amplifier was implemented in TSMC 0.18 um CMOS technology and based on the cascode resistive feedback architecture with bandwidth extension by series peaking inductor. The first part introduces series LC band pass filter to achieve input matching. The second part introduces resistive feedback with series inductive peaking configuration to extend bandwidth and gain. The measured bandwidth of the low noise amplifier covers UWB 3.1-10.6GHz and within this band the gain is 8 ~12.5 dB, the noise figure is 2.9 ~ 4.3 dB, the input return loss is below -10.0 dB, the output return loss is below -10.0 dB. The input third intercept point(IIP3) measured at 6.8GHz is +5.0 dBm, the input power at 1dB gain compression point(P1dB) at 6.8GHz is -5.5 dBm. This low noise amplifier consumes 18 mW from a 1.5 V power supply. The chip size included pad is 0.68 mm2.

碩士
國立臺灣大學
地理環境資源學研究所
103
Throughout worldwide, earthquakes have deprived lots of life and property. However, earthquakes cannot be predicted precisely in terms of the epicenter, time, seismic scale, and depth with various means. Most of errors were caused by misleading signal processing. The goal of this study provide a better signal processing method to depict the potential zone of seismic epicenter. In order to realize the significant signal and frequency, this study utilizes Fast Fourier Transform (FFT) to analyze Ultra Low Frequency (ULF) signals and define a warning line for dividing normal and abnormal signals. In this study, an epicenter location can be inferred by intersection of at least three abnormal angles from different stations. In addition, epicenter estimation analysis imports probability buffer concept in spatial cross analysis, moreover, this concept also applies in depth estimation. Break time estimation concludes both lots of papers information and abnormal signal pattern, so this study define that break time of earthquake is one week after abnormal signal appearance. For magnitude regression, this study utilizes three different parameter, MAEQ, MMEQ and IAEQ, to regress the correlation with Richter magnitude scale. Up to day, this study has successfully found significant signal of earthquake precursors and also calculated the potential zone of seismic epicenter, break time, depth potential and magnitude beforehand. In conclusion, this research provides a new method for epicenter prediction by analyzing ULF electromagnetic signals.

With the prevalence of smartphones, pedestrians and joggers today often walk or run while listening to music. Since they are deprived of auditory stimuli that could provide important cues to dangers, they are at a much greater risk of being hit by cars or other vehicles. We start this research into building a wearable system that uses multichannel audio sensors embedded in a headset to help detect and locate cars from their honks and engine and tire noises. Based on this detection, the system can warn pedestrians of the imminent danger of approaching cars. We demonstrate that using a segmented architecture and implementation consisting of headset-mounted audio sensors, front-end hardware that performs signal processing and feature extraction, and machine-learning-based classification on a smartphone, we are able to provide early danger detection in real time, from up to 80m distance, with greater than 80% precision and 90% recall, and alert the user on time (about 6s in advance for a car traveling at 30mph). The time delay between audio signals in a microphone array is the most important feature for sound-source localization. This work also presents a polarity-coincidence, adaptive time-delay estimation (PCC-ATDE) mixed-signal technique that uses 1-bit quantized signals and a negative-feedback architecture to directly determine the time delay between signals in the analog inputs and convert it to a digital number. This direct conversion, without a multibit ADC and further digital-signal processing, allows for ultra low power consumption. A prototype chip in 0:18μm CMOS with 4 analog inputs consumes 78nW with a 3-channel 8-bit digital time-delay output while sampling at 50kHz with a 20μs resolution and 6.06 ENOB. We present a theoretical analysis for the nonlinear, signal-dependent feedback loop of the PCC-ATDE. A delay-domain model of the system is developed to estimate the power bandwidth of the converter and predict its dynamic response. Results are validated with experiments using real-life stimuli, captured with a microphone array, that demonstrate the technique’s ability to localize a sound source. The chip is further integrated in an embedded platform and deployed as an audio-based vehicle-bearing IoT system. Finally, we investigate the signal’s envelope, an important feature for a host of applications enabled by machine-learning algorithms. Conventionally, the raw analog signal is digitized first, followed by feature extraction in the digital domain. This work presents an ultra-low-power envelope-to-digital converter (EDC) consisting of a passive switched-capacitor envelope detector and an inseparable successive approximation-register analog-to-digital converter (ADC). The two blocks integrate directly at different sampling rates without a buffer between them thanks to the ping-pong operation of their sampling capacitors. An EDC prototype was fabricated in 180nm CMOS. It provides 7.1 effective bits of ADC resolution and supports input signal bandwidth up to 5kHz and an envelope bandwidth up to 50Hz while consuming 9.6nW.

碩士
國立臺灣大學
地理環境資源學研究所
107
With growing instability of spatial and temporal precipitation variability and water supply in Taiwan, utilizing alternative water sources is one of the important trends in water resources development. Understanding that hyporheic water is one of the resources that has the characteristics of slow flow velocity, low turbidity, high water quality and low ecological impact, it has a great potential to be utilized. However, the researches about hyporheic water are mainly focused on the interrelationships between the hyporheic zone and its biological ecosystem. The researches about utilizing hyporheic water are relatively insufficient and the potential water content can’t be effectively estimated. Therefore, the purpose of this study is to propose an innovative procedure to investigate distribution of the hyporheic zone and to verify the results by comparing with ground truth data. We also made measurements in wet and dry seasons to see the time series change. The results show that by applying Ultra Low Frequency Electromagnetic Wave Remote Sensing techniques, in most cases the stratigraphic section identified in the study successfully matched the ground true well data and hydrogeological conceptual model. The hyporheic zone lies between riverbed and aquitard 1 (-4m~-38m) and the optimal water intake area lies in gravel layer of aquifer 1 (-24m~-34m). The resistivity profiles of wet and dry seasons show significant difference owing to precipitation variability. In conclusion, this study provides an effective way to evaluate hyporheic zone in southern Taiwan. We hope that this study can contribute to practical hyporheic water resources development project.

The last two decades have witnessed the CMOS processes and design techniques develop and prosper with unprecedented speed. They have been widely employed in contemporary integrated circuit (IC) commercial products resulting in highly added value. Tremendous e orts have been devoted to extend and optimize the CMOS process and its application for future wireless communication systems. Meanwhile, the last twenty years have also seen the fast booming of the wireless communication technology typically characterized by the mobile communication technology, WLAN technology, WPAN technology, etc. Nowadays, the spectral resource is getting increasingly scarce, particularly over the frequency from 0.7 to 6 GHz, whether the employed frequency band is licensed or not. To combat this dilemma, the ultra wideband (UWB) technology emerges to provide a promising solution for short-range wireless communication while using an unlicensed wide band in an overlay manner. Another trend of obtaining more spectrum is moving upwards to higher frequency bands. The WiFi-Alliance has already developed a certi cation program of the 60-GHz band. On the other side, millimeterwave (mmWave) frequency bands such as 28-GHz, 38-GHz, and 71-GHz are likely to be licensed for next generation wireless communication networks. This new trend poses both a challenge and opportunity for the mmWave integrated circuits design. This thesis combines the state-of-the-art IC and hardware technologies and design techniques to implement and propose UWB and 5G prototyping systems. First of all, by giving a thorough analysis of a transmitted reference pulse cluster (TRPC) scheme and mathematical modeling, a TRPC-UWB transceiver structure is proposed and its features and speci cations are derived. Following that, the detailed design, fabrication and veri cation of the TRPC-UWB transmitter front end and wideband voltage-controlled oscillators (VCOs) in CMOS process is presented. The TRPCUWB transmitter demonstrates a state-of-the-art energy e ciency of 38.4 pJ/pulse. Secondly, a novel system architecture named distributed phased array based MIMO (DPA-MIMO) is proposed as a solution to overcome design challenges for the future 5G cellular user equipment (UE) design. In addition, a prototyping design of on-chip mmWave antenna with radiation e ciency enhancement is presented for the IEEE 802.11ad application. Furthermore, two wideband K-band VCO prototypes based on two di erent topologies are designed and fabricated in a standard CMOS process. They both show good performance at center frequencies of 22.3 and 26.1 GHz. Finally, two CMOS mmWave VCO prototypes working at the potential future 5G frequency bands are presented with measurement results.
Graduate
2018-04-30
amenghym@gmail.com

Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques.
Graduation date: 2013
Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014

碩士
國立交通大學
電機工程學系
103
For many electrical devices in our day life, power supply designed by an isolated converter is indispensable. Especially in low output power applications, the flyback converter is a better candidate. This thesis presents an AC/DC power module by designing an adapter for high efficiency laptops. The proposed overall power management (OPM) in laptops can improve the overall conversion efficiency by the flexible voltage scaling (FVS) technique in cooperation with conventional dynamic voltage scaling (DVS) technique. 12% light load efficiency and 7% peak efficiency are improved compared to conventional design with DVS technique only but without the FVS technique. The proposed green mode effectively reduces chip quiescent current to 11μA and suppresses ultra-light load power loss to 10mW, which is much smaller than 500mW standby power defined by the restriction of Energy Star Standard and 40mW of state-of-the-art commercial products.