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Journal articles on the topic 'Ultra-scaled MOSFET'

Author: Grafiati

Published: 4 June 2021

Last updated: 1 February 2022

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1

Osintsev, Dmitry, V. Sverdlov, and Siegfried Selberherr. "Acoustic Phonon and Surface Roughness Spin Relaxation Mechanisms in Strained Ultra-Scaled Silicon Films." Advanced Materials Research 854 (November 2013): 29–34. http://dx.doi.org/10.4028/www.scientific.net/amr.854.29.

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We consider the impact of the surface roughness and phonon induced relaxation on transport and spin characteristics in ultra-thin SOI MOSFET devices. We show that the regions in the momentum space, which are responsible for strong spin relaxation, can be efficiently removed by applying uniaxial strain. The spin lifetime in strained films can be improved by orders of magnitude, while the momentum relaxation time determining the electron mobility can only be increased by a factor of two.

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2

Ahangari, Zahra, and Morteza Fathipour. "Band structure effect on the electron current oscillation in ultra-scaled GaSb Schottky MOSFET: tight-binding approach." Journal of Computational Electronics 13, no. 2 (2013): 375–82. http://dx.doi.org/10.1007/s10825-013-0544-x.

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3

Singh, Vikram, Satinder K. Sharma, Dinesh Kumar, and R. K. Nahar. "Study of rapid thermal annealing on ultra thin high-k HfO2 films properties for nano scaled MOSFET technology." Microelectronic Engineering 91 (March 2012): 137–43. http://dx.doi.org/10.1016/j.mee.2011.09.005.

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4

Gupta, M. "Ballistic MOSFETs, the ultra scaled transistors." IEEE Potentials 21, no. 5 (2002): 13–16. http://dx.doi.org/10.1109/mp.2002.1166619.

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5

Saltin, Johan, Nguyen Cong Dao, Philip H. W. Leong, and Hiu Yung Wong. "Energy Filtering Effect at Source Contact on Ultra-Scaled MOSFETs." IEEE Journal of the Electron Devices Society 8 (2020): 662–67. http://dx.doi.org/10.1109/jeds.2020.2981251.

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6

TAKAGI, SHIN-ICHI. "OPTIMIZED DESIGN OF THE SUBBAND STRUCTURE IN MOS INVERSION LAYERS FOR REALIZING HIGH PERFORMANCE AND LOW POWER Si MOSFETS." International Journal of High Speed Electronics and Systems 10, no. 01 (2000): 155–70. http://dx.doi.org/10.1142/s0129156400000192.

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Enhancement of inversion-layer mobility becomes more important in scaled CMOS from the viewpoints of both higher performance and lower power consumption. The severe influence of inversion-layer capacitance prevents MOSFETs with ultra-thin gate oxides from operating at low supply voltage. This paper presents an engineering scenario of the subband structure in the inversion layer for the enhancement of electron mobility in n-MOSFETs. A key factor is to enlarge the difference in the subband energies of the two-fold and four-fold valleys and, as a result, the electron occupancy of the two-fold val

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7

Othman, Noraini, Mohd Khairuddin Md Arshad, Syarifah Norfaezah Sabki, and U. Hashim. "Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs on Suppression of Short-Channel Effects (SCEs): A Review." Advanced Materials Research 1109 (June 2015): 257–61. http://dx.doi.org/10.4028/www.scientific.net/amr.1109.257.

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This paper reviews the different UTBB SOI MOSFET structures and their superiority in suppressing short-channel effects (SCEs). As the gate length (Lg), buried oxide thickness (TBOX) and silicon thickness (Tsi) are scaled down, the severity of SCEs becomes significant. The different UTBB SOI MOSFET device structures introduced to suppress these SCEs are discussed. The effectiveness of these structures in managing the associated SCEs such as drain-induced barrier lowering (DIBL), subthreshold swing (SS) and off-state leakage current (Ioff) is also presented. Further evaluations are made on other

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8

Salmani-Jelodar, Mehdi, Hesameddin Ilatikhameneh, Sungguen Kim, Kwok Ng, Prasad Sarangapani, and Gerhard Klimeck. "Optimum High-k Oxide for the Best Performance of Ultra-Scaled Double-Gate MOSFETs." IEEE Transactions on Nanotechnology 15, no. 6 (2016): 904–10. http://dx.doi.org/10.1109/tnano.2016.2583411.

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9

Kalra, Shruti, та A. B. Bhattacharyya. "An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α-Power MOSFET Model". Journal of Integrated Circuits and Systems 11, № 1 (2016): 57–68. http://dx.doi.org/10.29292/jics.v11i1.430.

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Aggressive technological scaling continues to drive ultra-large-scale-integrated chips to higher clock speed. This causes large power consumption leading to considerable thermal generation and on-chip temperature gradient. Though much of the research has been focused on low power design, thermal issues still persist and need attention for enhanced integrated circuit reliability. The present paper outlines a methodology for a first hand estimating effect of temperature on basic CMOS building blocks at ultra deep submicron technology nodes utilizing modified α-power law based MOSFET model. The g

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10

Kaharudin, K. E., F. Salehuddin, A. S. M. Zain, and Ameer F. Roslan. "Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 4 (2019): 2863. http://dx.doi.org/10.11591/ijece.v9i4.pp2863-2873.

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The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. Th

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11

Illarionov, Yury Yu, Markus Bina, Stanislav E. Tyaginov, and Tibor Grasser. "An analytical approach for the determination of the lateral trap position in ultra-scaled MOSFETs." Japanese Journal of Applied Physics 53, no. 4S (2014): 04EC22. http://dx.doi.org/10.7567/jjap.53.04ec22.

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12

Velayudhan, V., F. Gamiz, J. Martin-Martinez, R. Rodriguez, M. Nafria, and X. Aymerich. "Influence of the interface trap location on the performance and variability of ultra-scaled MOSFETs." Microelectronics Reliability 53, no. 9-11 (2013): 1243–46. http://dx.doi.org/10.1016/j.microrel.2013.07.052.

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13

Sverdlov, V., A. Gehring, H. Kosina, and S. Selberherr. "Quantum transport in ultra-scaled double-gate MOSFETs: A Wigner function-based Monte Carlo approach." Solid-State Electronics 49, no. 9 (2005): 1510–15. http://dx.doi.org/10.1016/j.sse.2005.07.013.

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14

Jiang, Xiang-Wei, and Shu-Shen Li. "Quantum confinement effects and source-to-drain tunneling in ultra-scaled double-gate silicon n-MOSFETs." Chinese Physics B 21, no. 2 (2012): 027304. http://dx.doi.org/10.1088/1674-1056/21/2/027304.

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15

Martín, M. J., R. Rengel, E. Pascual, J. Łusakowski, W. Knap, and T. González. "Onset of quasi-ballistic transport and mobility degradation in ultra scaled MOSFETs: a Monte Carlo study." physica status solidi (c) 5, no. 1 (2008): 123–26. http://dx.doi.org/10.1002/pssc.200776517.

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16

Chang, Jiwon. "Simulation of channel orientation dependent transport in ultra-scaled monolayer MoX2 (X = S, Se, Te) n-MOSFETs." Journal of Physics D: Applied Physics 48, no. 14 (2015): 145101. http://dx.doi.org/10.1088/0022-3727/48/14/145101.

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17

Theodorou, C. G., E. G. Ioannidis, S. Haendler, E. Josse, C. A. Dimitriadis, and G. Ghibaudo. "Low frequency noise variability in ultra scaled FD-SOI n-MOSFETs: Dependence on gate bias, frequency and temperature." Solid-State Electronics 117 (March 2016): 88–93. http://dx.doi.org/10.1016/j.sse.2015.11.011.

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18

Principato, Fabio, Saverio Altieri, Leonardo Abbene, and Francesco Pintacuda. "Accelerated Tests on Si and SiC Power Transistors with Thermal, Fast and Ultra-Fast Neutrons." Sensors 20, no. 11 (2020): 3021. http://dx.doi.org/10.3390/s20113021.

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Neutron test campaigns on silicon (Si) and silicon carbide (SiC) power MOSFETs and IGBTs were conducted at the TRIGA (Training, Research, Isotopes, General Atomics) Mark II (Pavia, Italy) nuclear reactor and ChipIr-ISIS Neutron and Muon Source (Didcot, U.K.) facility. About 2000 power transistors made by STMicroelectronics were tested in all the experiments. Tests with thermal and fast neutrons (up to about 10 MeV) at the TRIGA Mark II reactor showed that single-event burnout (SEB) failures only occurred at voltages close to the rated drain-source voltage. Thermal neutrons did not induce SEB,

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19

Ren, Shufeng, Mengwei Si, Kai Ni, et al. "Total Ionizing Dose (TID) Effects in Extremely Scaled Ultra-Thin Channel Nanowire (NW) Gate-All-Around (GAA) InGaAs MOSFETs." IEEE Transactions on Nuclear Science 62, no. 6 (2015): 2888–93. http://dx.doi.org/10.1109/tns.2015.2497090.

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20

Afzalian, Aryan. "Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors." npj 2D Materials and Applications 5, no. 1 (2021). http://dx.doi.org/10.1038/s41699-020-00181-1.

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AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to en

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21

Ahangari, Zahra. "Impact of indium mole fraction on the quantum transport of ultra-scaled In x Ga1–x As double-gate Schottky MOSFET: tight-binding approach." Applied Physics A 122, no. 2 (2016). http://dx.doi.org/10.1007/s00339-016-9629-2.

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